64 /* Empirical */) {\n // For simulation performance, we should avoid generating\n // exteremely wide shifters, so we divide and conquer.\n // Empirically, this does not impact synthesis QoR.\n val mid = numInVals / 2\n val msb = in(in.getWidth - 1)\n val lsbs = in(in.getWidth - 2, 0)\n if (mid < topBound) {\n if (mid <= bottomBound) {\n Mux(msb,\n lowMask(lsbs, topBound - mid, bottomBound - mid),\n 0.U\n )\n } else {\n Mux(msb,\n lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,\n lowMask(lsbs, mid, bottomBound)\n )\n }\n } else {\n ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))\n }\n } else {\n val shift = (BigInt(-1)<>in\n Reverse(\n shift(\n (numInVals - 1 - bottomBound).toInt,\n (numInVals - topBound).toInt\n )\n )\n }\n }\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nobject countLeadingZeros\n{\n def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nobject orReduceBy2\n{\n def apply(in: UInt): UInt =\n {\n val reducedWidth = (in.getWidth + 1)>>1\n val reducedVec = Wire(Vec(reducedWidth, Bool()))\n for (ix <- 0 until reducedWidth - 1) {\n reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR\n }\n reducedVec(reducedWidth - 1) :=\n in(in.getWidth - 1, (reducedWidth - 1) * 2).orR\n reducedVec.asUInt\n }\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nobject orReduceBy4\n{\n def apply(in: UInt): UInt =\n {\n val reducedWidth = (in.getWidth + 3)>>2\n val reducedVec = Wire(Vec(reducedWidth, Bool()))\n for (ix <- 0 until reducedWidth - 1) {\n reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR\n }\n reducedVec(reducedWidth - 1) :=\n in(in.getWidth - 1, (reducedWidth - 1) * 4).orR\n reducedVec.asUInt\n }\n}\nFile rawFloatFromIN.scala:\n/*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\n\nobject rawFloatFromIN\n{\n def apply(signedIn: Bool, in: Bits): RawFloat =\n {\n val expWidth = log2Up(in.getWidth) + 1\n//*** CHANGE THIS; CAN BE VERY LARGE:\n val extIntWidth = 1<<(expWidth - 1)\n\n val sign = signedIn && in(in.getWidth - 1)\n val absIn = Mux(sign, -in.asUInt, in.asUInt)\n val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)\n val adjustedNormDist = countLeadingZeros(extAbsIn)\n val sig =\n (extAbsIn<= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n val s1_req_rmeta = Wire(Vec(nWays, Vec(bankWidth, new BTBMeta)))\n val s1_req_rbtb = Wire(Vec(nWays, Vec(bankWidth, new BTBEntry)))\n val s1_req_rebtb = Wire(UInt(vaddrBitsExtended.W))\n\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n val s1_targs = Wire(Vec(nWays, Vec(bankWidth, UInt(vaddrBitsExtended.W))))\n for (w <- 0 until bankWidth) {\n for (b <- 0 until nWays) {\n val entry_btb = WireInit(s1_req_rbtb(b)(w))\n s1_targs(b)(w) := Mux(entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n }\n\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := s1_targs(s1_hit_ways(w))(w)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n io.resp.f1(w) := io.resp_in(0).f1(w)\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n if (params.useFlops) {\n for (w <- 0 until nWays) {\n val meta = Reg(Vec(nSets, Vec(bankWidth, new BTBMeta)))\n val btb = Reg(Vec(nSets, Vec(bankWidth, new BTBEntry)))\n s1_req_rmeta(w) := meta(s1_idx)\n s1_req_rbtb(w) := btb(s1_idx)\n for (i <- 0 until bankWidth) {\n when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {\n when (doing_reset || s1_update_wbtb_mask(i)) {\n btb(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,\n 0.U.asTypeOf(new BTBEntry), s1_update_wbtb_data)\n }\n when (doing_reset || s1_update_wmeta_mask(i)) {\n meta(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,\n 0.U.asTypeOf(new BTBMeta), s1_update_wmeta_data(i))\n }\n }\n }\n }\n val ebtb = Reg(Vec(extendedNSets, UInt(vaddrBitsExtended.W)))\n s1_req_rebtb := ebtb(s1_idx)\n\n } else {\n for (w <- 0 until nWays) {\n val meta = SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W)))\n val btb = SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W)))\n meta.suggestName(s\"btb_meta_way_${w}\")\n btb.suggestName(s\"btb_data_way_${w}\")\n s1_req_rmeta(w) := VecInit(meta.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta)))\n s1_req_rbtb(w) := VecInit(btb.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBEntry)))\n\n when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {\n btb.write(\n Mux(doing_reset, reset_idx, s1_update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wbtb_mask).asBools\n )\n meta.write(\n Mux(doing_reset, reset_idx, s1_update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wmeta_mask).asBools\n )\n }\n }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n ebtb.suggestName(s\"btb_ebtb\")\n s1_req_rebtb := ebtb.read(s0_idx, s0_valid)\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n }\n}\n"},"response":{"kind":"string","value":"module btb_data_way_1(\t// @[btb.scala:192:29]\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [55:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [55:0] W0_data,\n input [3:0] W0_mask\n);\n\n btb_data_way_0_ext btb_data_way_0_ext (\t// @[btb.scala:192:29]\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\t// @[btb.scala:192:29]\nendmodule"}}},{"rowIdx":5095,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile SynchronizerReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}\n"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_113(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire _sync_2_T = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h1;\t// @[SynchronizerReg.scala:51:87, :54:22, :68:19]\n end\n always @(posedge, posedge)"}}},{"rowIdx":5096,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncQueueSource_Phit_6(\t// @[AsyncQueue.scala:70:7]\n input clock,\t// @[AsyncQueue.scala:70:7]\n input reset,\t// @[AsyncQueue.scala:70:7]\n output io_enq_ready,\t// @[AsyncQueue.scala:73:14]\n input io_enq_valid,\t// @[AsyncQueue.scala:73:14]\n input [31:0] io_enq_bits_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_0_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_1_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_2_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_3_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_4_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_5_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_6_phit,\t// @[AsyncQueue.scala:73:14]\n output [31:0] io_async_mem_7_phit,\t// @[AsyncQueue.scala:73:14]\n input [3:0] io_async_ridx,\t// @[AsyncQueue.scala:73:14]\n output [3:0] io_async_widx,\t// @[AsyncQueue.scala:73:14]\n input io_async_safe_ridx_valid,\t// @[AsyncQueue.scala:73:14]\n output io_async_safe_widx_valid,\t// @[AsyncQueue.scala:73:14]\n output io_async_safe_source_reset_n,\t// @[AsyncQueue.scala:73:14]\n input io_async_safe_sink_reset_n\t// @[AsyncQueue.scala:73:14]\n);\n\n wire _sink_extend_io_out;\t// @[AsyncQueue.scala:105:30]\n wire _source_valid_0_io_out;\t// @[AsyncQueue.scala:102:32]\n wire io_enq_valid_0 = io_enq_valid;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_ridx_0 = io_async_ridx;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n;\t// @[AsyncQueue.scala:70:7]\n wire _widx_T = reset;\t// @[AsyncQueue.scala:83:30]\n wire _ready_reg_T = reset;\t// @[AsyncQueue.scala:90:35]\n wire _widx_reg_T = reset;\t// @[AsyncQueue.scala:93:34]\n wire _source_valid_0_reset_T = reset;\t// @[AsyncQueue.scala:107:36]\n wire _source_valid_1_reset_T = reset;\t// @[AsyncQueue.scala:108:36]\n wire _sink_extend_reset_T = reset;\t// @[AsyncQueue.scala:109:36]\n wire _sink_valid_reset_T = reset;\t// @[AsyncQueue.scala:110:35]\n wire _io_async_safe_source_reset_n_T = reset;\t// @[AsyncQueue.scala:123:34]\n wire _io_enq_ready_T;\t// @[AsyncQueue.scala:91:29]\n wire _io_async_safe_source_reset_n_T_1;\t// @[AsyncQueue.scala:123:27]\n wire io_enq_ready_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_0_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_1_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_2_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_3_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_4_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_5_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_6_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire [31:0] io_async_mem_7_phit_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_widx_valid_0;\t// @[AsyncQueue.scala:70:7]\n wire io_async_safe_source_reset_n_0;\t// @[AsyncQueue.scala:70:7]\n wire [3:0] io_async_widx_0;\t// @[AsyncQueue.scala:70:7]\n wire sink_ready;\t// @[AsyncQueue.scala:81:28]\n reg [31:0] mem_0_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_0_phit_0 = mem_0_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_1_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_1_phit_0 = mem_1_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_2_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_2_phit_0 = mem_2_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_3_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_3_phit_0 = mem_3_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_4_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_4_phit_0 = mem_4_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_5_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_5_phit_0 = mem_5_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_6_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_6_phit_0 = mem_6_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n reg [31:0] mem_7_phit;\t// @[AsyncQueue.scala:82:16]\n assign io_async_mem_7_phit_0 = mem_7_phit;\t// @[AsyncQueue.scala:70:7, :82:16]\n wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0;\t// @[Decoupled.scala:51:35]\n wire _widx_T_2 = ~sink_ready;\t// @[AsyncQueue.scala:81:28, :83:77]\n wire [3:0] _widx_incremented_T_2;\t// @[AsyncQueue.scala:53:23]\n wire [3:0] widx_incremented;\t// @[AsyncQueue.scala:51:27]\n reg [3:0] widx_widx_bin;\t// @[AsyncQueue.scala:52:25]\n wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1};\t// @[Decoupled.scala:51:35]\n wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0];\t// @[AsyncQueue.scala:53:43]\n assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1;\t// @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]\n assign widx_incremented = _widx_incremented_T_2;\t// @[AsyncQueue.scala:51:27, :53:23]\n wire [2:0] _widx_T_3 = widx_incremented[3:1];\t// @[AsyncQueue.scala:51:27, :54:32]\n wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3};\t// @[AsyncQueue.scala:51:27, :54:{17,32}]\n wire [3:0] ridx;\t// @[ShiftReg.scala:48:24]\n wire [3:0] _ready_T = ridx ^ 4'hC;\t// @[ShiftReg.scala:48:24]\n wire _ready_T_1 = widx != _ready_T;\t// @[AsyncQueue.scala:54:17, :85:{34,44}]\n wire ready = sink_ready & _ready_T_1;\t// @[AsyncQueue.scala:81:28, :85:{26,34}]\n wire [2:0] _index_T = io_async_widx_0[2:0];\t// @[AsyncQueue.scala:70:7, :87:52]\n wire _index_T_1 = io_async_widx_0[3];\t// @[AsyncQueue.scala:70:7, :87:80]\n wire [2:0] _index_T_2 = {_index_T_1, 2'h0};\t// @[AsyncQueue.scala:87:{80,93}]\n wire [2:0] index = _index_T ^ _index_T_2;\t// @[AsyncQueue.scala:87:{52,64,93}]\n reg ready_reg;\t// @[AsyncQueue.scala:90:56]\n assign _io_enq_ready_T = ready_reg & sink_ready;\t// @[AsyncQueue.scala:81:28, :90:56, :91:29]\n assign io_enq_ready_0 = _io_enq_ready_T;\t// @[AsyncQueue.scala:70:7, :91:29]\n reg [3:0] widx_gray;\t// @[AsyncQueue.scala:93:55]\n assign io_async_widx_0 = widx_gray;\t// @[AsyncQueue.scala:70:7, :93:55]\n wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46]\n wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1;\t// @[AsyncQueue.scala:107:{36,43,46}]\n wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2;\t// @[AsyncQueue.scala:107:{43,65}]\n wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46, :108:46]\n wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1;\t// @[AsyncQueue.scala:108:{36,43,46}]\n wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2;\t// @[AsyncQueue.scala:108:{43,65}]\n wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0;\t// @[AsyncQueue.scala:70:7, :107:46, :109:46]\n wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1;\t// @[AsyncQueue.scala:109:{36,43,46}]\n wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2;\t// @[AsyncQueue.scala:109:{43,65}]\n assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T;\t// @[AsyncQueue.scala:123:{27,34}]\n assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1;\t// @[AsyncQueue.scala:70:7, :123:27]\n always @(posedge clock) begin\t// @[AsyncQueue.scala:70:7]\n if (_widx_T_1 & index == 3'h0)\t// @[Decoupled.scala:51:35]\n mem_0_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h1)\t// @[Decoupled.scala:51:35]\n mem_1_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h2)\t// @[Decoupled.scala:51:35]\n mem_2_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h3)\t// @[Decoupled.scala:51:35]\n mem_3_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h4)\t// @[Decoupled.scala:51:35]\n mem_4_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h5)\t// @[Decoupled.scala:51:35]\n mem_5_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & index == 3'h6)\t// @[Decoupled.scala:51:35]\n mem_6_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n if (_widx_T_1 & (&index))\t// @[Decoupled.scala:51:35]\n mem_7_phit <= io_enq_bits_phit_0;\t// @[AsyncQueue.scala:70:7, :82:16]\n always @(posedge)\n always @(posedge clock or posedge _widx_T) begin\t// @[AsyncQueue.scala:70:7, :83:30]\n if (_widx_T)\t// @[AsyncQueue.scala:70:7, :83:30]\n widx_widx_bin <= 4'h0;\t// @[AsyncQueue.scala:52:25]\n else\t// @[AsyncQueue.scala:70:7]\n widx_widx_bin <= widx_incremented;\t// @[AsyncQueue.scala:51:27, :52:25]\n always @(posedge, posedge)\n always @(posedge clock or posedge _ready_reg_T) begin\t// @[AsyncQueue.scala:70:7, :90:35]\n if (_ready_reg_T)\t// @[AsyncQueue.scala:70:7, :90:35]\n ready_reg <= 1'h0;\t// @[AsyncQueue.scala:90:56]\n else\t// @[AsyncQueue.scala:70:7]\n ready_reg <= ready;\t// @[AsyncQueue.scala:85:26, :90:56]\n always @(posedge, posedge)\n always @(posedge clock or posedge _widx_reg_T) begin\t// @[AsyncQueue.scala:70:7, :93:34]\n if (_widx_reg_T)\t// @[AsyncQueue.scala:70:7, :93:34]\n widx_gray <= 4'h0;\t// @[AsyncQueue.scala:52:25, :93:55]\n else\t// @[AsyncQueue.scala:70:7]\n widx_gray <= widx;\t// @[AsyncQueue.scala:54:17, :93:55]\n always @(posedge, posedge)"}}},{"rowIdx":5097,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\n"},"response":{"kind":"string","value":"module OptimizationBarrier_TLBEntryData_66(\t// @[package.scala:267:30]\n input clock,\t// @[package.scala:267:30]\n input reset,\t// @[package.scala:267:30]\n input [19:0] io_x_ppn,\t// @[package.scala:268:18]\n input io_x_u,\t// @[package.scala:268:18]\n input io_x_g,\t// @[package.scala:268:18]\n input io_x_ae_ptw,\t// @[package.scala:268:18]\n input io_x_ae_final,\t// @[package.scala:268:18]\n input io_x_ae_stage2,\t// @[package.scala:268:18]\n input io_x_pf,\t// @[package.scala:268:18]\n input io_x_gf,\t// @[package.scala:268:18]\n input io_x_sw,\t// @[package.scala:268:18]\n input io_x_sx,\t// @[package.scala:268:18]\n input io_x_sr,\t// @[package.scala:268:18]\n input io_x_hw,\t// @[package.scala:268:18]\n input io_x_hx,\t// @[package.scala:268:18]\n input io_x_hr,\t// @[package.scala:268:18]\n input io_x_pw,\t// @[package.scala:268:18]\n input io_x_px,\t// @[package.scala:268:18]\n input io_x_pr,\t// @[package.scala:268:18]\n input io_x_ppp,\t// @[package.scala:268:18]\n input io_x_pal,\t// @[package.scala:268:18]\n input io_x_paa,\t// @[package.scala:268:18]\n input io_x_eff,\t// @[package.scala:268:18]\n input io_x_c,\t// @[package.scala:268:18]\n input io_x_fragmented_superpage,\t// @[package.scala:268:18]\n output [19:0] io_y_ppn,\t// @[package.scala:268:18]\n output io_y_u,\t// @[package.scala:268:18]\n output io_y_ae_ptw,\t// @[package.scala:268:18]\n output io_y_ae_final,\t// @[package.scala:268:18]\n output io_y_ae_stage2,\t// @[package.scala:268:18]\n output io_y_pf,\t// @[package.scala:268:18]\n output io_y_gf,\t// @[package.scala:268:18]\n output io_y_sw,\t// @[package.scala:268:18]\n output io_y_sx,\t// @[package.scala:268:18]\n output io_y_sr,\t// @[package.scala:268:18]\n output io_y_hw,\t// @[package.scala:268:18]\n output io_y_hx,\t// @[package.scala:268:18]\n output io_y_hr,\t// @[package.scala:268:18]\n output io_y_pw,\t// @[package.scala:268:18]\n output io_y_px,\t// @[package.scala:268:18]\n output io_y_pr,\t// @[package.scala:268:18]\n output io_y_ppp,\t// @[package.scala:268:18]\n output io_y_pal,\t// @[package.scala:268:18]\n output io_y_paa,\t// @[package.scala:268:18]\n output io_y_eff,\t// @[package.scala:268:18]\n output io_y_c\t// @[package.scala:268:18]\n);\n\n wire [19:0] io_x_ppn_0 = io_x_ppn;\t// @[package.scala:267:30]\n wire io_x_u_0 = io_x_u;\t// @[package.scala:267:30]\n wire io_x_g_0 = io_x_g;\t// @[package.scala:267:30]\n wire io_x_ae_ptw_0 = io_x_ae_ptw;\t// @[package.scala:267:30]\n wire io_x_ae_final_0 = io_x_ae_final;\t// @[package.scala:267:30]\n wire io_x_ae_stage2_0 = io_x_ae_stage2;\t// @[package.scala:267:30]\n wire io_x_pf_0 = io_x_pf;\t// @[package.scala:267:30]\n wire io_x_gf_0 = io_x_gf;\t// @[package.scala:267:30]\n wire io_x_sw_0 = io_x_sw;\t// @[package.scala:267:30]\n wire io_x_sx_0 = io_x_sx;\t// @[package.scala:267:30]\n wire io_x_sr_0 = io_x_sr;\t// @[package.scala:267:30]\n wire io_x_hw_0 = io_x_hw;\t// @[package.scala:267:30]\n wire io_x_hx_0 = io_x_hx;\t// @[package.scala:267:30]\n wire io_x_hr_0 = io_x_hr;\t// @[package.scala:267:30]\n wire io_x_pw_0 = io_x_pw;\t// @[package.scala:267:30]\n wire io_x_px_0 = io_x_px;\t// @[package.scala:267:30]\n wire io_x_pr_0 = io_x_pr;\t// @[package.scala:267:30]\n wire io_x_ppp_0 = io_x_ppp;\t// @[package.scala:267:30]\n wire io_x_pal_0 = io_x_pal;\t// @[package.scala:267:30]\n wire io_x_paa_0 = io_x_paa;\t// @[package.scala:267:30]\n wire io_x_eff_0 = io_x_eff;\t// @[package.scala:267:30]\n wire io_x_c_0 = io_x_c;\t// @[package.scala:267:30]\n wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage;\t// @[package.scala:267:30]\n wire [19:0] io_y_ppn_0 = io_x_ppn_0;\t// @[package.scala:267:30]\n wire io_y_u_0 = io_x_u_0;\t// @[package.scala:267:30]\n wire io_y_g = io_x_g_0;\t// @[package.scala:267:30]\n wire io_y_ae_ptw_0 = io_x_ae_ptw_0;\t// @[package.scala:267:30]\n wire io_y_ae_final_0 = io_x_ae_final_0;\t// @[package.scala:267:30]\n wire io_y_ae_stage2_0 = io_x_ae_stage2_0;\t// @[package.scala:267:30]\n wire io_y_pf_0 = io_x_pf_0;\t// @[package.scala:267:30]\n wire io_y_gf_0 = io_x_gf_0;\t// @[package.scala:267:30]\n wire io_y_sw_0 = io_x_sw_0;\t// @[package.scala:267:30]\n wire io_y_sx_0 = io_x_sx_0;\t// @[package.scala:267:30]\n wire io_y_sr_0 = io_x_sr_0;\t// @[package.scala:267:30]\n wire io_y_hw_0 = io_x_hw_0;\t// @[package.scala:267:30]\n wire io_y_hx_0 = io_x_hx_0;\t// @[package.scala:267:30]\n wire io_y_hr_0 = io_x_hr_0;\t// @[package.scala:267:30]\n wire io_y_pw_0 = io_x_pw_0;\t// @[package.scala:267:30]\n wire io_y_px_0 = io_x_px_0;\t// @[package.scala:267:30]\n wire io_y_pr_0 = io_x_pr_0;\t// @[package.scala:267:30]\n wire io_y_ppp_0 = io_x_ppp_0;\t// @[package.scala:267:30]\n wire io_y_pal_0 = io_x_pal_0;\t// @[package.scala:267:30]\n wire io_y_paa_0 = io_x_paa_0;\t// @[package.scala:267:30]\n wire io_y_eff_0 = io_x_eff_0;\t// @[package.scala:267:30]\n wire io_y_c_0 = io_x_c_0;\t// @[package.scala:267:30]\n wire io_y_fragmented_superpage = io_x_fragmented_superpage_0;\t// @[package.scala:267:30]\n assign io_y_ppn = io_y_ppn_0;\t// @[package.scala:267:30]\n assign io_y_u = io_y_u_0;\t// @[package.scala:267:30]\n assign io_y_ae_ptw = io_y_ae_ptw_0;\t// @[package.scala:267:30]\n assign io_y_ae_final = io_y_ae_final_0;\t// @[package.scala:267:30]\n assign io_y_ae_stage2 = io_y_ae_stage2_0;\t// @[package.scala:267:30]\n assign io_y_pf = io_y_pf_0;\t// @[package.scala:267:30]\n assign io_y_gf = io_y_gf_0;\t// @[package.scala:267:30]\n assign io_y_sw = io_y_sw_0;\t// @[package.scala:267:30]\n assign io_y_sx = io_y_sx_0;\t// @[package.scala:267:30]\n assign io_y_sr = io_y_sr_0;\t// @[package.scala:267:30]\n assign io_y_hw = io_y_hw_0;\t// @[package.scala:267:30]\n assign io_y_hx = io_y_hx_0;\t// @[package.scala:267:30]\n assign io_y_hr = io_y_hr_0;\t// @[package.scala:267:30]\n assign io_y_pw = io_y_pw_0;\t// @[package.scala:267:30]\n assign io_y_px = io_y_px_0;\t// @[package.scala:267:30]\n assign io_y_pr = io_y_pr_0;\t// @[package.scala:267:30]\n assign io_y_ppp = io_y_ppp_0;\t// @[package.scala:267:30]\n assign io_y_pal = io_y_pal_0;\t// @[package.scala:267:30]\n assign io_y_paa = io_y_paa_0;\t// @[package.scala:267:30]\n assign io_y_eff = io_y_eff_0;\t// @[package.scala:267:30]\n assign io_y_c = io_y_c_0;\t// @[package.scala:267:30]\nendmodule"}}},{"rowIdx":5098,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile FIFOFixer.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.lazymodule._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.diplomacy.RegionType\nimport freechips.rocketchip.util.property\n\nclass TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule\n{\n private def fifoMap(seq: Seq[TLSlaveParameters]) = {\n val (flatManagers, keepManagers) = seq.partition(policy)\n // We need to be careful if one flatManager and one keepManager share an existing domain\n // Erring on the side of caution, we will also flatten the keepManager in this case\n val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0\n val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted\n // Calculate what the FIFO domains look like after the fixer is applied\n val flatMap = flatDomains.map { x => (x, 0) }.toMap\n val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap\n val map = flatMap ++ keepMap\n val fixMap = seq.map { m => m.fifoId match {\n case None => if (policy(m)) Some(0) else None\n case Some(id) => Some(map(id)) // also flattens some who did not ask\n } }\n // Compress the FIFO domain space of those we are combining\n val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap\n val splatMap = seq.map { m => m.fifoId match {\n case None => None\n case Some(id) => reMap.lift(id)\n } }\n (fixMap, splatMap)\n }\n\n val node = new AdapterNode(TLImp)(\n { cp => cp },\n { mp =>\n val (fixMap, _) = fifoMap(mp.managers)\n mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })\n }) with TLFormatNode {\n override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0\n }\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>\n val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)\n\n // Do we need to serialize the request to this manager?\n val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)\n // Compact the IDs of the cases we serialize\n val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {\n case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None\n }\n val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0\n val a_id = if (compacted.isEmpty) 0.U else\n edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)\n val a_noDomain = a_id === 0.U\n\n if (false) {\n println(s\"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(\", \")}\")\n println(s\"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(\", \")}\")\n println(s\"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(\", \")}\")\n println(s\"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}\")\n println(\"\")\n }\n\n // Count beats\n val a_first = edgeIn.first(in.a)\n val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck\n\n // Keep one bit for each source recording if there is an outstanding request that must be made FIFO\n // Sources unused in the stall signal calculation should be pruned by DCE\n val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))\n when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }\n when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }\n\n val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>\n val a_sel = c.sourceId.contains(in.a.bits.source)\n val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)\n val track = flight.slice(c.sourceId.start, c.sourceId.end)\n\n a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)\n }\n\n val stall = stalls.foldLeft(false.B)(_||_)\n\n out.a <> in.a\n in.d <> out.d\n out.a.valid := in.a.valid && (a_notFIFO || !stall)\n in.a.ready := out.a.ready && (a_notFIFO || !stall)\n\n if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {\n in .b <> out.b\n out.c <> in .c\n out.e <> in .e\n } else {\n in.b.valid := false.B\n in.c.ready := true.B\n in.e.ready := true.B\n out.b.ready := true.B\n out.c.valid := false.B\n out.e.valid := false.B\n }\n\n//Functional cover properties\n \n property.cover(in.a.valid && stall, \"COVER FIFOFIXER STALL\", \"Cover: Stall occured for a valid transaction\")\n\n val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))\n val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))\n val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))\n\n when (a_first && in.a.fire && !a_notFIFO) {\n SourceIdSet := UIntToOH(in.a.bits.source)\n }\n when (d_first && in.d.fire) {\n SourceIdClear := UIntToOH(in.d.bits.source)\n }\n\n SourceIdFIFOed := SourceIdFIFOed | SourceIdSet\n val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)\n\n property.cover(allIDs_FIFOed, \"COVER all sources\", \"Cover: FIFOFIXER covers all Source IDs\")\n //property.cover(flight.reduce(_ && _), \"COVER full\", \"Cover: FIFO is full with all Source IDs\")\n property.cover(!(flight.reduce(_ || _)), \"COVER empty\", \"Cover: FIFO is empty\")\n property.cover(SourceIdSet > 0.U, \"COVER at least one push\", \"Cover: At least one Source ID is pushed\")\n property.cover(SourceIdClear > 0.U, \"COVER at least one pop\", \"Cover: At least one Source ID is popped\")\n\n }\n }\n}\n\nobject TLFIFOFixer\n{\n // Which slaves should have their FIFOness combined?\n // NOTE: this transformation is still only applied for masters with requestFifo\n type Policy = TLSlaveParameters => Boolean\n import RegionType._\n\n val all: Policy = m => true\n val allFIFO: Policy = m => m.fifoId.isDefined\n val allVolatile: Policy = m => m.regionType <= VOLATILE\n\n def apply(policy: Policy = all)(implicit p: Parameters): TLNode =\n {\n val fixer = LazyModule(new TLFIFOFixer(policy))\n fixer.node\n }\n}\nFile Nodes.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}\n\ncase object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))\n\nobject TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]\n{\n def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)\n def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)\n\n def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)\n def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)\n\n def render(ei: TLEdgeIn) = RenderedEdge(colour = \"#000000\" /* black */, label = (ei.manager.beatBytes * 8).toString)\n\n override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {\n val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))\n monitor.io.in := bundle\n }\n\n override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =\n pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })\n override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =\n pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })\n}\n\n\ntrait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]\n\ncase class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode\ncase class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode\n\ncase class TLAdapterNode(\n clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },\n managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLJunctionNode(\n clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],\n managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(\n implicit valName: ValName)\n extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\ncase class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode\n\nobject TLNameNode {\n def apply(name: ValName) = TLIdentityNode()(name)\n def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLIdentityNode = apply(Some(name))\n}\n\ncase class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()\n\nobject TLTempNode {\n def apply(): TLEphemeralNode = TLEphemeralNode()(ValName(\"temp\"))\n}\n\ncase class TLNexusNode(\n clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,\n managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(\n implicit valName: ValName)\n extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode\n\nabstract class TLCustomNode(implicit valName: ValName)\n extends CustomNode(TLImp) with TLFormatNode\n\n// Asynchronous crossings\n\ntrait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]\n\nobject TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]\n{\n def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)\n def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = \"#ff0000\" /* red */, label = e.manager.async.depth.toString)\n\n override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLAsyncAdapterNode(\n clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },\n managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode\n\ncase class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode\n\nobject TLAsyncNameNode {\n def apply(name: ValName) = TLAsyncIdentityNode()(name)\n def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLAsyncIdentityNode = apply(Some(name))\n}\n\ncase class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLAsyncImp)(\n dFn = { p => TLAsyncClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain\ncase class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)\n extends MixedAdapterNode(TLAsyncImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },\n uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]\n\n// Rationally related crossings\n\ntrait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]\n\nobject TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]\n{\n def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)\n def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = \"#00ff00\" /* green */)\n\n override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLRationalAdapterNode(\n clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },\n managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode\n\ncase class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode\n\nobject TLRationalNameNode {\n def apply(name: ValName) = TLRationalIdentityNode()(name)\n def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLRationalIdentityNode = apply(Some(name))\n}\n\ncase class TLRationalSourceNode()(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLRationalImp)(\n dFn = { p => TLRationalClientPortParameters(p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain\ncase class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)\n extends MixedAdapterNode(TLRationalImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]\n\n// Credited version of TileLink channels\n\ntrait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]\n\nobject TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]\n{\n def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)\n def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)\n def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = \"#ffff00\" /* yellow */, e.delay.toString)\n\n override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =\n pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))\n override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =\n pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))\n}\n\ncase class TLCreditedAdapterNode(\n clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },\n managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(\n implicit valName: ValName)\n extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode\n\ncase class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode\n\nobject TLCreditedNameNode {\n def apply(name: ValName) = TLCreditedIdentityNode()(name)\n def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse(\"with_no_name\")))\n def apply(name: String): TLCreditedIdentityNode = apply(Some(name))\n}\n\ncase class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLImp, TLCreditedImp)(\n dFn = { p => TLCreditedClientPortParameters(delay, p) },\n uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain\n\ncase class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)\n extends MixedAdapterNode(TLCreditedImp, TLImp)(\n dFn = { p => p.base.v1copy(minLatency = 1) },\n uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]\nFile LazyModuleImp.scala:\npackage org.chipsalliance.diplomacy.lazymodule\n\nimport chisel3.{withClockAndReset, Module, RawModule, Reset, _}\nimport chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}\nimport firrtl.passes.InlineAnnotation\nimport org.chipsalliance.cde.config.Parameters\nimport org.chipsalliance.diplomacy.nodes.Dangle\n\nimport scala.collection.immutable.SortedMap\n\n/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].\n *\n * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.\n */\nsealed trait LazyModuleImpLike extends RawModule {\n\n /** [[LazyModule]] that contains this instance. */\n val wrapper: LazyModule\n\n /** IOs that will be automatically \"punched\" for this instance. */\n val auto: AutoBundle\n\n /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */\n protected[diplomacy] val dangles: Seq[Dangle]\n\n // [[wrapper.module]] had better not be accessed while LazyModules are still being built!\n require(\n LazyModule.scope.isEmpty,\n s\"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}\"\n )\n\n /** Set module name. Defaults to the containing LazyModule's desiredName. */\n override def desiredName: String = wrapper.desiredName\n\n suggestName(wrapper.suggestedName)\n\n /** [[Parameters]] for chisel [[Module]]s. */\n implicit val p: Parameters = wrapper.p\n\n /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and\n * submodules.\n */\n protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {\n // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],\n // 2. return [[Dangle]]s from each module.\n val childDangles = wrapper.children.reverse.flatMap { c =>\n implicit val sourceInfo: SourceInfo = c.info\n c.cloneProto.map { cp =>\n // If the child is a clone, then recursively set cloneProto of its children as well\n def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {\n require(bases.size == clones.size)\n (bases.zip(clones)).map { case (l, r) =>\n require(l.getClass == r.getClass, s\"Cloned children class mismatch ${l.name} != ${r.name}\")\n l.cloneProto = Some(r)\n assignCloneProtos(l.children, r.children)\n }\n }\n assignCloneProtos(c.children, cp.children)\n // Clone the child module as a record, and get its [[AutoBundle]]\n val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)\n val clonedAuto = clone(\"auto\").asInstanceOf[AutoBundle]\n // Get the empty [[Dangle]]'s of the cloned child\n val rawDangles = c.cloneDangles()\n require(rawDangles.size == clonedAuto.elements.size)\n // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s\n val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }\n dangles\n }.getOrElse {\n // For non-clones, instantiate the child module\n val mod = try {\n Module(c.module)\n } catch {\n case e: ChiselException => {\n println(s\"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}\")\n throw e\n }\n }\n mod.dangles\n }\n }\n\n // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].\n // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.\n val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())\n // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]\n val allDangles = nodeDangles ++ childDangles\n // Group [[allDangles]] by their [[source]].\n val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)\n // For each [[source]] set of [[Dangle]]s of size 2, ensure that these\n // can be connected as a source-sink pair (have opposite flipped value).\n // Make the connection and mark them as [[done]].\n val done = Set() ++ pairing.values.filter(_.size == 2).map {\n case Seq(a, b) =>\n require(a.flipped != b.flipped)\n // @todo <> in chisel3 makes directionless connection.\n if (a.flipped) {\n a.data <> b.data\n } else {\n b.data <> a.data\n }\n a.source\n case _ => None\n }\n // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.\n val forward = allDangles.filter(d => !done(d.source))\n // Generate [[AutoBundle]] IO from [[forward]].\n val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))\n // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]\n val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>\n if (d.flipped) {\n d.data <> io\n } else {\n io <> d.data\n }\n d.copy(dataOpt = Some(io), name = wrapper.suggestedName + \"_\" + d.name)\n }\n // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].\n wrapper.inModuleBody.reverse.foreach {\n _()\n }\n\n if (wrapper.shouldBeInlined) {\n chisel3.experimental.annotate(new ChiselAnnotation {\n def toFirrtl = InlineAnnotation(toNamed)\n })\n }\n\n // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].\n (auto, dangles)\n }\n}\n\n/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {\n\n /** Instantiate hardware of this `Module`. */\n val (auto, dangles) = instantiate()\n}\n\n/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].\n *\n * @param wrapper\n * the [[LazyModule]] from which the `.module` call is being made.\n */\nclass LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {\n // These wires are the default clock+reset for all LazyModule children.\n // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the\n // [[LazyRawModuleImp]] children.\n // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.\n /** drive clock explicitly. */\n val childClock: Clock = Wire(Clock())\n\n /** drive reset explicitly. */\n val childReset: Reset = Wire(Reset())\n // the default is that these are disabled\n childClock := false.B.asClock\n childReset := chisel3.DontCare\n\n def provideImplicitClockToLazyChildren: Boolean = false\n val (auto, dangles) =\n if (provideImplicitClockToLazyChildren) {\n withClockAndReset(childClock, childReset) { instantiate() }\n } else {\n instantiate()\n }\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile MixedNode.scala:\npackage org.chipsalliance.diplomacy.nodes\n\nimport chisel3.{Data, DontCare, Wire}\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.{Field, Parameters}\n\nimport org.chipsalliance.diplomacy.ValName\nimport org.chipsalliance.diplomacy.sourceLine\n\n/** One side metadata of a [[Dangle]].\n *\n * Describes one side of an edge going into or out of a [[BaseNode]].\n *\n * @param serial\n * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.\n * @param index\n * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.\n */\ncase class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {\n\n import scala.math.Ordered.orderingToOrdered\n\n def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))\n}\n\n/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]\n * connects.\n *\n * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,\n * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].\n *\n * @param source\n * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within\n * that [[BaseNode]].\n * @param sink\n * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that\n * [[BaseNode]].\n * @param flipped\n * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to\n * `danglesIn`.\n * @param dataOpt\n * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module\n */\ncase class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {\n def data = dataOpt.get\n}\n\n/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often\n * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually\n * implement the protocol.\n */\ncase class Edges[EI, EO](in: Seq[EI], out: Seq[EO])\n\n/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */\ncase object MonitorsEnabled extends Field[Boolean](true)\n\n/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.\n *\n * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but\n * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink\n * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the\n * [[LazyModule]].\n */\ncase object RenderFlipped extends Field[Boolean](false)\n\n/** The sealed node class in the package, all node are derived from it.\n *\n * @param inner\n * Sink interface implementation.\n * @param outer\n * Source interface implementation.\n * @param valName\n * val name of this node.\n * @tparam DI\n * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters\n * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected\n * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port\n * parameters.\n * @tparam UI\n * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing\n * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.\n * @tparam EI\n * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers\n * specified for a sink according to protocol.\n * @tparam BI\n * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.\n * It should extends from [[chisel3.Data]], which represents the real hardware.\n * @tparam DO\n * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters\n * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.\n * @tparam UO\n * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing\n * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].\n * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.\n * @tparam EO\n * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers\n * specified for a source according to protocol.\n * @tparam BO\n * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source\n * interface. It should extends from [[chisel3.Data]], which represents the real hardware.\n *\n * @note\n * Call Graph of [[MixedNode]]\n * - line `─`: source is process by a function and generate pass to others\n * - Arrow `→`: target of arrow is generated by source\n *\n * {{{\n * (from the other node)\n * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐\n * ↓ │\n * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │\n * [[InwardNode.accPI]] │ │ │\n * │ │ (based on protocol) │\n * │ │ [[MixedNode.inner.edgeI]] │\n * │ │ ↓ │\n * ↓ │ │ │\n * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │\n * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │\n * │ │ ↑ │ │ │\n * │ │ │ [[OutwardNode.doParams]] │ │\n * │ │ │ (from the other node) │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * │ │ │ └────────┬──────────────┤ │\n * │ │ │ │ │ │\n * │ │ │ │ (based on protocol) │\n * │ │ │ │ [[MixedNode.inner.edgeI]] │\n * │ │ │ │ │ │\n * │ │ (from the other node) │ ↓ │\n * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │\n * │ ↑ ↑ │ │ ↓ │\n * │ │ │ │ │ [[MixedNode.in]] │\n * │ │ │ │ ↓ ↑ │\n * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │\n * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │\n * │ │ │ [[MixedNode.bundleOut]]─┐ │ │\n * │ │ │ ↑ ↓ │ │\n * │ │ │ │ [[MixedNode.out]] │ │\n * │ ↓ ↓ │ ↑ │ │\n * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │\n * │ │ (from the other node) ↑ │ │\n * │ │ │ │ │ │\n * │ │ │ [[MixedNode.outer.edgeO]] │ │\n * │ │ │ (based on protocol) │ │\n * │ │ │ │ │ │\n * │ │ │ ┌────────────────────────────────────────┤ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * │ │ │ │ │ │ │\n * (immobilize after elaboration)│ ↓ │ │ │ │\n * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │\n * ↑ (inward port from [[OutwardNode]]) │ │ │ │\n * │ ┌─────────────────────────────────────────┤ │ │ │\n * │ │ │ │ │ │\n * │ │ │ │ │ │\n * [[OutwardNode.accPO]] │ ↓ │ │ │\n * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │\n * │ ↑ │ │\n * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │\n * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘\n * }}}\n */\nabstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](\n val inner: InwardNodeImp[DI, UI, EI, BI],\n val outer: OutwardNodeImp[DO, UO, EO, BO]\n)(\n implicit valName: ValName)\n extends BaseNode\n with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]\n with InwardNode[DI, UI, BI]\n with OutwardNode[DO, UO, BO] {\n // Generate a [[NodeHandle]] with inward and outward node are both this node.\n val inward = this\n val outward = this\n\n /** Debug info of nodes binding. */\n def bindingInfo: String = s\"\"\"$iBindingInfo\n |$oBindingInfo\n |\"\"\".stripMargin\n\n /** Debug info of ports connecting. */\n def connectedPortsInfo: String = s\"\"\"${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(\",\")}]\n |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** Debug info of parameters propagations. */\n def parametersInfo: String = s\"\"\"${doParams.size} downstream outward parameters: [${doParams.mkString(\",\")}]\n |${uoParams.size} upstream outward parameters: [${uoParams.mkString(\",\")}]\n |${diParams.size} downstream inward parameters: [${diParams.mkString(\",\")}]\n |${uiParams.size} upstream inward parameters: [${uiParams.mkString(\",\")}]\n |\"\"\".stripMargin\n\n /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and\n * [[MixedNode.iPortMapping]].\n *\n * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward\n * stars and outward stars.\n *\n * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type\n * of node.\n *\n * @param iKnown\n * Number of known-size ([[BIND_ONCE]]) input bindings.\n * @param oKnown\n * Number of known-size ([[BIND_ONCE]]) output bindings.\n * @param iStar\n * Number of unknown size ([[BIND_STAR]]) input bindings.\n * @param oStar\n * Number of unknown size ([[BIND_STAR]]) output bindings.\n * @return\n * A Tuple of the resolved number of input and output connections.\n */\n protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)\n\n /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output\n * ports.\n *\n * @param n\n * The size of the output sequence to generate.\n * @param p\n * Sequence of downward-flowing input parameters of this node.\n * @return\n * A `n`-sized sequence of downward-flowing output edge parameters.\n */\n protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]\n\n /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].\n *\n * @param n\n * Size of the output sequence.\n * @param p\n * Upward-flowing output edge parameters.\n * @return\n * A n-sized sequence of upward-flowing input edge parameters.\n */\n protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]\n\n /** @return\n * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with\n * [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)\n\n /** @return\n * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of\n * output bindings bound with [[BIND_STAR]].\n */\n protected[diplomacy] lazy val sourceCard: Int =\n iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)\n\n /** @return list of nodes involved in flex bindings with this node. */\n protected[diplomacy] lazy val flexes: Seq[BaseNode] =\n oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)\n\n /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin\n * greedily taking up the remaining connections.\n *\n * @return\n * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return\n * value is not relevant.\n */\n protected[diplomacy] lazy val flexOffset: Int = {\n\n /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex\n * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a\n * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of\n * each node in the current set and decide whether they should be added to the set or not.\n *\n * @return\n * the mapping of [[BaseNode]] indexed by their serial numbers.\n */\n def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {\n if (visited.contains(v.serial) || !v.flexibleArityDirection) {\n visited\n } else {\n v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))\n }\n }\n\n /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.\n *\n * @example\n * {{{\n * a :*=* b :*=* c\n * d :*=* b\n * e :*=* f\n * }}}\n *\n * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`\n */\n val flexSet = DFS(this, Map()).values\n\n /** The total number of :*= operators where we're on the left. */\n val allSink = flexSet.map(_.sinkCard).sum\n\n /** The total number of :=* operators used when we're on the right. */\n val allSource = flexSet.map(_.sourceCard).sum\n\n require(\n allSink == 0 || allSource == 0,\n s\"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction.\"\n )\n allSink - allSource\n }\n\n /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */\n protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {\n if (flexibleArityDirection) flexOffset\n else if (n.flexibleArityDirection) n.flexOffset\n else 0\n }\n\n /** For a node which is connected between two nodes, select the one that will influence the direction of the flex\n * resolution.\n */\n protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {\n val dir = edgeArityDirection(n)\n if (dir < 0) l\n else if (dir > 0) r\n else 1\n }\n\n /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */\n private var starCycleGuard = false\n\n /** Resolve all the star operators into concrete indicies. As connections are being made, some may be \"star\"\n * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also\n * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct\n * edge parameters and later build up correct bundle connections.\n *\n * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding\n * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort\n * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=\n * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`\n */\n protected[diplomacy] lazy val (\n oPortMapping: Seq[(Int, Int)],\n iPortMapping: Seq[(Int, Int)],\n oStar: Int,\n iStar: Int\n ) = {\n try {\n if (starCycleGuard) throw StarCycleException()\n starCycleGuard = true\n // For a given node N...\n // Number of foo :=* N\n // + Number of bar :=* foo :*=* N\n val oStars = oBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)\n }\n // Number of N :*= foo\n // + Number of N :*=* foo :*= bar\n val iStars = iBindings.count { case (_, n, b, _, _) =>\n b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)\n }\n // 1 for foo := N\n // + bar.iStar for bar :*= foo :*=* N\n // + foo.iStar for foo :*= N\n // + 0 for foo :=* N\n val oKnown = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => 0\n }\n }.sum\n // 1 for N := foo\n // + bar.oStar for N :*=* foo :=* bar\n // + foo.oStar for N :=* foo\n // + 0 for N :*= foo\n val iKnown = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)\n case BIND_QUERY => n.oStar\n case BIND_STAR => 0\n }\n }.sum\n // Resolve star depends on the node subclass to implement the algorithm for this.\n val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)\n // Cumulative list of resolved outward binding range starting points\n val oSum = oBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)\n case BIND_QUERY => n.iStar\n case BIND_STAR => oStar\n }\n }.scanLeft(0)(_ + _)\n // Cumulative list of resolved inward binding range starting points\n val iSum = iBindings.map { case (_, n, b, _, _) =>\n b match {\n case BIND_ONCE => 1\n case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)\n case BIND_QUERY => n.oStar\n case BIND_STAR => iStar\n }\n }.scanLeft(0)(_ + _)\n // Create ranges for each binding based on the running sums and return\n // those along with resolved values for the star operations.\n (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)\n } catch {\n case c: StarCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Sequence of inward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.\n * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this\n * connection was made in the source code.\n */\n protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =\n oBindings.flatMap { case (i, n, _, p, s) =>\n // for each binding operator in this node, look at what it connects to\n val (start, end) = n.iPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n /** Sequence of outward ports.\n *\n * This should be called after all star bindings are resolved.\n *\n * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of\n * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection\n * was made in the source code.\n */\n protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =\n iBindings.flatMap { case (i, n, _, p, s) =>\n // query this port index range of this node in the other side of node.\n val (start, end) = n.oPortMapping(i)\n (start until end).map { j => (j, n, p, s) }\n }\n\n // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree\n // Thus, there must exist an Eulerian path and the below algorithms terminate\n @scala.annotation.tailrec\n private def oTrace(\n tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)\n ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.iForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => oTrace((j, m, p, s))\n }\n }\n\n @scala.annotation.tailrec\n private def iTrace(\n tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)\n ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {\n case (i, n, p, s) => n.oForward(i) match {\n case None => (i, n, p, s)\n case Some((j, m)) => iTrace((j, m, p, s))\n }\n }\n\n /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - Numeric index of this binding in the [[InwardNode]] on the other end.\n * - [[InwardNode]] on the other end of this binding.\n * - A view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)\n\n /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.\n *\n * Each Port is a tuple of:\n * - numeric index of this binding in [[OutwardNode]] on the other end.\n * - [[OutwardNode]] on the other end of this binding.\n * - a view of [[Parameters]] where the binding occurred.\n * - [[SourceInfo]] for source-level error reporting.\n */\n lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)\n\n private var oParamsCycleGuard = false\n protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }\n protected[diplomacy] lazy val doParams: Seq[DO] = {\n try {\n if (oParamsCycleGuard) throw DownwardCycleException()\n oParamsCycleGuard = true\n val o = mapParamsD(oPorts.size, diParams)\n require(\n o.size == oPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of outward ports should equal the number of produced outward parameters.\n |$context\n |$connectedPortsInfo\n |Downstreamed inward parameters: [${diParams.mkString(\",\")}]\n |Produced outward parameters: [${o.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n o.map(outer.mixO(_, this))\n } catch {\n case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n private var iParamsCycleGuard = false\n protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }\n protected[diplomacy] lazy val uiParams: Seq[UI] = {\n try {\n if (iParamsCycleGuard) throw UpwardCycleException()\n iParamsCycleGuard = true\n val i = mapParamsU(iPorts.size, uoParams)\n require(\n i.size == iPorts.size,\n s\"\"\"Diplomacy has detected a problem with your graph:\n |At the following node, the number of inward ports should equal the number of produced inward parameters.\n |$context\n |$connectedPortsInfo\n |Upstreamed outward parameters: [${uoParams.mkString(\",\")}]\n |Produced inward parameters: [${i.mkString(\",\")}]\n |\"\"\".stripMargin\n )\n i.map(inner.mixI(_, this))\n } catch {\n case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)\n }\n }\n\n /** Outward edge parameters. */\n protected[diplomacy] lazy val edgesOut: Seq[EO] =\n (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }\n\n /** Inward edge parameters. */\n protected[diplomacy] lazy val edgesIn: Seq[EI] =\n (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }\n\n /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.\n *\n * If you need to access to the edges of a foreign Node, use this method (in/out create bundles).\n */\n lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)\n\n /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */\n protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>\n val x = Wire(outer.bundleO(e)).suggestName(s\"${valName.value}Out\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */\n protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>\n val x = Wire(inner.bundleI(e)).suggestName(s\"${valName.value}In\")\n // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,\n // In the future, we should add an option to decide whether allowing unconnected in the LazyModule\n x := DontCare\n x\n }\n\n private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(serial, i),\n sink = HalfEdge(n.serial, j),\n flipped = false,\n name = wirePrefix + \"out\",\n dataOpt = None\n )\n }\n private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>\n Dangle(\n source = HalfEdge(n.serial, j),\n sink = HalfEdge(serial, i),\n flipped = true,\n name = wirePrefix + \"in\",\n dataOpt = None\n )\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */\n protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleOut(i)))\n }\n\n /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */\n protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>\n d.copy(dataOpt = Some(bundleIn(i)))\n }\n\n private[diplomacy] var instantiated = false\n\n /** Gather Bundle and edge parameters of outward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def out: Seq[(BO, EO)] = {\n require(\n instantiated,\n s\"$name.out should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleOut.zip(edgesOut)\n }\n\n /** Gather Bundle and edge parameters of inward ports.\n *\n * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within\n * [[LazyModuleImp]] code or after its instantiation has completed.\n */\n def in: Seq[(BI, EI)] = {\n require(\n instantiated,\n s\"$name.in should not be called until after instantiation of its parent LazyModule.module has begun\"\n )\n bundleIn.zip(edgesIn)\n }\n\n /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,\n * instantiate monitors on all input ports if appropriate, and return all the dangles of this node.\n */\n protected[diplomacy] def instantiate(): Seq[Dangle] = {\n instantiated = true\n if (!circuitIdentity) {\n (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }\n }\n danglesOut ++ danglesIn\n }\n\n protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn\n\n /** Connects the outward part of a node with the inward part of this node. */\n protected[diplomacy] def bind(\n h: OutwardNode[DI, UI, BI],\n binding: NodeBinding\n )(\n implicit p: Parameters,\n sourceInfo: SourceInfo\n ): Unit = {\n val x = this // x := y\n val y = h\n sourceLine(sourceInfo, \" at \", \"\")\n val i = x.iPushed\n val o = y.oPushed\n y.oPush(\n i,\n x,\n binding match {\n case BIND_ONCE => BIND_ONCE\n case BIND_FLEX => BIND_FLEX\n case BIND_STAR => BIND_QUERY\n case BIND_QUERY => BIND_STAR\n }\n )\n x.iPush(o, y, binding)\n }\n\n /* Metadata for printing the node graph. */\n def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>\n val re = inner.render(e)\n (n, re.copy(flipped = re.flipped != p(RenderFlipped)))\n }\n\n /** Metadata for printing the node graph */\n def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLFIFOFixer_2(\t// @[FIFOFixer.scala:50:9]\n input clock,\t// @[FIFOFixer.scala:50:9]\n input reset,\t// @[FIFOFixer.scala:50:9]\n output auto_anon_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_bufferable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_modifiable,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_readalloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_writealloc,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_privileged,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_secure,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_user_amba_prot_fetch,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_privileged_0 = auto_anon_in_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_secure_0 = auto_anon_in_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_user_amba_prot_fetch_0 = auto_anon_in_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire [32:0] _a_notFIFO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_notFIFO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_id_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_id_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [15:0] _allIDs_FIFOed_T = 16'hFFFF;\t// @[FIFOFixer.scala:127:48]\n wire [2:0] auto_anon_in_a_bits_param = 3'h0;\t// @[Nodes.scala:27:25]\n wire [2:0] auto_anon_out_a_bits_param = 3'h0;\t// @[Nodes.scala:27:25]\n wire [2:0] anonIn_a_bits_param = 3'h0;\t// @[Nodes.scala:27:25]\n wire [2:0] anonOut_a_bits_param = 3'h0;\t// @[Nodes.scala:27:25]\n wire auto_anon_in_a_bits_corrupt = 1'h0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_corrupt = 1'h0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_bits_corrupt = 1'h0;\t// @[MixedNode.scala:542:17]\n wire a_noDomain = 1'h0;\t// @[FIFOFixer.scala:63:29]\n wire _flight_WIRE_0 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_1 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_2 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_3 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_4 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_5 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_6 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_7 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_8 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_9 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_10 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_11 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_12 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_13 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_14 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_15 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _stalls_T_9 = 1'h0;\t// @[FIFOFixer.scala:88:71]\n wire _stalls_T_10 = 1'h0;\t// @[FIFOFixer.scala:88:65]\n wire stalls_0 = 1'h0;\t// @[FIFOFixer.scala:88:50]\n wire _stalls_T_20 = 1'h0;\t// @[FIFOFixer.scala:88:71]\n wire _stalls_T_21 = 1'h0;\t// @[FIFOFixer.scala:88:65]\n wire stalls_1 = 1'h0;\t// @[FIFOFixer.scala:88:50]\n wire _stall_T = 1'h0;\t// @[FIFOFixer.scala:91:45]\n wire stall = 1'h0;\t// @[FIFOFixer.scala:91:45]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire _a_notFIFO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _a_id_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _flight_T = 1'h1;\t// @[FIFOFixer.scala:80:65]\n wire _stalls_a_sel_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_2 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire _stalls_a_sel_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_6 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire _anonOut_a_valid_T = 1'h1;\t// @[FIFOFixer.scala:95:50]\n wire _anonOut_a_valid_T_1 = 1'h1;\t// @[FIFOFixer.scala:95:47]\n wire _anonIn_a_ready_T = 1'h1;\t// @[FIFOFixer.scala:96:50]\n wire _anonIn_a_ready_T_1 = 1'h1;\t// @[FIFOFixer.scala:96:47]\n wire anonIn_a_valid = auto_anon_in_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_secure = auto_anon_in_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_user_amba_prot_fetch = auto_anon_in_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_ready = auto_anon_in_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_ready = auto_anon_out_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17]\n wire [7:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_in_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_out_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_in_a_ready_0 = anonIn_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire _anonOut_a_valid_T_2 = anonIn_a_valid;\t// @[FIFOFixer.scala:95:33]\n assign anonOut_a_bits_opcode = anonIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_size = anonIn_a_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_source = anonIn_a_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n wire [3:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n wire [3:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n assign anonOut_a_bits_address = anonIn_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n wire [31:0] _a_notFIFO_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_id_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n assign anonOut_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_secure = anonIn_a_bits_user_amba_prot_secure;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_user_amba_prot_fetch = anonIn_a_bits_user_amba_prot_fetch;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_mask = anonIn_a_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_data = anonIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_d_ready = anonIn_d_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign auto_anon_in_d_valid_0 = anonIn_d_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n assign _anonIn_a_ready_T_2 = anonOut_a_ready;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_out_a_valid_0 = anonOut_a_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_d_ready_0 = anonOut_d_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonIn_d_valid = anonOut_d_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_opcode = anonOut_d_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_param = anonOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_size = anonOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_source = anonOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_sink = anonOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_denied = anonOut_d_bits_denied;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_data = anonOut_d_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_1 = {1'h0, _a_id_T};\t// @[Parameters.scala:137:{31,41}]\n wire _T_5 = anonIn_a_ready & anonIn_a_valid;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_4;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T_4 = _T_5;\t// @[Decoupled.scala:51:35]\n wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T = anonOut_d_ready & anonOut_d_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = anonOut_d_bits_opcode[0];\t// @[Edges.scala:106:36]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6;\t// @[FIFOFixer.scala:75:63]\n wire d_first = d_first_first & _d_first_T_1;\t// @[FIFOFixer.scala:75:{42,63}]\n reg flight_0;\t// @[FIFOFixer.scala:79:27]\n reg flight_1;\t// @[FIFOFixer.scala:79:27]\n reg flight_2;\t// @[FIFOFixer.scala:79:27]\n reg flight_3;\t// @[FIFOFixer.scala:79:27]\n reg flight_4;\t// @[FIFOFixer.scala:79:27]\n reg flight_5;\t// @[FIFOFixer.scala:79:27]\n reg flight_6;\t// @[FIFOFixer.scala:79:27]\n reg flight_7;\t// @[FIFOFixer.scala:79:27]\n reg flight_8;\t// @[FIFOFixer.scala:79:27]\n reg flight_9;\t// @[FIFOFixer.scala:79:27]\n reg flight_10;\t// @[FIFOFixer.scala:79:27]\n reg flight_11;\t// @[FIFOFixer.scala:79:27]\n reg flight_12;\t// @[FIFOFixer.scala:79:27]\n reg flight_13;\t// @[FIFOFixer.scala:79:27]\n reg flight_14;\t// @[FIFOFixer.scala:79:27]\n reg flight_15;\t// @[FIFOFixer.scala:79:27]\n wire _T_9 = anonIn_d_ready & anonIn_d_valid;\t// @[Decoupled.scala:51:35]\n wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _stalls_a_sel_T = anonIn_a_bits_source[3];\t// @[Parameters.scala:54:10]\n wire _stalls_a_sel_T_5 = anonIn_a_bits_source[3];\t// @[Parameters.scala:54:10]\n wire _stalls_a_sel_T_1 = ~_stalls_a_sel_T;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel = _stalls_a_sel_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_3 = _stalls_id_T_1;\t// @[FIFOFixer.scala:85:{47,56}]\n wire _stalls_T = stalls_a_sel & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_1 = flight_0 | flight_1;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_2 = _stalls_T_1 | flight_2;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_3 = _stalls_T_2 | flight_3;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_4 = _stalls_T_3 | flight_4;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_5 = _stalls_T_4 | flight_5;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_6 = _stalls_T_5 | flight_6;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_7 = _stalls_T_6 | flight_7;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_8 = _stalls_T & _stalls_T_7;\t// @[FIFOFixer.scala:88:{15,26,44}]\n wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel_1 = _stalls_a_sel_T_8;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_7 = _stalls_id_T_5;\t// @[FIFOFixer.scala:85:{47,56}]\n wire _stalls_T_11 = stalls_a_sel_1 & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_12 = flight_8 | flight_9;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_13 = _stalls_T_12 | flight_10;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_14 = _stalls_T_13 | flight_11;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_15 = _stalls_T_14 | flight_12;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_16 = _stalls_T_15 | flight_13;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_17 = _stalls_T_16 | flight_14;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_18 = _stalls_T_17 | flight_15;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18;\t// @[FIFOFixer.scala:88:{15,26,44}]\n assign anonOut_a_valid = _anonOut_a_valid_T_2;\t// @[FIFOFixer.scala:95:33]\n assign anonIn_a_ready = _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n reg [15:0] SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35]\n wire [15:0] SourceIdSet;\t// @[FIFOFixer.scala:116:36]\n wire [15:0] SourceIdClear;\t// @[FIFOFixer.scala:117:38]\n wire [15:0] _SourceIdSet_T = 16'h1 << anonIn_a_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [15:0] _SourceIdClear_T = 16'h1 << anonIn_d_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [15:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet;\t// @[FIFOFixer.scala:115:35, :116:36, :126:40]\n wire allIDs_FIFOed = &SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35, :127:41]\n wire _T_1 = a_first & _T_5;\t// @[Decoupled.scala:51:35]\n wire _T_3 = d_first & _T_9;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[FIFOFixer.scala:50:9]\n if (reset) begin\t// @[FIFOFixer.scala:50:9]\n a_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n d_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n flight_0 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_1 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_2 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_3 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_4 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_5 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_6 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_7 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_8 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_9 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_10 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_11 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_12 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_13 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_14 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_15 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n SourceIdFIFOed <= 16'h0;\t// @[FIFOFixer.scala:115:35]\n end\n else begin\t// @[FIFOFixer.scala:50:9]\n if (_a_first_T)\t// @[Decoupled.scala:51:35]\n a_first_counter <= _a_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n if (_d_first_T)\t// @[Decoupled.scala:51:35]\n d_first_counter <= _d_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n flight_0 <= ~(_T_3 & anonIn_d_bits_source == 4'h0) & (_T_1 & anonIn_a_bits_source == 4'h0 | flight_0);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_1 <= ~(_T_3 & anonIn_d_bits_source == 4'h1) & (_T_1 & anonIn_a_bits_source == 4'h1 | flight_1);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_2 <= ~(_T_3 & anonIn_d_bits_source == 4'h2) & (_T_1 & anonIn_a_bits_source == 4'h2 | flight_2);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_3 <= ~(_T_3 & anonIn_d_bits_source == 4'h3) & (_T_1 & anonIn_a_bits_source == 4'h3 | flight_3);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_4 <= ~(_T_3 & anonIn_d_bits_source == 4'h4) & (_T_1 & anonIn_a_bits_source == 4'h4 | flight_4);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_5 <= ~(_T_3 & anonIn_d_bits_source == 4'h5) & (_T_1 & anonIn_a_bits_source == 4'h5 | flight_5);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_6 <= ~(_T_3 & anonIn_d_bits_source == 4'h6) & (_T_1 & anonIn_a_bits_source == 4'h6 | flight_6);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_7 <= ~(_T_3 & anonIn_d_bits_source == 4'h7) & (_T_1 & anonIn_a_bits_source == 4'h7 | flight_7);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_8 <= ~(_T_3 & anonIn_d_bits_source == 4'h8) & (_T_1 & anonIn_a_bits_source == 4'h8 | flight_8);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_9 <= ~(_T_3 & anonIn_d_bits_source == 4'h9) & (_T_1 & anonIn_a_bits_source == 4'h9 | flight_9);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_10 <= ~(_T_3 & anonIn_d_bits_source == 4'hA) & (_T_1 & anonIn_a_bits_source == 4'hA | flight_10);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_11 <= ~(_T_3 & anonIn_d_bits_source == 4'hB) & (_T_1 & anonIn_a_bits_source == 4'hB | flight_11);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_12 <= ~(_T_3 & anonIn_d_bits_source == 4'hC) & (_T_1 & anonIn_a_bits_source == 4'hC | flight_12);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_13 <= ~(_T_3 & anonIn_d_bits_source == 4'hD) & (_T_1 & anonIn_a_bits_source == 4'hD | flight_13);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_14 <= ~(_T_3 & anonIn_d_bits_source == 4'hE) & (_T_1 & anonIn_a_bits_source == 4'hE | flight_14);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_15 <= ~(_T_3 & (&anonIn_d_bits_source)) & (_T_1 & (&anonIn_a_bits_source) | flight_15);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n SourceIdFIFOed <= _SourceIdFIFOed_T;\t// @[FIFOFixer.scala:115:35, :126:40]\n end\n always @(posedge)\n TLMonitor_19 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (anonIn_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (anonIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (anonIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_size (anonIn_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_source (anonIn_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (anonIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_bufferable (anonIn_a_bits_user_amba_prot_bufferable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_modifiable (anonIn_a_bits_user_amba_prot_modifiable),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_readalloc (anonIn_a_bits_user_amba_prot_readalloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_writealloc (anonIn_a_bits_user_amba_prot_writealloc),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_privileged (anonIn_a_bits_user_amba_prot_privileged),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_secure (anonIn_a_bits_user_amba_prot_secure),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_user_amba_prot_fetch (anonIn_a_bits_user_amba_prot_fetch),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_mask (anonIn_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (anonIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (anonIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (anonIn_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (anonIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (anonIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (anonIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (anonIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (anonIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (anonIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (anonIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (anonIn_d_bits_corrupt)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n assign auto_anon_in_a_ready = auto_anon_in_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_valid = auto_anon_in_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_valid = auto_anon_out_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_bufferable = auto_anon_out_a_bits_user_amba_prot_bufferable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_modifiable = auto_anon_out_a_bits_user_amba_prot_modifiable_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_readalloc = auto_anon_out_a_bits_user_amba_prot_readalloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_writealloc = auto_anon_out_a_bits_user_amba_prot_writealloc_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_privileged = auto_anon_out_a_bits_user_amba_prot_privileged_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_secure = auto_anon_out_a_bits_user_amba_prot_secure_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_user_amba_prot_fetch = auto_anon_out_a_bits_user_amba_prot_fetch_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_d_ready = auto_anon_out_d_ready_0;\t// @[FIFOFixer.scala:50:9]\nendmodule"}}},{"rowIdx":5099,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile util.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}\nFile consts.scala:\n//******************************************************************************\n// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Constants\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.common.constants\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.Str\nimport freechips.rocketchip.rocket.RVCExpander\n\n/**\n * Mixin for issue queue types\n */\ntrait IQType\n{\n val IQT_SZ = 3\n val IQT_INT = 1.U(IQT_SZ.W)\n val IQT_MEM = 2.U(IQT_SZ.W)\n val IQT_FP = 4.U(IQT_SZ.W)\n\n val IQT_MFP = 6.U(IQT_SZ.W)\n}\n\n\n/**\n * Mixin for scalar operation constants\n */\ntrait ScalarOpConstants\n{\n val X = BitPat(\"b?\")\n val Y = BitPat(\"b1\")\n val N = BitPat(\"b0\")\n\n //************************************\n // Extra Constants\n\n // Which branch predictor predicted us\n val BSRC_SZ = 2\n val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred\n val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred\n val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred\n val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution\n\n //************************************\n // Control Signals\n\n // CFI types\n val CFI_SZ = 3\n val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction\n val CFI_BR = 1.U(CFI_SZ.W) // Branch\n val CFI_JAL = 2.U(CFI_SZ.W) // JAL\n val CFI_JALR = 3.U(CFI_SZ.W) // JALR\n\n // PC Select Signal\n val PC_PLUS4 = 0.U(2.W) // PC + 4\n val PC_BRJMP = 1.U(2.W) // brjmp_target\n val PC_JALR = 2.U(2.W) // jump_reg_target\n\n // Branch Type\n val BR_N = 0.U(4.W) // Next\n val BR_NE = 1.U(4.W) // Branch on NotEqual\n val BR_EQ = 2.U(4.W) // Branch on Equal\n val BR_GE = 3.U(4.W) // Branch on Greater/Equal\n val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned\n val BR_LT = 5.U(4.W) // Branch on Less Than\n val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned\n val BR_J = 7.U(4.W) // Jump\n val BR_JR = 8.U(4.W) // Jump Register\n\n // RS1 Operand Select Signal\n val OP1_RS1 = 0.U(2.W) // Register Source #1\n val OP1_ZERO= 1.U(2.W)\n val OP1_PC = 2.U(2.W)\n val OP1_X = BitPat(\"b??\")\n\n // RS2 Operand Select Signal\n val OP2_RS2 = 0.U(3.W) // Register Source #2\n val OP2_IMM = 1.U(3.W) // immediate\n val OP2_ZERO= 2.U(3.W) // constant 0\n val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)\n val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1\n val OP2_X = BitPat(\"b???\")\n\n // Register File Write Enable Signal\n val REN_0 = false.B\n val REN_1 = true.B\n\n // Is 32b Word or 64b Doubldword?\n val SZ_DW = 1\n val DW_X = true.B // Bool(xLen==64)\n val DW_32 = false.B\n val DW_64 = true.B\n val DW_XPR = true.B // Bool(xLen==64)\n\n // Memory Enable Signal\n val MEN_0 = false.B\n val MEN_1 = true.B\n val MEN_X = false.B\n\n // Immediate Extend Select\n val IS_I = 0.U(3.W) // I-Type (LD,ALU)\n val IS_S = 1.U(3.W) // S-Type (ST)\n val IS_B = 2.U(3.W) // SB-Type (BR)\n val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)\n val IS_J = 4.U(3.W) // UJ-Type (J/JAL)\n val IS_X = BitPat(\"b???\")\n\n // Decode Stage Control Signals\n val RT_FIX = 0.U(2.W)\n val RT_FLT = 1.U(2.W)\n val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)\n val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)\n // TODO rename RT_NAR\n\n // Micro-op opcodes\n // TODO change micro-op opcodes into using enum\n val UOPC_SZ = 7\n val uopX = BitPat.dontCare(UOPC_SZ)\n val uopNOP = 0.U(UOPC_SZ.W)\n val uopLD = 1.U(UOPC_SZ.W)\n val uopSTA = 2.U(UOPC_SZ.W) // store address generation\n val uopSTD = 3.U(UOPC_SZ.W) // store data generation\n val uopLUI = 4.U(UOPC_SZ.W)\n\n val uopADDI = 5.U(UOPC_SZ.W)\n val uopANDI = 6.U(UOPC_SZ.W)\n val uopORI = 7.U(UOPC_SZ.W)\n val uopXORI = 8.U(UOPC_SZ.W)\n val uopSLTI = 9.U(UOPC_SZ.W)\n val uopSLTIU= 10.U(UOPC_SZ.W)\n val uopSLLI = 11.U(UOPC_SZ.W)\n val uopSRAI = 12.U(UOPC_SZ.W)\n val uopSRLI = 13.U(UOPC_SZ.W)\n\n val uopSLL = 14.U(UOPC_SZ.W)\n val uopADD = 15.U(UOPC_SZ.W)\n val uopSUB = 16.U(UOPC_SZ.W)\n val uopSLT = 17.U(UOPC_SZ.W)\n val uopSLTU = 18.U(UOPC_SZ.W)\n val uopAND = 19.U(UOPC_SZ.W)\n val uopOR = 20.U(UOPC_SZ.W)\n val uopXOR = 21.U(UOPC_SZ.W)\n val uopSRA = 22.U(UOPC_SZ.W)\n val uopSRL = 23.U(UOPC_SZ.W)\n\n val uopBEQ = 24.U(UOPC_SZ.W)\n val uopBNE = 25.U(UOPC_SZ.W)\n val uopBGE = 26.U(UOPC_SZ.W)\n val uopBGEU = 27.U(UOPC_SZ.W)\n val uopBLT = 28.U(UOPC_SZ.W)\n val uopBLTU = 29.U(UOPC_SZ.W)\n val uopCSRRW= 30.U(UOPC_SZ.W)\n val uopCSRRS= 31.U(UOPC_SZ.W)\n val uopCSRRC= 32.U(UOPC_SZ.W)\n val uopCSRRWI=33.U(UOPC_SZ.W)\n val uopCSRRSI=34.U(UOPC_SZ.W)\n val uopCSRRCI=35.U(UOPC_SZ.W)\n\n val uopJ = 36.U(UOPC_SZ.W)\n val uopJAL = 37.U(UOPC_SZ.W)\n val uopJALR = 38.U(UOPC_SZ.W)\n val uopAUIPC= 39.U(UOPC_SZ.W)\n\n//val uopSRET = 40.U(UOPC_SZ.W)\n val uopCFLSH= 41.U(UOPC_SZ.W)\n val uopFENCE= 42.U(UOPC_SZ.W)\n\n val uopADDIW= 43.U(UOPC_SZ.W)\n val uopADDW = 44.U(UOPC_SZ.W)\n val uopSUBW = 45.U(UOPC_SZ.W)\n val uopSLLIW= 46.U(UOPC_SZ.W)\n val uopSLLW = 47.U(UOPC_SZ.W)\n val uopSRAIW= 48.U(UOPC_SZ.W)\n val uopSRAW = 49.U(UOPC_SZ.W)\n val uopSRLIW= 50.U(UOPC_SZ.W)\n val uopSRLW = 51.U(UOPC_SZ.W)\n val uopMUL = 52.U(UOPC_SZ.W)\n val uopMULH = 53.U(UOPC_SZ.W)\n val uopMULHU= 54.U(UOPC_SZ.W)\n val uopMULHSU=55.U(UOPC_SZ.W)\n val uopMULW = 56.U(UOPC_SZ.W)\n val uopDIV = 57.U(UOPC_SZ.W)\n val uopDIVU = 58.U(UOPC_SZ.W)\n val uopREM = 59.U(UOPC_SZ.W)\n val uopREMU = 60.U(UOPC_SZ.W)\n val uopDIVW = 61.U(UOPC_SZ.W)\n val uopDIVUW= 62.U(UOPC_SZ.W)\n val uopREMW = 63.U(UOPC_SZ.W)\n val uopREMUW= 64.U(UOPC_SZ.W)\n\n val uopFENCEI = 65.U(UOPC_SZ.W)\n // = 66.U(UOPC_SZ.W)\n val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)\n\n val uopFMV_W_X = 68.U(UOPC_SZ.W)\n val uopFMV_D_X = 69.U(UOPC_SZ.W)\n val uopFMV_X_W = 70.U(UOPC_SZ.W)\n val uopFMV_X_D = 71.U(UOPC_SZ.W)\n\n val uopFSGNJ_S = 72.U(UOPC_SZ.W)\n val uopFSGNJ_D = 73.U(UOPC_SZ.W)\n\n val uopFCVT_S_D = 74.U(UOPC_SZ.W)\n val uopFCVT_D_S = 75.U(UOPC_SZ.W)\n\n val uopFCVT_S_X = 76.U(UOPC_SZ.W)\n val uopFCVT_D_X = 77.U(UOPC_SZ.W)\n\n val uopFCVT_X_S = 78.U(UOPC_SZ.W)\n val uopFCVT_X_D = 79.U(UOPC_SZ.W)\n\n val uopCMPR_S = 80.U(UOPC_SZ.W)\n val uopCMPR_D = 81.U(UOPC_SZ.W)\n\n val uopFCLASS_S = 82.U(UOPC_SZ.W)\n val uopFCLASS_D = 83.U(UOPC_SZ.W)\n\n val uopFMINMAX_S = 84.U(UOPC_SZ.W)\n val uopFMINMAX_D = 85.U(UOPC_SZ.W)\n\n // = 86.U(UOPC_SZ.W)\n val uopFADD_S = 87.U(UOPC_SZ.W)\n val uopFSUB_S = 88.U(UOPC_SZ.W)\n val uopFMUL_S = 89.U(UOPC_SZ.W)\n val uopFADD_D = 90.U(UOPC_SZ.W)\n val uopFSUB_D = 91.U(UOPC_SZ.W)\n val uopFMUL_D = 92.U(UOPC_SZ.W)\n\n val uopFMADD_S = 93.U(UOPC_SZ.W)\n val uopFMSUB_S = 94.U(UOPC_SZ.W)\n val uopFNMADD_S = 95.U(UOPC_SZ.W)\n val uopFNMSUB_S = 96.U(UOPC_SZ.W)\n val uopFMADD_D = 97.U(UOPC_SZ.W)\n val uopFMSUB_D = 98.U(UOPC_SZ.W)\n val uopFNMADD_D = 99.U(UOPC_SZ.W)\n val uopFNMSUB_D = 100.U(UOPC_SZ.W)\n\n val uopFDIV_S = 101.U(UOPC_SZ.W)\n val uopFDIV_D = 102.U(UOPC_SZ.W)\n val uopFSQRT_S = 103.U(UOPC_SZ.W)\n val uopFSQRT_D = 104.U(UOPC_SZ.W)\n\n val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline\n val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET\n val uopSFENCE = 107.U(UOPC_SZ.W)\n\n val uopROCC = 108.U(UOPC_SZ.W)\n\n val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from \"add rd, x0, rs2\"\n\n // The Bubble Instruction (Machine generated NOP)\n // Insert (XOR x0,x0,x0) which is different from software compiler\n // generated NOPs which are (ADDI x0, x0, 0).\n // Reasoning for this is to let visualizers and stat-trackers differentiate\n // between software NOPs and machine-generated Bubbles in the pipeline.\n val BUBBLE = (0x4033).U(32.W)\n\n def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {\n val uop = Wire(new boom.v3.common.MicroOp)\n uop := DontCare // Overridden in the following lines\n uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior\n uop.bypassable := false.B\n uop.fp_val := false.B\n uop.uses_stq := false.B\n uop.uses_ldq := false.B\n uop.pdst := 0.U\n uop.dst_rtype := RT_X\n\n val cs = Wire(new boom.v3.common.CtrlSignals())\n cs := DontCare // Overridden in the following lines\n cs.br_type := BR_N\n cs.csr_cmd := freechips.rocketchip.rocket.CSR.N\n cs.is_load := false.B\n cs.is_sta := false.B\n cs.is_std := false.B\n\n uop.ctrl := cs\n uop\n }\n}\n\n/**\n * Mixin for RISCV constants\n */\ntrait RISCVConstants\n{\n // abstract out instruction decode magic numbers\n val RD_MSB = 11\n val RD_LSB = 7\n val RS1_MSB = 19\n val RS1_LSB = 15\n val RS2_MSB = 24\n val RS2_LSB = 20\n val RS3_MSB = 31\n val RS3_LSB = 27\n\n val CSR_ADDR_MSB = 31\n val CSR_ADDR_LSB = 20\n val CSR_ADDR_SZ = 12\n\n // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)\n val SHAMT_5_BIT = 25\n val LONGEST_IMM_SZ = 20\n val X0 = 0.U\n val RA = 1.U // return address register\n\n // memory consistency model\n // The C/C++ atomics MCM requires that two loads to the same address maintain program order.\n // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).\n val MCM_ORDER_DEPENDENT_LOADS = true\n\n val jal_opc = (0x6f).U\n val jalr_opc = (0x67).U\n\n def GetUop(inst: UInt): UInt = inst(6,0)\n def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)\n def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)\n\n def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {\n val rvc_exp = Module(new RVCExpander)\n rvc_exp.io.in := inst\n Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {\n val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {\n val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt\n }\n\n // Note: Accepts only EXPANDED rvc instructions\n def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {\n val bdecode = Module(new boom.v3.exu.BranchDecode)\n bdecode.io.inst := inst\n bdecode.io.pc := 0.U\n bdecode.io.out.cfi_type\n }\n}\n\n/**\n * Mixin for exception cause constants\n */\ntrait ExcCauseConstants\n{\n // a memory disambigious misspeculation occurred\n val MINI_EXCEPTION_MEM_ORDERING = 16.U\n val MINI_EXCEPTION_CSR_REPLAY = 17.U\n\n require (!freechips.rocketchip.rocket.Causes.all.contains(16))\n require (!freechips.rocketchip.rocket.Causes.all.contains(17))\n}\nFile issue-slot.scala:\n//******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Issue Slot Logic\n//--------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Note: stores (and AMOs) are \"broken down\" into 2 uops, but stored within a single issue-slot.\n// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.\n// TODO Disable ldspec for FP queue.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\nimport FUConstants._\n\n/**\n * IO bundle to interact with Issue slot\n *\n * @param numWakeupPorts number of wakeup ports for the slot\n */\nclass IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle\n{\n val valid = Output(Bool())\n val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?\n val request = Output(Bool())\n val request_hp = Output(Bool())\n val grant = Input(Bool())\n\n val brupdate = Input(new BrUpdateInfo())\n val kill = Input(Bool()) // pipeline flush\n val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)\n val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.\n\n val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))\n val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))\n val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))\n val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!\n val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.\n val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.\n\n val debug = {\n val result = new Bundle {\n val p1 = Bool()\n val p2 = Bool()\n val p3 = Bool()\n val ppred = Bool()\n val state = UInt(width=2.W)\n }\n Output(result)\n }\n}\n\n/**\n * Single issue slot. Holds a uop within the issue queue\n *\n * @param numWakeupPorts number of wakeup ports\n */\nclass IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)\n extends BoomModule\n with IssueUnitConstants\n{\n val io = IO(new IssueSlotIO(numWakeupPorts))\n\n // slot invalid?\n // slot is valid, holding 1 uop\n // slot is valid, holds 2 uops (like a store)\n def is_invalid = state === s_invalid\n def is_valid = state =/= s_invalid\n\n val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)\n val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)\n val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n\n val state = RegInit(s_invalid)\n val p1 = RegInit(false.B)\n val p2 = RegInit(false.B)\n val p3 = RegInit(false.B)\n val ppred = RegInit(false.B)\n\n // Poison if woken up by speculative load.\n // Poison lasts 1 cycle (as ldMiss will come on the next cycle).\n // SO if poisoned is true, set it to false!\n val p1_poisoned = RegInit(false.B)\n val p2_poisoned = RegInit(false.B)\n p1_poisoned := false.B\n p2_poisoned := false.B\n val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)\n val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)\n\n val slot_uop = RegInit(NullMicroOp)\n val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)\n\n //-----------------------------------------------------------------------------\n // next slot state computation\n // compute the next state for THIS entry slot (in a collasping queue, the\n // current uop may get moved elsewhere, and a new uop can enter\n\n when (io.kill) {\n state := s_invalid\n } .elsewhen (io.in_uop.valid) {\n state := io.in_uop.bits.iw_state\n } .elsewhen (io.clear) {\n state := s_invalid\n } .otherwise {\n state := next_state\n }\n\n //-----------------------------------------------------------------------------\n // \"update\" state\n // compute the next state for the micro-op in this slot. This micro-op may\n // be moved elsewhere, so the \"next_state\" travels with it.\n\n // defaults\n next_state := state\n next_uopc := slot_uop.uopc\n next_lrs1_rtype := slot_uop.lrs1_rtype\n next_lrs2_rtype := slot_uop.lrs2_rtype\n\n when (io.kill) {\n next_state := s_invalid\n } .elsewhen ((io.grant && (state === s_valid_1)) ||\n (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {\n // try to issue this uop.\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_invalid\n }\n } .elsewhen (io.grant && (state === s_valid_2)) {\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_valid_1\n when (p1) {\n slot_uop.uopc := uopSTD\n next_uopc := uopSTD\n slot_uop.lrs1_rtype := RT_X\n next_lrs1_rtype := RT_X\n } .otherwise {\n slot_uop.lrs2_rtype := RT_X\n next_lrs2_rtype := RT_X\n }\n }\n }\n\n when (io.in_uop.valid) {\n slot_uop := io.in_uop.bits\n assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n }\n\n // Wakeup Compare Logic\n\n // these signals are the \"next_p*\" for the current slot's micro-op.\n // they are important for shifting the current slot_uop up to an other entry.\n val next_p1 = WireInit(p1)\n val next_p2 = WireInit(p2)\n val next_p3 = WireInit(p3)\n val next_ppred = WireInit(ppred)\n\n when (io.in_uop.valid) {\n p1 := !(io.in_uop.bits.prs1_busy)\n p2 := !(io.in_uop.bits.prs2_busy)\n p3 := !(io.in_uop.bits.prs3_busy)\n ppred := !(io.in_uop.bits.ppred_busy)\n }\n\n when (io.ldspec_miss && next_p1_poisoned) {\n assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n p1 := false.B\n }\n when (io.ldspec_miss && next_p2_poisoned) {\n assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n p2 := false.B\n }\n\n for (i <- 0 until numWakeupPorts) {\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {\n p1 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {\n p2 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {\n p3 := true.B\n }\n }\n when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {\n ppred := true.B\n }\n\n for (w <- 0 until memWidth) {\n assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n \"Loads to x0 should never speculatively wakeup other instructions\")\n }\n\n // TODO disable if FP IQ.\n for (w <- 0 until memWidth) {\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs1 &&\n next_uop.lrs1_rtype === RT_FIX) {\n p1 := true.B\n p1_poisoned := true.B\n assert (!next_p1_poisoned)\n }\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs2 &&\n next_uop.lrs2_rtype === RT_FIX) {\n p2 := true.B\n p2_poisoned := true.B\n assert (!next_p2_poisoned)\n }\n }\n\n\n // Handle branch misspeculations\n val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)\n\n // was this micro-op killed by a branch? if yes, we can't let it be valid if\n // we compact it into an other entry\n when (IsKilledByBranch(io.brupdate, slot_uop)) {\n next_state := s_invalid\n }\n\n when (!io.in_uop.valid) {\n slot_uop.br_mask := next_br_mask\n }\n\n //-------------------------------------------------------------\n // Request Logic\n io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill\n val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr\n io.request_hp := io.request && high_priority\n\n when (state === s_valid_1) {\n io.request := p1 && p2 && p3 && ppred && !io.kill\n } .elsewhen (state === s_valid_2) {\n io.request := (p1 || p2) && ppred && !io.kill\n } .otherwise {\n io.request := false.B\n }\n\n //assign outputs\n io.valid := is_valid\n io.uop := slot_uop\n io.uop.iw_p1_poisoned := p1_poisoned\n io.uop.iw_p2_poisoned := p2_poisoned\n\n // micro-op will vacate due to grant.\n val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)\n val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)\n io.will_be_valid := is_valid && !(may_vacate && !squash_grant)\n\n io.out_uop := slot_uop\n io.out_uop.iw_state := next_state\n io.out_uop.uopc := next_uopc\n io.out_uop.lrs1_rtype := next_lrs1_rtype\n io.out_uop.lrs2_rtype := next_lrs2_rtype\n io.out_uop.br_mask := next_br_mask\n io.out_uop.prs1_busy := !p1\n io.out_uop.prs2_busy := !p2\n io.out_uop.prs3_busy := !p3\n io.out_uop.ppred_busy := !ppred\n io.out_uop.iw_p1_poisoned := p1_poisoned\n io.out_uop.iw_p2_poisoned := p2_poisoned\n\n when (state === s_valid_2) {\n when (p1 && p2 && ppred) {\n ; // send out the entire instruction as one uop\n } .elsewhen (p1 && ppred) {\n io.uop.uopc := slot_uop.uopc\n io.uop.lrs2_rtype := RT_X\n } .elsewhen (p2 && ppred) {\n io.uop.uopc := uopSTD\n io.uop.lrs1_rtype := RT_X\n }\n }\n\n // debug outputs\n io.debug.p1 := p1\n io.debug.p2 := p2\n io.debug.p3 := p3\n io.debug.ppred := ppred\n io.debug.state := state\n}\n"},"response":{"kind":"string","value":"module IssueSlot_135(\t// @[issue-slot.scala:69:7]\n input clock,\t// @[issue-slot.scala:69:7]\n input reset,\t// @[issue-slot.scala:69:7]\n output io_valid,\t// @[issue-slot.scala:73:14]\n output io_will_be_valid,\t// @[issue-slot.scala:73:14]\n output io_request,\t// @[issue-slot.scala:73:14]\n output io_request_hp,\t// @[issue-slot.scala:73:14]\n input io_grant,\t// @[issue-slot.scala:73:14]\n input [15:0] io_brupdate_b1_resolve_mask,\t// @[issue-slot.scala:73:14]\n input [15:0] io_brupdate_b1_mispredict_mask,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_uopc,\t// @[issue-slot.scala:73:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[issue-slot.scala:73:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[issue-slot.scala:73:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[issue-slot.scala:73:14]\n input [2:0] io_brupdate_b2_uop_iq_type,\t// @[issue-slot.scala:73:14]\n input [9:0] io_brupdate_b2_uop_fu_code,\t// @[issue-slot.scala:73:14]\n input [3:0] io_brupdate_b2_uop_ctrl_br_type,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_ctrl_op1_sel,\t// @[issue-slot.scala:73:14]\n input [2:0] io_brupdate_b2_uop_ctrl_op2_sel,\t// @[issue-slot.scala:73:14]\n input [2:0] io_brupdate_b2_uop_ctrl_imm_sel,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_ctrl_op_fcn,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ctrl_fcn_dw,\t// @[issue-slot.scala:73:14]\n input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ctrl_is_load,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ctrl_is_sta,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ctrl_is_std,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_iw_state,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_iw_p1_poisoned,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_iw_p2_poisoned,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_br,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_jalr,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_jal,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[issue-slot.scala:73:14]\n input [15:0] io_brupdate_b2_uop_br_mask,\t// @[issue-slot.scala:73:14]\n input [3:0] io_brupdate_b2_uop_br_tag,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_ftq_idx,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[issue-slot.scala:73:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_taken,\t// @[issue-slot.scala:73:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[issue-slot.scala:73:14]\n input [11:0] io_brupdate_b2_uop_csr_addr,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_rob_idx,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_ldq_idx,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_stq_idx,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_pdst,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_prs1,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_prs2,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_prs3,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_ppred,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[issue-slot.scala:73:14]\n input [6:0] io_brupdate_b2_uop_stale_pdst,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_exception,\t// @[issue-slot.scala:73:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_bypassable,\t// @[issue-slot.scala:73:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_fence,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_amo,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_is_unique,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[issue-slot.scala:73:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[issue-slot.scala:73:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[issue-slot.scala:73:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[issue-slot.scala:73:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_ldst_val,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_fp_val,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_fp_single,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_debug_fsrc,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_uop_debug_tsrc,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_valid,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_mispredict,\t// @[issue-slot.scala:73:14]\n input io_brupdate_b2_taken,\t// @[issue-slot.scala:73:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[issue-slot.scala:73:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[issue-slot.scala:73:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[issue-slot.scala:73:14]\n input [20:0] io_brupdate_b2_target_offset,\t// @[issue-slot.scala:73:14]\n input io_kill,\t// @[issue-slot.scala:73:14]\n input io_clear,\t// @[issue-slot.scala:73:14]\n input io_ldspec_miss,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_0_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_0_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_0_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_1_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_1_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_1_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_2_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_2_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_2_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_3_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_3_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_3_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_4_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_4_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_4_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_5_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_5_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_5_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_6_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_wakeup_ports_6_bits_pdst,\t// @[issue-slot.scala:73:14]\n input io_wakeup_ports_6_bits_poisoned,\t// @[issue-slot.scala:73:14]\n input io_spec_ld_wakeup_0_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_spec_ld_wakeup_0_bits,\t// @[issue-slot.scala:73:14]\n input io_in_uop_valid,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_uopc,\t// @[issue-slot.scala:73:14]\n input [31:0] io_in_uop_bits_inst,\t// @[issue-slot.scala:73:14]\n input [31:0] io_in_uop_bits_debug_inst,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_rvc,\t// @[issue-slot.scala:73:14]\n input [39:0] io_in_uop_bits_debug_pc,\t// @[issue-slot.scala:73:14]\n input [2:0] io_in_uop_bits_iq_type,\t// @[issue-slot.scala:73:14]\n input [9:0] io_in_uop_bits_fu_code,\t// @[issue-slot.scala:73:14]\n input [3:0] io_in_uop_bits_ctrl_br_type,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_ctrl_op1_sel,\t// @[issue-slot.scala:73:14]\n input [2:0] io_in_uop_bits_ctrl_op2_sel,\t// @[issue-slot.scala:73:14]\n input [2:0] io_in_uop_bits_ctrl_imm_sel,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_ctrl_op_fcn,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ctrl_fcn_dw,\t// @[issue-slot.scala:73:14]\n input [2:0] io_in_uop_bits_ctrl_csr_cmd,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ctrl_is_load,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ctrl_is_sta,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ctrl_is_std,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_iw_state,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_iw_p1_poisoned,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_iw_p2_poisoned,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_br,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_jalr,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_jal,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_sfb,\t// @[issue-slot.scala:73:14]\n input [15:0] io_in_uop_bits_br_mask,\t// @[issue-slot.scala:73:14]\n input [3:0] io_in_uop_bits_br_tag,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_ftq_idx,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_edge_inst,\t// @[issue-slot.scala:73:14]\n input [5:0] io_in_uop_bits_pc_lob,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_taken,\t// @[issue-slot.scala:73:14]\n input [19:0] io_in_uop_bits_imm_packed,\t// @[issue-slot.scala:73:14]\n input [11:0] io_in_uop_bits_csr_addr,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_rob_idx,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_ldq_idx,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_stq_idx,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_rxq_idx,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_pdst,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_prs1,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_prs2,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_prs3,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_ppred,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_prs1_busy,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_prs2_busy,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_prs3_busy,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ppred_busy,\t// @[issue-slot.scala:73:14]\n input [6:0] io_in_uop_bits_stale_pdst,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_exception,\t// @[issue-slot.scala:73:14]\n input [63:0] io_in_uop_bits_exc_cause,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_bypassable,\t// @[issue-slot.scala:73:14]\n input [4:0] io_in_uop_bits_mem_cmd,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_mem_size,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_mem_signed,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_fence,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_fencei,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_amo,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_uses_ldq,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_uses_stq,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_sys_pc2epc,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_is_unique,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_flush_on_commit,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ldst_is_rs1,\t// @[issue-slot.scala:73:14]\n input [5:0] io_in_uop_bits_ldst,\t// @[issue-slot.scala:73:14]\n input [5:0] io_in_uop_bits_lrs1,\t// @[issue-slot.scala:73:14]\n input [5:0] io_in_uop_bits_lrs2,\t// @[issue-slot.scala:73:14]\n input [5:0] io_in_uop_bits_lrs3,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_ldst_val,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_dst_rtype,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_lrs1_rtype,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_lrs2_rtype,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_frs3_en,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_fp_val,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_fp_single,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_xcpt_pf_if,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_xcpt_ae_if,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_xcpt_ma_if,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_bp_debug_if,\t// @[issue-slot.scala:73:14]\n input io_in_uop_bits_bp_xcpt_if,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_debug_fsrc,\t// @[issue-slot.scala:73:14]\n input [1:0] io_in_uop_bits_debug_tsrc,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_uopc,\t// @[issue-slot.scala:73:14]\n output [31:0] io_out_uop_inst,\t// @[issue-slot.scala:73:14]\n output [31:0] io_out_uop_debug_inst,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_rvc,\t// @[issue-slot.scala:73:14]\n output [39:0] io_out_uop_debug_pc,\t// @[issue-slot.scala:73:14]\n output [2:0] io_out_uop_iq_type,\t// @[issue-slot.scala:73:14]\n output [9:0] io_out_uop_fu_code,\t// @[issue-slot.scala:73:14]\n output [3:0] io_out_uop_ctrl_br_type,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_ctrl_op1_sel,\t// @[issue-slot.scala:73:14]\n output [2:0] io_out_uop_ctrl_op2_sel,\t// @[issue-slot.scala:73:14]\n output [2:0] io_out_uop_ctrl_imm_sel,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_ctrl_op_fcn,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ctrl_fcn_dw,\t// @[issue-slot.scala:73:14]\n output [2:0] io_out_uop_ctrl_csr_cmd,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ctrl_is_load,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ctrl_is_sta,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ctrl_is_std,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_iw_state,\t// @[issue-slot.scala:73:14]\n output io_out_uop_iw_p1_poisoned,\t// @[issue-slot.scala:73:14]\n output io_out_uop_iw_p2_poisoned,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_br,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_jalr,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_jal,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_sfb,\t// @[issue-slot.scala:73:14]\n output [15:0] io_out_uop_br_mask,\t// @[issue-slot.scala:73:14]\n output [3:0] io_out_uop_br_tag,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_ftq_idx,\t// @[issue-slot.scala:73:14]\n output io_out_uop_edge_inst,\t// @[issue-slot.scala:73:14]\n output [5:0] io_out_uop_pc_lob,\t// @[issue-slot.scala:73:14]\n output io_out_uop_taken,\t// @[issue-slot.scala:73:14]\n output [19:0] io_out_uop_imm_packed,\t// @[issue-slot.scala:73:14]\n output [11:0] io_out_uop_csr_addr,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_rob_idx,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_ldq_idx,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_stq_idx,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_rxq_idx,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_pdst,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_prs1,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_prs2,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_prs3,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_ppred,\t// @[issue-slot.scala:73:14]\n output io_out_uop_prs1_busy,\t// @[issue-slot.scala:73:14]\n output io_out_uop_prs2_busy,\t// @[issue-slot.scala:73:14]\n output io_out_uop_prs3_busy,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ppred_busy,\t// @[issue-slot.scala:73:14]\n output [6:0] io_out_uop_stale_pdst,\t// @[issue-slot.scala:73:14]\n output io_out_uop_exception,\t// @[issue-slot.scala:73:14]\n output [63:0] io_out_uop_exc_cause,\t// @[issue-slot.scala:73:14]\n output io_out_uop_bypassable,\t// @[issue-slot.scala:73:14]\n output [4:0] io_out_uop_mem_cmd,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_mem_size,\t// @[issue-slot.scala:73:14]\n output io_out_uop_mem_signed,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_fence,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_fencei,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_amo,\t// @[issue-slot.scala:73:14]\n output io_out_uop_uses_ldq,\t// @[issue-slot.scala:73:14]\n output io_out_uop_uses_stq,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_sys_pc2epc,\t// @[issue-slot.scala:73:14]\n output io_out_uop_is_unique,\t// @[issue-slot.scala:73:14]\n output io_out_uop_flush_on_commit,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ldst_is_rs1,\t// @[issue-slot.scala:73:14]\n output [5:0] io_out_uop_ldst,\t// @[issue-slot.scala:73:14]\n output [5:0] io_out_uop_lrs1,\t// @[issue-slot.scala:73:14]\n output [5:0] io_out_uop_lrs2,\t// @[issue-slot.scala:73:14]\n output [5:0] io_out_uop_lrs3,\t// @[issue-slot.scala:73:14]\n output io_out_uop_ldst_val,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_dst_rtype,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_lrs1_rtype,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_lrs2_rtype,\t// @[issue-slot.scala:73:14]\n output io_out_uop_frs3_en,\t// @[issue-slot.scala:73:14]\n output io_out_uop_fp_val,\t// @[issue-slot.scala:73:14]\n output io_out_uop_fp_single,\t// @[issue-slot.scala:73:14]\n output io_out_uop_xcpt_pf_if,\t// @[issue-slot.scala:73:14]\n output io_out_uop_xcpt_ae_if,\t// @[issue-slot.scala:73:14]\n output io_out_uop_xcpt_ma_if,\t// @[issue-slot.scala:73:14]\n output io_out_uop_bp_debug_if,\t// @[issue-slot.scala:73:14]\n output io_out_uop_bp_xcpt_if,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_debug_fsrc,\t// @[issue-slot.scala:73:14]\n output [1:0] io_out_uop_debug_tsrc,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_uopc,\t// @[issue-slot.scala:73:14]\n output [31:0] io_uop_inst,\t// @[issue-slot.scala:73:14]\n output [31:0] io_uop_debug_inst,\t// @[issue-slot.scala:73:14]\n output io_uop_is_rvc,\t// @[issue-slot.scala:73:14]\n output [39:0] io_uop_debug_pc,\t// @[issue-slot.scala:73:14]\n output [2:0] io_uop_iq_type,\t// @[issue-slot.scala:73:14]\n output [9:0] io_uop_fu_code,\t// @[issue-slot.scala:73:14]\n output [3:0] io_uop_ctrl_br_type,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_ctrl_op1_sel,\t// @[issue-slot.scala:73:14]\n output [2:0] io_uop_ctrl_op2_sel,\t// @[issue-slot.scala:73:14]\n output [2:0] io_uop_ctrl_imm_sel,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_ctrl_op_fcn,\t// @[issue-slot.scala:73:14]\n output io_uop_ctrl_fcn_dw,\t// @[issue-slot.scala:73:14]\n output [2:0] io_uop_ctrl_csr_cmd,\t// @[issue-slot.scala:73:14]\n output io_uop_ctrl_is_load,\t// @[issue-slot.scala:73:14]\n output io_uop_ctrl_is_sta,\t// @[issue-slot.scala:73:14]\n output io_uop_ctrl_is_std,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_iw_state,\t// @[issue-slot.scala:73:14]\n output io_uop_iw_p1_poisoned,\t// @[issue-slot.scala:73:14]\n output io_uop_iw_p2_poisoned,\t// @[issue-slot.scala:73:14]\n output io_uop_is_br,\t// @[issue-slot.scala:73:14]\n output io_uop_is_jalr,\t// @[issue-slot.scala:73:14]\n output io_uop_is_jal,\t// @[issue-slot.scala:73:14]\n output io_uop_is_sfb,\t// @[issue-slot.scala:73:14]\n output [15:0] io_uop_br_mask,\t// @[issue-slot.scala:73:14]\n output [3:0] io_uop_br_tag,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_ftq_idx,\t// @[issue-slot.scala:73:14]\n output io_uop_edge_inst,\t// @[issue-slot.scala:73:14]\n output [5:0] io_uop_pc_lob,\t// @[issue-slot.scala:73:14]\n output io_uop_taken,\t// @[issue-slot.scala:73:14]\n output [19:0] io_uop_imm_packed,\t// @[issue-slot.scala:73:14]\n output [11:0] io_uop_csr_addr,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_rob_idx,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_ldq_idx,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_stq_idx,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_rxq_idx,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_pdst,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_prs1,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_prs2,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_prs3,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_ppred,\t// @[issue-slot.scala:73:14]\n output io_uop_prs1_busy,\t// @[issue-slot.scala:73:14]\n output io_uop_prs2_busy,\t// @[issue-slot.scala:73:14]\n output io_uop_prs3_busy,\t// @[issue-slot.scala:73:14]\n output io_uop_ppred_busy,\t// @[issue-slot.scala:73:14]\n output [6:0] io_uop_stale_pdst,\t// @[issue-slot.scala:73:14]\n output io_uop_exception,\t// @[issue-slot.scala:73:14]\n output [63:0] io_uop_exc_cause,\t// @[issue-slot.scala:73:14]\n output io_uop_bypassable,\t// @[issue-slot.scala:73:14]\n output [4:0] io_uop_mem_cmd,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_mem_size,\t// @[issue-slot.scala:73:14]\n output io_uop_mem_signed,\t// @[issue-slot.scala:73:14]\n output io_uop_is_fence,\t// @[issue-slot.scala:73:14]\n output io_uop_is_fencei,\t// @[issue-slot.scala:73:14]\n output io_uop_is_amo,\t// @[issue-slot.scala:73:14]\n output io_uop_uses_ldq,\t// @[issue-slot.scala:73:14]\n output io_uop_uses_stq,\t// @[issue-slot.scala:73:14]\n output io_uop_is_sys_pc2epc,\t// @[issue-slot.scala:73:14]\n output io_uop_is_unique,\t// @[issue-slot.scala:73:14]\n output io_uop_flush_on_commit,\t// @[issue-slot.scala:73:14]\n output io_uop_ldst_is_rs1,\t// @[issue-slot.scala:73:14]\n output [5:0] io_uop_ldst,\t// @[issue-slot.scala:73:14]\n output [5:0] io_uop_lrs1,\t// @[issue-slot.scala:73:14]\n output [5:0] io_uop_lrs2,\t// @[issue-slot.scala:73:14]\n output [5:0] io_uop_lrs3,\t// @[issue-slot.scala:73:14]\n output io_uop_ldst_val,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_dst_rtype,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_lrs1_rtype,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_lrs2_rtype,\t// @[issue-slot.scala:73:14]\n output io_uop_frs3_en,\t// @[issue-slot.scala:73:14]\n output io_uop_fp_val,\t// @[issue-slot.scala:73:14]\n output io_uop_fp_single,\t// @[issue-slot.scala:73:14]\n output io_uop_xcpt_pf_if,\t// @[issue-slot.scala:73:14]\n output io_uop_xcpt_ae_if,\t// @[issue-slot.scala:73:14]\n output io_uop_xcpt_ma_if,\t// @[issue-slot.scala:73:14]\n output io_uop_bp_debug_if,\t// @[issue-slot.scala:73:14]\n output io_uop_bp_xcpt_if,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_debug_fsrc,\t// @[issue-slot.scala:73:14]\n output [1:0] io_uop_debug_tsrc,\t// @[issue-slot.scala:73:14]\n output io_debug_p1,\t// @[issue-slot.scala:73:14]\n output io_debug_p2,\t// @[issue-slot.scala:73:14]\n output io_debug_p3,\t// @[issue-slot.scala:73:14]\n output io_debug_ppred,\t// @[issue-slot.scala:73:14]\n output [1:0] io_debug_state\t// @[issue-slot.scala:73:14]\n);\n\n wire io_grant_0 = io_grant;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[issue-slot.scala:69:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type;\t// @[issue-slot.scala:69:7]\n wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[issue-slot.scala:69:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[issue-slot.scala:69:7]\n wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[issue-slot.scala:69:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[issue-slot.scala:69:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[issue-slot.scala:69:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[issue-slot.scala:69:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[issue-slot.scala:69:7]\n wire io_kill_0 = io_kill;\t// @[issue-slot.scala:69:7]\n wire io_clear_0 = io_clear;\t// @[issue-slot.scala:69:7]\n wire io_ldspec_miss_0 = io_ldspec_miss;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_valid_0 = io_in_uop_valid;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc;\t// @[issue-slot.scala:69:7]\n wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type;\t// @[issue-slot.scala:69:7]\n wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken;\t// @[issue-slot.scala:69:7]\n wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed;\t// @[issue-slot.scala:69:7]\n wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception;\t// @[issue-slot.scala:69:7]\n wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if;\t// @[issue-slot.scala:69:7]\n wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc;\t// @[issue-slot.scala:69:7]\n wire io_pred_wakeup_port_valid = 1'h0;\t// @[issue-slot.scala:69:7]\n wire slot_uop_uop_is_rvc = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ctrl_fcn_dw = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ctrl_is_load = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ctrl_is_sta = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ctrl_is_std = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_iw_p1_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_iw_p2_poisoned = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_br = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_jalr = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_jal = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_sfb = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_edge_inst = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_taken = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_prs1_busy = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_prs2_busy = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_prs3_busy = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ppred_busy = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_exception = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_bypassable = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_mem_signed = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_fence = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_fencei = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_amo = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_uses_ldq = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_uses_stq = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_sys_pc2epc = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_is_unique = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_flush_on_commit = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ldst_is_rs1 = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_ldst_val = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_frs3_en = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_fp_val = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_fp_single = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_xcpt_pf_if = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_xcpt_ae_if = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_xcpt_ma_if = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_bp_debug_if = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_uop_bp_xcpt_if = 1'h0;\t// @[consts.scala:269:19]\n wire slot_uop_cs_fcn_dw = 1'h0;\t// @[consts.scala:279:18]\n wire slot_uop_cs_is_load = 1'h0;\t// @[consts.scala:279:18]\n wire slot_uop_cs_is_sta = 1'h0;\t// @[consts.scala:279:18]\n wire slot_uop_cs_is_std = 1'h0;\t// @[consts.scala:279:18]\n wire [4:0] io_pred_wakeup_port_bits = 5'h0;\t// @[issue-slot.scala:69:7]\n wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_uop_ftq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_uop_ldq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_uop_stq_idx = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_uop_ppred = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_uop_mem_cmd = 5'h0;\t// @[consts.scala:269:19]\n wire [4:0] slot_uop_cs_op_fcn = 5'h0;\t// @[consts.scala:279:18]\n wire [2:0] slot_uop_uop_iq_type = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0;\t// @[consts.scala:269:19]\n wire [2:0] slot_uop_cs_op2_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] slot_uop_cs_imm_sel = 3'h0;\t// @[consts.scala:279:18]\n wire [2:0] slot_uop_cs_csr_cmd = 3'h0;\t// @[consts.scala:279:18]\n wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_iw_state = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_rxq_idx = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_mem_size = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_debug_fsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_uop_debug_tsrc = 2'h0;\t// @[consts.scala:269:19]\n wire [1:0] slot_uop_cs_op1_sel = 2'h0;\t// @[consts.scala:279:18]\n wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] slot_uop_uop_br_tag = 4'h0;\t// @[consts.scala:269:19]\n wire [3:0] slot_uop_cs_br_type = 4'h0;\t// @[consts.scala:279:18]\n wire [1:0] slot_uop_uop_dst_rtype = 2'h2;\t// @[consts.scala:269:19]\n wire [5:0] slot_uop_uop_pc_lob = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] slot_uop_uop_ldst = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] slot_uop_uop_lrs1 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] slot_uop_uop_lrs2 = 6'h0;\t// @[consts.scala:269:19]\n wire [5:0] slot_uop_uop_lrs3 = 6'h0;\t// @[consts.scala:269:19]\n wire [63:0] slot_uop_uop_exc_cause = 64'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_uopc = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_rob_idx = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_prs1 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_prs2 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_prs3 = 7'h0;\t// @[consts.scala:269:19]\n wire [6:0] slot_uop_uop_stale_pdst = 7'h0;\t// @[consts.scala:269:19]\n wire [11:0] slot_uop_uop_csr_addr = 12'h0;\t// @[consts.scala:269:19]\n wire [19:0] slot_uop_uop_imm_packed = 20'h0;\t// @[consts.scala:269:19]\n wire [15:0] slot_uop_uop_br_mask = 16'h0;\t// @[consts.scala:269:19]\n wire [9:0] slot_uop_uop_fu_code = 10'h0;\t// @[consts.scala:269:19]\n wire [39:0] slot_uop_uop_debug_pc = 40'h0;\t// @[consts.scala:269:19]\n wire [31:0] slot_uop_uop_inst = 32'h0;\t// @[consts.scala:269:19]\n wire [31:0] slot_uop_uop_debug_inst = 32'h0;\t// @[consts.scala:269:19]\n wire _io_valid_T;\t// @[issue-slot.scala:79:24]\n wire _io_will_be_valid_T_4;\t// @[issue-slot.scala:262:32]\n wire _io_request_hp_T;\t// @[issue-slot.scala:243:31]\n wire [6:0] next_uopc;\t// @[issue-slot.scala:82:29]\n wire [1:0] next_state;\t// @[issue-slot.scala:81:29]\n wire [15:0] next_br_mask;\t// @[util.scala:85:25]\n wire _io_out_uop_prs1_busy_T;\t// @[issue-slot.scala:270:28]\n wire _io_out_uop_prs2_busy_T;\t// @[issue-slot.scala:271:28]\n wire _io_out_uop_prs3_busy_T;\t// @[issue-slot.scala:272:28]\n wire _io_out_uop_ppred_busy_T;\t// @[issue-slot.scala:273:28]\n wire [1:0] next_lrs1_rtype;\t// @[issue-slot.scala:83:29]\n wire [1:0] next_lrs2_rtype;\t// @[issue-slot.scala:84:29]\n wire [3:0] io_out_uop_ctrl_br_type_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_ctrl_op1_sel_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_out_uop_ctrl_op2_sel_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_out_uop_ctrl_imm_sel_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_ctrl_op_fcn_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ctrl_fcn_dw_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_out_uop_ctrl_csr_cmd_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ctrl_is_load_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ctrl_is_sta_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ctrl_is_std_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_uopc_0;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_out_uop_inst_0;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_out_uop_debug_inst_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_rvc_0;\t// @[issue-slot.scala:69:7]\n wire [39:0] io_out_uop_debug_pc_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_out_uop_iq_type_0;\t// @[issue-slot.scala:69:7]\n wire [9:0] io_out_uop_fu_code_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_iw_state_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_iw_p1_poisoned_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_iw_p2_poisoned_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_br_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_jalr_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_jal_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_sfb_0;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_out_uop_br_mask_0;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_out_uop_br_tag_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_ftq_idx_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_edge_inst_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_out_uop_pc_lob_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_taken_0;\t// @[issue-slot.scala:69:7]\n wire [19:0] io_out_uop_imm_packed_0;\t// @[issue-slot.scala:69:7]\n wire [11:0] io_out_uop_csr_addr_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_rob_idx_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_ldq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_stq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_rxq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_pdst_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_prs1_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_prs2_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_prs3_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_ppred_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_prs1_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_prs2_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_prs3_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ppred_busy_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_out_uop_stale_pdst_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_exception_0;\t// @[issue-slot.scala:69:7]\n wire [63:0] io_out_uop_exc_cause_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_bypassable_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_out_uop_mem_cmd_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_mem_size_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_mem_signed_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_fence_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_fencei_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_amo_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_uses_ldq_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_uses_stq_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_sys_pc2epc_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_is_unique_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_flush_on_commit_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ldst_is_rs1_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_out_uop_ldst_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_out_uop_lrs1_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_out_uop_lrs2_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_out_uop_lrs3_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_ldst_val_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_dst_rtype_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_lrs1_rtype_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_lrs2_rtype_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_frs3_en_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_fp_val_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_fp_single_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_xcpt_pf_if_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_xcpt_ae_if_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_xcpt_ma_if_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_bp_debug_if_0;\t// @[issue-slot.scala:69:7]\n wire io_out_uop_bp_xcpt_if_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_debug_fsrc_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_out_uop_debug_tsrc_0;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_uop_ctrl_br_type_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_ctrl_op1_sel_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_uop_ctrl_op2_sel_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_uop_ctrl_imm_sel_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_ctrl_op_fcn_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ctrl_fcn_dw_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_uop_ctrl_csr_cmd_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ctrl_is_load_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ctrl_is_sta_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ctrl_is_std_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_uopc_0;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_uop_inst_0;\t// @[issue-slot.scala:69:7]\n wire [31:0] io_uop_debug_inst_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_rvc_0;\t// @[issue-slot.scala:69:7]\n wire [39:0] io_uop_debug_pc_0;\t// @[issue-slot.scala:69:7]\n wire [2:0] io_uop_iq_type_0;\t// @[issue-slot.scala:69:7]\n wire [9:0] io_uop_fu_code_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_iw_state_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_iw_p1_poisoned_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_iw_p2_poisoned_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_br_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_jalr_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_jal_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_sfb_0;\t// @[issue-slot.scala:69:7]\n wire [15:0] io_uop_br_mask_0;\t// @[issue-slot.scala:69:7]\n wire [3:0] io_uop_br_tag_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_ftq_idx_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_edge_inst_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_uop_pc_lob_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_taken_0;\t// @[issue-slot.scala:69:7]\n wire [19:0] io_uop_imm_packed_0;\t// @[issue-slot.scala:69:7]\n wire [11:0] io_uop_csr_addr_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_rob_idx_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_ldq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_stq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_rxq_idx_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_pdst_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_prs1_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_prs2_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_prs3_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_ppred_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_prs1_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_prs2_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_prs3_busy_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ppred_busy_0;\t// @[issue-slot.scala:69:7]\n wire [6:0] io_uop_stale_pdst_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_exception_0;\t// @[issue-slot.scala:69:7]\n wire [63:0] io_uop_exc_cause_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_bypassable_0;\t// @[issue-slot.scala:69:7]\n wire [4:0] io_uop_mem_cmd_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_mem_size_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_mem_signed_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_fence_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_fencei_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_amo_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_uses_ldq_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_uses_stq_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_sys_pc2epc_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_is_unique_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_flush_on_commit_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ldst_is_rs1_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_uop_ldst_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_uop_lrs1_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_uop_lrs2_0;\t// @[issue-slot.scala:69:7]\n wire [5:0] io_uop_lrs3_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_ldst_val_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_dst_rtype_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_lrs1_rtype_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_lrs2_rtype_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_frs3_en_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_fp_val_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_fp_single_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_xcpt_pf_if_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_xcpt_ae_if_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_xcpt_ma_if_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_bp_debug_if_0;\t// @[issue-slot.scala:69:7]\n wire io_uop_bp_xcpt_if_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_debug_fsrc_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_uop_debug_tsrc_0;\t// @[issue-slot.scala:69:7]\n wire io_debug_p1_0;\t// @[issue-slot.scala:69:7]\n wire io_debug_p2_0;\t// @[issue-slot.scala:69:7]\n wire io_debug_p3_0;\t// @[issue-slot.scala:69:7]\n wire io_debug_ppred_0;\t// @[issue-slot.scala:69:7]\n wire [1:0] io_debug_state_0;\t// @[issue-slot.scala:69:7]\n wire io_valid_0;\t// @[issue-slot.scala:69:7]\n wire io_will_be_valid_0;\t// @[issue-slot.scala:69:7]\n wire io_request_0;\t// @[issue-slot.scala:69:7]\n wire io_request_hp_0;\t// @[issue-slot.scala:69:7]\n assign io_out_uop_iw_state_0 = next_state;\t// @[issue-slot.scala:69:7, :81:29]\n assign io_out_uop_uopc_0 = next_uopc;\t// @[issue-slot.scala:69:7, :82:29]\n assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype;\t// @[issue-slot.scala:69:7, :83:29]\n assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype;\t// @[issue-slot.scala:69:7, :84:29]\n reg [1:0] state;\t// @[issue-slot.scala:86:22]\n assign io_debug_state_0 = state;\t// @[issue-slot.scala:69:7, :86:22]\n reg p1;\t// @[issue-slot.scala:87:22]\n assign io_debug_p1_0 = p1;\t// @[issue-slot.scala:69:7, :87:22]\n wire next_p1 = p1;\t// @[issue-slot.scala:87:22, :163:25]\n reg p2;\t// @[issue-slot.scala:88:22]\n assign io_debug_p2_0 = p2;\t// @[issue-slot.scala:69:7, :88:22]\n wire next_p2 = p2;\t// @[issue-slot.scala:88:22, :164:25]\n reg p3;\t// @[issue-slot.scala:89:22]\n assign io_debug_p3_0 = p3;\t// @[issue-slot.scala:69:7, :89:22]\n wire next_p3 = p3;\t// @[issue-slot.scala:89:22, :165:25]\n reg ppred;\t// @[issue-slot.scala:90:22]\n assign io_debug_ppred_0 = ppred;\t// @[issue-slot.scala:69:7, :90:22]\n wire next_ppred = ppred;\t// @[issue-slot.scala:90:22, :166:28]\n reg p1_poisoned;\t// @[issue-slot.scala:95:28]\n assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned;\t// @[issue-slot.scala:69:7, :95:28]\n assign io_uop_iw_p1_poisoned_0 = p1_poisoned;\t// @[issue-slot.scala:69:7, :95:28]\n reg p2_poisoned;\t// @[issue-slot.scala:96:28]\n assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned;\t// @[issue-slot.scala:69:7, :96:28]\n assign io_uop_iw_p2_poisoned_0 = p2_poisoned;\t// @[issue-slot.scala:69:7, :96:28]\n wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned;\t// @[issue-slot.scala:69:7, :95:28, :99:29]\n wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned;\t// @[issue-slot.scala:69:7, :96:28, :100:29]\n reg [6:0] slot_uop_uopc;\t// @[issue-slot.scala:102:25]\n reg [31:0] slot_uop_inst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_inst_0 = slot_uop_inst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_inst_0 = slot_uop_inst;\t// @[issue-slot.scala:69:7, :102:25]\n reg [31:0] slot_uop_debug_inst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_debug_inst_0 = slot_uop_debug_inst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_debug_inst_0 = slot_uop_debug_inst;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_rvc;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_rvc_0 = slot_uop_is_rvc;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_rvc_0 = slot_uop_is_rvc;\t// @[issue-slot.scala:69:7, :102:25]\n reg [39:0] slot_uop_debug_pc;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_debug_pc_0 = slot_uop_debug_pc;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_debug_pc_0 = slot_uop_debug_pc;\t// @[issue-slot.scala:69:7, :102:25]\n reg [2:0] slot_uop_iq_type;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_iq_type_0 = slot_uop_iq_type;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_iq_type_0 = slot_uop_iq_type;\t// @[issue-slot.scala:69:7, :102:25]\n reg [9:0] slot_uop_fu_code;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_fu_code_0 = slot_uop_fu_code;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_fu_code_0 = slot_uop_fu_code;\t// @[issue-slot.scala:69:7, :102:25]\n reg [3:0] slot_uop_ctrl_br_type;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_ctrl_op1_sel;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel;\t// @[issue-slot.scala:69:7, :102:25]\n reg [2:0] slot_uop_ctrl_op2_sel;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel;\t// @[issue-slot.scala:69:7, :102:25]\n reg [2:0] slot_uop_ctrl_imm_sel;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_ctrl_op_fcn;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ctrl_fcn_dw;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw;\t// @[issue-slot.scala:69:7, :102:25]\n reg [2:0] slot_uop_ctrl_csr_cmd;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ctrl_is_load;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ctrl_is_sta;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ctrl_is_std;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_iw_state;\t// @[issue-slot.scala:102:25]\n assign io_uop_iw_state_0 = slot_uop_iw_state;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_iw_p1_poisoned;\t// @[issue-slot.scala:102:25]\n reg slot_uop_iw_p2_poisoned;\t// @[issue-slot.scala:102:25]\n reg slot_uop_is_br;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_br_0 = slot_uop_is_br;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_br_0 = slot_uop_is_br;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_jalr;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_jalr_0 = slot_uop_is_jalr;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_jalr_0 = slot_uop_is_jalr;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_jal;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_jal_0 = slot_uop_is_jal;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_jal_0 = slot_uop_is_jal;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_sfb;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_sfb_0 = slot_uop_is_sfb;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_sfb_0 = slot_uop_is_sfb;\t// @[issue-slot.scala:69:7, :102:25]\n reg [15:0] slot_uop_br_mask;\t// @[issue-slot.scala:102:25]\n assign io_uop_br_mask_0 = slot_uop_br_mask;\t// @[issue-slot.scala:69:7, :102:25]\n reg [3:0] slot_uop_br_tag;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_br_tag_0 = slot_uop_br_tag;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_br_tag_0 = slot_uop_br_tag;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_ftq_idx;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ftq_idx_0 = slot_uop_ftq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_edge_inst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_edge_inst_0 = slot_uop_edge_inst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_edge_inst_0 = slot_uop_edge_inst;\t// @[issue-slot.scala:69:7, :102:25]\n reg [5:0] slot_uop_pc_lob;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_pc_lob_0 = slot_uop_pc_lob;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_pc_lob_0 = slot_uop_pc_lob;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_taken;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_taken_0 = slot_uop_taken;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_taken_0 = slot_uop_taken;\t// @[issue-slot.scala:69:7, :102:25]\n reg [19:0] slot_uop_imm_packed;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_imm_packed_0 = slot_uop_imm_packed;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_imm_packed_0 = slot_uop_imm_packed;\t// @[issue-slot.scala:69:7, :102:25]\n reg [11:0] slot_uop_csr_addr;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_csr_addr_0 = slot_uop_csr_addr;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_csr_addr_0 = slot_uop_csr_addr;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_rob_idx;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_rob_idx_0 = slot_uop_rob_idx;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_rob_idx_0 = slot_uop_rob_idx;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_ldq_idx;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ldq_idx_0 = slot_uop_ldq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_stq_idx;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_stq_idx_0 = slot_uop_stq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_stq_idx_0 = slot_uop_stq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_rxq_idx;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_rxq_idx_0 = slot_uop_rxq_idx;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_pdst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_pdst_0 = slot_uop_pdst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_pdst_0 = slot_uop_pdst;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_prs1;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_prs1_0 = slot_uop_prs1;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_prs1_0 = slot_uop_prs1;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_prs2;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_prs2_0 = slot_uop_prs2;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_prs2_0 = slot_uop_prs2;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_prs3;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_prs3_0 = slot_uop_prs3;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_prs3_0 = slot_uop_prs3;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_ppred;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ppred_0 = slot_uop_ppred;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ppred_0 = slot_uop_ppred;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_prs1_busy;\t// @[issue-slot.scala:102:25]\n assign io_uop_prs1_busy_0 = slot_uop_prs1_busy;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_prs2_busy;\t// @[issue-slot.scala:102:25]\n assign io_uop_prs2_busy_0 = slot_uop_prs2_busy;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_prs3_busy;\t// @[issue-slot.scala:102:25]\n assign io_uop_prs3_busy_0 = slot_uop_prs3_busy;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ppred_busy;\t// @[issue-slot.scala:102:25]\n assign io_uop_ppred_busy_0 = slot_uop_ppred_busy;\t// @[issue-slot.scala:69:7, :102:25]\n reg [6:0] slot_uop_stale_pdst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_stale_pdst_0 = slot_uop_stale_pdst;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_exception;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_exception_0 = slot_uop_exception;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_exception_0 = slot_uop_exception;\t// @[issue-slot.scala:69:7, :102:25]\n reg [63:0] slot_uop_exc_cause;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_exc_cause_0 = slot_uop_exc_cause;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_exc_cause_0 = slot_uop_exc_cause;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_bypassable;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_bypassable_0 = slot_uop_bypassable;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_bypassable_0 = slot_uop_bypassable;\t// @[issue-slot.scala:69:7, :102:25]\n reg [4:0] slot_uop_mem_cmd;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_mem_cmd_0 = slot_uop_mem_cmd;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_mem_size;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_mem_size_0 = slot_uop_mem_size;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_mem_size_0 = slot_uop_mem_size;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_mem_signed;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_mem_signed_0 = slot_uop_mem_signed;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_mem_signed_0 = slot_uop_mem_signed;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_fence;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_fence_0 = slot_uop_is_fence;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_fence_0 = slot_uop_is_fence;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_fencei;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_fencei_0 = slot_uop_is_fencei;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_fencei_0 = slot_uop_is_fencei;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_amo;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_amo_0 = slot_uop_is_amo;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_amo_0 = slot_uop_is_amo;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_uses_ldq;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_uses_ldq_0 = slot_uop_uses_ldq;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_uses_stq;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_uses_stq_0 = slot_uop_uses_stq;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_uses_stq_0 = slot_uop_uses_stq;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_is_unique;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_is_unique_0 = slot_uop_is_unique;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_is_unique_0 = slot_uop_is_unique;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_flush_on_commit;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:69:7, :102:25]\n reg [5:0] slot_uop_ldst;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ldst_0 = slot_uop_ldst;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ldst_0 = slot_uop_ldst;\t// @[issue-slot.scala:69:7, :102:25]\n reg [5:0] slot_uop_lrs1;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_lrs1_0 = slot_uop_lrs1;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_lrs1_0 = slot_uop_lrs1;\t// @[issue-slot.scala:69:7, :102:25]\n reg [5:0] slot_uop_lrs2;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_lrs2_0 = slot_uop_lrs2;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_lrs2_0 = slot_uop_lrs2;\t// @[issue-slot.scala:69:7, :102:25]\n reg [5:0] slot_uop_lrs3;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_lrs3_0 = slot_uop_lrs3;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_lrs3_0 = slot_uop_lrs3;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_ldst_val;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_ldst_val_0 = slot_uop_ldst_val;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_ldst_val_0 = slot_uop_ldst_val;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_dst_rtype;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_dst_rtype_0 = slot_uop_dst_rtype;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_lrs1_rtype;\t// @[issue-slot.scala:102:25]\n reg [1:0] slot_uop_lrs2_rtype;\t// @[issue-slot.scala:102:25]\n reg slot_uop_frs3_en;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_frs3_en_0 = slot_uop_frs3_en;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_frs3_en_0 = slot_uop_frs3_en;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_fp_val;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_fp_val_0 = slot_uop_fp_val;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_fp_val_0 = slot_uop_fp_val;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_fp_single;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_fp_single_0 = slot_uop_fp_single;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_fp_single_0 = slot_uop_fp_single;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_bp_debug_if;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if;\t// @[issue-slot.scala:69:7, :102:25]\n reg slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_debug_fsrc;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc;\t// @[issue-slot.scala:69:7, :102:25]\n reg [1:0] slot_uop_debug_tsrc;\t// @[issue-slot.scala:102:25]\n assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc;\t// @[issue-slot.scala:69:7, :102:25]\n assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc;\t// @[issue-slot.scala:69:7, :102:25]\n wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc;\t// @[issue-slot.scala:69:7, :102:25, :103:21]\n wire _T_11 = state == 2'h2;\t// @[issue-slot.scala:86:22, :134:25]\n wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred;\t// @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]\n wire _T_12 = io_grant_0 & _T_11;\t// @[issue-slot.scala:69:7, :134:25, :139:25]\n wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned);\t// @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]\n wire _GEN = _T_12 & ~_T_14;\t// @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]\n wire _GEN_0 = io_kill_0 | _T_7;\t// @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]\n wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1);\t// @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]\n assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3;\t// @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]\n assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2;\t// @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]\n wire _GEN_2 = _GEN_0 | ~_GEN | p1;\t// @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]\n assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2;\t// @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]\n wire _p1_T = ~io_in_uop_bits_prs1_busy_0;\t// @[issue-slot.scala:69:7, :169:11]\n wire _p2_T = ~io_in_uop_bits_prs2_busy_0;\t// @[issue-slot.scala:69:7, :170:11]\n wire _p3_T = ~io_in_uop_bits_prs3_busy_0;\t// @[issue-slot.scala:69:7, :171:11]\n wire _ppred_T = ~io_in_uop_bits_ppred_busy_0;\t// @[issue-slot.scala:69:7, :172:14]\n wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned;\t// @[issue-slot.scala:69:7, :99:29, :175:24]\n wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned;\t// @[issue-slot.scala:69:7, :100:29, :179:24]\n wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0;\t// @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]\n wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0;\t// @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":50,"numItemsPerPage":100,"numTotalItems":35529,"offset":5000,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc1MjcyNjkxNCwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NTI3MzA1MTQsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.Bldr7F5ViXaSzSPnCANNJMWtZOfAZtul5PvusvXUYH5Q3iZPXbCKLxY6objiVeGkjKAnOhjgsqm4GU8Eh9zCAA","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i32_e8_s24_10( // @[INToRecFN.scala:43:7]
input [31:0] io_in, // @[INToRecFN.scala:46:16]
output [32:0] io_out // @[INToRecFN.scala:46:16]
);
wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [32:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31]
wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70]
wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_10 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_4( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_393( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_21( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_21 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File HasTiles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
import freechips.rocketchip.tilelink.TLWidthWidget
import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
import freechips.rocketchip.rocket.TracedInstruction
import freechips.rocketchip.util.TraceCoreInterface
import scala.collection.immutable.SortedMap
/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
/** List of HierarchicalLocations which might contain a Tile */
case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil)
/** For determining static tile id */
case object NumTiles extends Field[Int](0)
/** Whether to add timing-closure registers along the path of the hart id
* as it propagates through the subsystem and into the tile.
*
* These are typically only desirable when a dynamically programmable prefix is being combined
* with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]].
*/
case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false)
/** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block,
* and if so, what their width should be.
*/
case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None)
/** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block.
*
* Unlike the hart ids, the reset vector width is determined by the sinks within the tiles,
* based on the size of the address map visible to the tiles.
*/
case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
/** These are sources of "constants" that are driven into the tile.
*
* While they are not expected to change dyanmically while the tile is executing code,
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
* Each "prefix" input is actually the same full width as the outer hart id; the expected usage
* is that each prefix source would set only some non-overlapping portion of the bits to non-zero values.
* This node orReduces them, and further combines the reduction with the static ids assigned to each tile,
* producing a unique, dynamic hart id for each tile.
*
* If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered.
*
* The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into
* the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous.
*/
val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i =>
val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup
if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y
},
default = Some(() => 0.U(p(MaxHartIdBits).W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs
/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below
)
/** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids.
*
* Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile.
*/
val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match {
case Some(w) => (0 until nTotalTiles).map { i =>
val hartIdSource = BundleBridgeSource(() => UInt(w.W))
tileHartIdNodes(i) := hartIdSource
hartIdSource
}
case None => {
(0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode }
Nil
}
}
/** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors.
*
* Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile.
*/
val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match {
case true => (0 until nTotalTiles).map { i =>
val resetVectorSource = BundleBridgeSource[UInt]()
tileResetVectorNodes(i) := resetVectorSource
resetVectorSource
}
case false => {
(0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode }
Nil
}
}
}
/** These are sinks of notifications that are driven out from the tile.
*
* They need to be instantiated before tiles are attached to the subsystem containing them.
*/
trait HasTileNotificationSinks { this: LazyModule =>
val tileHaltXbarNode = IntXbar()
val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
tileHaltSinkNode := tileHaltXbarNode
val tileWFIXbarNode = IntXbar()
val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
tileWFISinkNode := tileWFIXbarNode
val tileCeaseXbarNode = IntXbar()
val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
tileCeaseSinkNode := tileCeaseXbarNode
}
/** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
*
* Sub-classes of this trait can optionally override the individual connect functions in order to specialize
* their attachment behaviors, but most use cases should be be handled simply by changing the implementation
* of the injectNode functions in crossingParams.
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: HierarchicalElementCrossingParamsLike
/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
})
tile_prci_domain
}
/** A default set of connections that need to occur for most tile types */
def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC(domain, context)
connectOutputNotifications(domain, context)
connectInputConstants(domain, context)
connectTrace(domain, context)
}
/** Connect the port where the tile is the master to a TileLink interconnect. */
def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
dataBus.coupleFrom(tileParams.baseName) { bus =>
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
}
}
/** Connect the port where the tile is the slave to a TileLink interconnect. */
def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
DisableMonitors { implicit p =>
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
controlBus.coupleTo(tileParams.baseName) { bus =>
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
}
}
}
/** Connect the various interrupts sent to and and raised by the tile. */
def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from tile.intInwardNode inside the tile. For this reason,
// we stub out missing interrupts with constant sources here.
// 1. Debug interrupt is definitely asynchronous in all cases.
domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } :=
context.debugNodes(domain.element.tileId)
// 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively,
// so might need to be synchronized depending on the Tile's crossing type.
// From CLINT: "msip" and "mtip"
context.msipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.msipNodes(domain.element.tileId)
}
// From PLIC: "meip"
context.meipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.meipNodes(domain.element.tileId)
}
// From PLIC: "seip" (only if supervisor mode is enabled)
if (domain.element.tileParams.core.hasSupervisorMode) {
context.seipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.seipNodes(domain.element.tileId)
}
}
// 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
// (they are connected to domain.element.intInwardNode in a seperate trait)
// 4. Interrupts coming out of the tile are sent to the PLIC,
// so might need to be synchronized depending on the Tile's crossing type.
context.tileToPlicNodes.get(domain.element.tileId).foreach { node =>
FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out =>
context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) }
}}
}
// 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock.
domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId))
}
/** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */
def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
domain {
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode)
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode)
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode)
}
// TODO should context be forced to have a trace sink connected here?
// for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally
}
/** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */
def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId)
domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId)
tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ }
}
/** Connect power/reset/clock resources. */
def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
(crossingParams.crossingType match {
case _: SynchronousCrossing | _: CreditedCrossing =>
if (crossingParams.forceSeparateClockReset) {
domain.clockNode := tlBusToGetClockDriverFrom.clockNode
} else {
domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
}
case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
case _: AsynchronousCrossing => {
val tileClockGroup = ClockGroup()
tileClockGroup := context.allClockGroupsNode
domain.clockNode := tileClockGroup
}
})
domain {
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
}
}
/** Function to handle all trace crossings when tile is instantiated inside domains */
def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle](
resetCrossingType = crossingParams.resetCrossingType)
context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode
val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface](
resetCrossingType = crossingParams.resetCrossingType)
context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode
}
}
case class CloneTileAttachParams(
sourceTileId: Int,
cloneParams: CanAttachTile
) extends CanAttachTile {
type TileType = cloneParams.TileType
type TileContextType = cloneParams.TileContextType
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
},
instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]]
)
tile_prci_domain
}
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TilePRCIDomain( // @[ClockDomain.scala:14:9]
output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_tl_master_clock_xing_out_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [63:0] auto_tl_master_clock_xing_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17]
assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17]
assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
RocketTile element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),
.auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),
.auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),
.auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),
.auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),
.auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),
.auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),
.auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d64s2k3z4c_1 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),
.auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),
.auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),
.auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),
.auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),
.auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),
.auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),
.auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),
.auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),
.auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),
.auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),
.auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),
.auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),
.auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),
.auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),
.auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),
.auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),
.auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),
.auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),
.auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),
.auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),
.auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_b_ready (tlMasterClockXingIn_b_ready),
.auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlMasterClockXingIn_c_valid),
.auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),
.auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),
.auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),
.auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),
.auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),
.auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),
.auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),
.auto_out_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlMasterClockXingIn_e_valid),
.auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)
); // @[Buffer.scala:75:28]
TLBuffer_2 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_1 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_2 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_3 intsink_5 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_1_0_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9]
.auto_out_sync_0 (intOutClockXingIn_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_4 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_2 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_65( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_103( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputBuffer_23( // @[InputUnit.scala:49:7]
input clock, // @[InputUnit.scala:49:7]
input reset, // @[InputUnit.scala:49:7]
input io_enq_0_valid, // @[InputUnit.scala:51:14]
input io_enq_0_bits_head, // @[InputUnit.scala:51:14]
input io_enq_0_bits_tail, // @[InputUnit.scala:51:14]
input [36:0] io_enq_0_bits_payload, // @[InputUnit.scala:51:14]
input [1:0] io_enq_0_bits_virt_channel_id, // @[InputUnit.scala:51:14]
input io_deq_0_ready, // @[InputUnit.scala:51:14]
output io_deq_0_valid, // @[InputUnit.scala:51:14]
output io_deq_0_bits_head, // @[InputUnit.scala:51:14]
output io_deq_0_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_0_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_1_ready, // @[InputUnit.scala:51:14]
output io_deq_1_valid, // @[InputUnit.scala:51:14]
output io_deq_1_bits_head, // @[InputUnit.scala:51:14]
output io_deq_1_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_1_bits_payload, // @[InputUnit.scala:51:14]
output io_deq_2_bits_head, // @[InputUnit.scala:51:14]
output io_deq_2_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_2_bits_payload, // @[InputUnit.scala:51:14]
input io_deq_3_ready, // @[InputUnit.scala:51:14]
output io_deq_3_valid, // @[InputUnit.scala:51:14]
output io_deq_3_bits_head, // @[InputUnit.scala:51:14]
output io_deq_3_bits_tail, // @[InputUnit.scala:51:14]
output [36:0] io_deq_3_bits_payload // @[InputUnit.scala:51:14]
);
wire _qs_3_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_2_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_1_io_enq_ready; // @[InputUnit.scala:90:49]
wire _qs_0_io_enq_ready; // @[InputUnit.scala:90:49]
wire [38:0] _mem_ext_R0_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R1_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R2_data; // @[InputUnit.scala:85:18]
wire [38:0] _mem_ext_R3_data; // @[InputUnit.scala:85:18]
reg [1:0] heads_0; // @[InputUnit.scala:86:24]
reg [1:0] heads_1; // @[InputUnit.scala:86:24]
reg [1:0] heads_2; // @[InputUnit.scala:86:24]
reg [1:0] heads_3; // @[InputUnit.scala:86:24]
reg [1:0] tails_0; // @[InputUnit.scala:87:24]
reg [1:0] tails_1; // @[InputUnit.scala:87:24]
reg [1:0] tails_2; // @[InputUnit.scala:87:24]
reg [1:0] tails_3; // @[InputUnit.scala:87:24]
wire _tails_T_12 = io_enq_0_bits_virt_channel_id == 2'h0; // @[Mux.scala:32:36]
wire _tails_T_21 = io_enq_0_bits_virt_channel_id == 2'h1; // @[Mux.scala:32:36]
wire _tails_T_14 = io_enq_0_bits_virt_channel_id == 2'h2; // @[Mux.scala:32:36]
wire direct_to_q = (_tails_T_12 & _qs_0_io_enq_ready | _tails_T_21 & _qs_1_io_enq_ready | _tails_T_14 & _qs_2_io_enq_ready | (&io_enq_0_bits_virt_channel_id) & _qs_3_io_enq_ready) & (_tails_T_12 & heads_0 == tails_0 | _tails_T_21 & heads_1 == tails_1 | _tails_T_14 & heads_2 == tails_2 | (&io_enq_0_bits_virt_channel_id) & heads_3 == tails_3); // @[Mux.scala:30:73, :32:36]
wire mem_MPORT_en = io_enq_0_valid & ~direct_to_q; // @[InputUnit.scala:96:62, :100:{27,30}]
wire [3:0][1:0] _GEN = {{tails_3}, {tails_2}, {tails_1}, {tails_0}}; // @[InputUnit.scala:87:24, :102:16]
wire _GEN_0 = io_enq_0_bits_virt_channel_id == 2'h0; // @[InputUnit.scala:103:45]
wire _GEN_1 = io_enq_0_bits_virt_channel_id == 2'h1; // @[InputUnit.scala:103:45]
wire _GEN_2 = io_enq_0_bits_virt_channel_id == 2'h2; // @[InputUnit.scala:103:45]
wire _GEN_3 = io_enq_0_valid & direct_to_q; // @[InputUnit.scala:96:62, :107:34]
wire can_to_q_0 = heads_0 != tails_0 & _qs_0_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_1 = heads_1 != tails_1 & _qs_1_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_2 = heads_2 != tails_2 & _qs_2_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire can_to_q_3 = heads_3 != tails_3 & _qs_3_io_enq_ready; // @[InputUnit.scala:86:24, :87:24, :88:49, :90:49, :117:{60,70}]
wire [3:0] to_q_oh_enc = can_to_q_0 ? 4'h1 : can_to_q_1 ? 4'h2 : can_to_q_2 ? 4'h4 : {can_to_q_3, 3'h0}; // @[OneHot.scala:58:35]
wire _GEN_4 = can_to_q_0 | can_to_q_1 | can_to_q_2 | can_to_q_3; // @[package.scala:81:59]
wire [1:0] head = (to_q_oh_enc[0] ? heads_0 : 2'h0) | (to_q_oh_enc[1] ? heads_1 : 2'h0) | (to_q_oh_enc[2] ? heads_2 : 2'h0) | (to_q_oh_enc[3] ? heads_3 : 2'h0); // @[OneHot.scala:83:30]
wire _GEN_5 = _GEN_4 & to_q_oh_enc[0]; // @[OneHot.scala:83:30]
wire _GEN_6 = _GEN_4 & to_q_oh_enc[1]; // @[OneHot.scala:83:30]
wire _GEN_7 = _GEN_4 & to_q_oh_enc[2]; // @[OneHot.scala:83:30]
wire _GEN_8 = _GEN_4 & to_q_oh_enc[3]; // @[OneHot.scala:83:30]
wire [1:0] _tails_T_25 = _GEN[io_enq_0_bits_virt_channel_id] == {&io_enq_0_bits_virt_channel_id, _tails_T_21} ? {&io_enq_0_bits_virt_channel_id, _tails_T_21} : _GEN[io_enq_0_bits_virt_channel_id] + 2'h1; // @[Mux.scala:30:73, :32:36]
wire _to_q_T_2 = to_q_oh_enc[3] | to_q_oh_enc[1]; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] to_q = {|(to_q_oh_enc[3:2]), _to_q_T_2}; // @[OneHot.scala:30:18, :32:{10,14,28}]
wire [1:0] _heads_T_17 = head == {to_q_oh_enc[3], to_q_oh_enc[1]} ? {to_q_oh_enc[3], to_q_oh_enc[1]} : head + 2'h1; // @[OneHot.scala:83:30]
always @(posedge clock) begin // @[InputUnit.scala:49:7]
if (reset) begin // @[InputUnit.scala:49:7]
heads_0 <= 2'h0; // @[InputUnit.scala:86:24]
heads_1 <= 2'h1; // @[InputUnit.scala:86:24]
heads_2 <= 2'h0; // @[InputUnit.scala:86:24]
heads_3 <= 2'h2; // @[InputUnit.scala:86:24]
tails_0 <= 2'h0; // @[InputUnit.scala:87:24]
tails_1 <= 2'h1; // @[InputUnit.scala:87:24]
tails_2 <= 2'h0; // @[InputUnit.scala:87:24]
tails_3 <= 2'h2; // @[InputUnit.scala:87:24]
end
else begin // @[InputUnit.scala:49:7]
if (_GEN_4 & {to_q_oh_enc[3:2], _to_q_T_2} == 3'h0) // @[OneHot.scala:30:18, :32:{10,14,28}]
heads_0 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & to_q == 2'h1) // @[OneHot.scala:32:10]
heads_1 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & to_q == 2'h2) // @[OneHot.scala:32:10]
heads_2 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (_GEN_4 & (&to_q)) // @[OneHot.scala:32:10]
heads_3 <= _heads_T_17; // @[InputUnit.scala:86:24, :122:27]
if (mem_MPORT_en & _GEN_0) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_0 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_1) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_1 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & _GEN_2) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_2 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
if (mem_MPORT_en & (&io_enq_0_bits_virt_channel_id)) // @[InputUnit.scala:87:24, :100:{27,44}, :103:45]
tails_3 <= _tails_T_25; // @[InputUnit.scala:87:24, :103:51]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_452( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_196 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_51( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [159:0] inflight; // @[Monitor.scala:614:27]
reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [639:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [255:0] _GEN = {248'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [255:0] _GEN_2 = {248'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [159:0] inflight_1; // @[Monitor.scala:726:35]
reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File tage.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module TageTable( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [43:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [6:0] reset_idx; // @[tage.scala:73:26]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26]
wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [36:0] _idx_T = {io_f1_req_pc_0[39:5], io_f1_req_pc_0[4:3] ^ idx_history}; // @[frontend.scala:162:35]
wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}]
wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35]
wire [29:0] _tag_T_1 = {_tag_T[29:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}]
wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87]
reg [6:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [18:0] clear_u_ctr; // @[tage.scala:109:28]
wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85]
wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33]
wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [36:0] _idx_T_1 = {io_update_pc_0[39:5], io_update_pc_0[4:3] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}]
wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35]
wire [29:0] _tag_T_3 = {_tag_T_2[29:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}]
wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 7'h0; // @[tage.scala:73:26]
clear_u_ctr <= 19'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_0 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module TLXbar_fbus_i2_o1_a32d64s5k3z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [4:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_0_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_0_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestEIO_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _requestEIO_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _requestEIO_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _requestEIO_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsEI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _beatsEI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] _beatsEI_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _beatsEI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] portsAOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsEOI_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _portsEOI_WIRE_1_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsEOI_WIRE_2_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _portsEOI_WIRE_3_bits_sink = 3'h0; // @[Bundles.scala:267:61]
wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire auto_anon_in_0_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [4:0] _addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _addressC_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _addressC_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] _beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _beatsCI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _beatsCI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] portsBIO_filtered_1_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] _portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] _portsCOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _portsCOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] portsCOI_filtered_1_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [4:0] in_0_a_bits_source = 5'h10; // @[Xbar.scala:159:18]
wire [4:0] _in_0_a_bits_source_T = 5'h10; // @[Xbar.scala:166:55]
wire [4:0] portsAOI_filtered_0_bits_source = 5'h10; // @[Xbar.scala:352:24]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [3:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [4:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [4:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [4:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [4:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [4:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [4:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_1_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [4:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire requestDOI_0_0 = out_0_d_bits_source == 5'h10; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [3:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[4]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLAToNoC_1( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
us.suggestName(s"tage_u_${histLength}")
table.suggestName(s"tage_table_${histLength}")
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))
val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f2_resp(w).valid := s2_req_rhits(w)
io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))
io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))
val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)
when (RegNext(wen) && singlePorted.B) {
s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))
} .otherwise {
s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))
}
when (wen) {
val widx = Mux(doing_reset, reset_idx, update_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))
val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)
table.write(widx, wdata, wmask.asBools)
}
val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})
val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))
val u_rdata = if (singlePorted) {
us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)
} else {
us.read(s1_hashed_idx, io.f1_req_valid)
}
s2_req_rus := u_rdata
when (update_u_wen) {
val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))
val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))
val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))
us.write(widx, wdata, wmask.asBools)
}
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048,
singlePorted: Boolean = false
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f2_resps = VecInit(tables.map(_.io.f2_resp))
val f3_resps = RegNext(f2_resps)
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var s2_provided = false.B
var s2_provider = 0.U
var s2_alt_provided = false.B
var s2_alt_provider = 0.U
for (i <- 0 until tageNTables) {
val hit = f2_resps(i)(w).valid
s2_alt_provided = s2_alt_provided || (s2_provided && hit)
s2_provided = s2_provided || hit
s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)
s2_provider = Mux(hit, i.U, s2_provider)
}
val s3_provided = RegNext(s2_provided)
val s3_provider = RegNext(s2_provider)
val s3_alt_provided = RegNext(s2_alt_provided)
val s3_alt_provider = RegNext(s2_alt_provider)
val prov = RegNext(f2_resps(s2_provider)(w).bits)
val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)
io.resp.f3(w).taken := Mux(s3_provided,
Mux(prov.ctr === 3.U || prov.ctr === 4.U,
Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),
prov.ctr(2)),
io.resp_in(0).f3(w).taken
)
f3_meta.provider(w).valid := s3_provided
f3_meta.provider(w).bits := s3_provider
f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := prov.u
f3_meta.provider_ctr(w) := prov.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module tage_u_16( // @[tage.scala:89:27]
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [7:0] R0_data,
input [7:0] W0_addr,
input W0_en,
input W0_clk,
input [7:0] W0_data,
input [7:0] W0_mask
);
tage_u_8_ext tage_u_8_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:89:27]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLFragmenter_TileResetSetter( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready // @[LazyModuleImp.scala:107:25]
);
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [20:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9]
wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_opcode = 3'h0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_size = 3'h0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_d_bits_opcode = 3'h0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_d_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] anonOut_d_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] dFragnum = 3'h0; // @[Fragmenter.scala:204:41]
wire [2:0] dsizeOH1 = 3'h0; // @[package.scala:243:46]
wire [2:0] acknum_fragment = 3'h0; // @[Fragmenter.scala:212:40]
wire [2:0] dFirst_acknum = 3'h0; // @[Fragmenter.scala:215:45]
wire [2:0] dFirst_size_hi = 3'h0; // @[OneHot.scala:30:18]
wire [2:0] dFirst_size = 3'h0; // @[OneHot.scala:32:10]
wire [2:0] _acknum_T_1 = 3'h0; // @[Fragmenter.scala:221:55]
wire [2:0] _acknum_T_2 = 3'h0; // @[Fragmenter.scala:221:24]
wire [2:0] _anonIn_d_bits_size_T = 3'h0; // @[Fragmenter.scala:239:32]
wire dFirst = 1'h1; // @[Fragmenter.scala:205:29]
wire dLast = 1'h1; // @[Fragmenter.scala:206:30]
wire _drop_T = 1'h1; // @[Fragmenter.scala:234:20]
wire _drop_T_1 = 1'h1; // @[Fragmenter.scala:234:37]
wire _anonIn_d_valid_T = 1'h1; // @[Fragmenter.scala:236:39]
wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire find_0 = 1'h1; // @[Parameters.scala:616:12]
wire aFirst = 1'h1; // @[Fragmenter.scala:304:29]
wire aToggle = 1'h1; // @[Fragmenter.scala:309:23]
wire auto_anon_in_a_ready = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_valid = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_ready = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_valid = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire anonIn_a_ready = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_valid = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dHasData = 1'h0; // @[Edges.scala:106:36]
wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36]
wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50]
wire _ack_decrement_T = 1'h0; // @[Fragmenter.scala:216:56]
wire ack_decrement = 1'h0; // @[Fragmenter.scala:216:32]
wire _dFirst_size_T_7 = 1'h0; // @[OneHot.scala:32:14]
wire _dFirst_size_T_9 = 1'h0; // @[OneHot.scala:32:14]
wire _dFirst_size_T_11 = 1'h0; // @[CircuitMath.scala:28:8]
wire _dToggle_T = 1'h0; // @[Fragmenter.scala:224:41]
wire _drop_T_2 = 1'h0; // @[Fragmenter.scala:234:33]
wire drop = 1'h0; // @[Fragmenter.scala:234:30]
wire _anonIn_d_valid_T_1 = 1'h0; // @[Fragmenter.scala:236:36]
wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50]
wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84]
wire _aToggle_T = 1'h0; // @[Fragmenter.scala:309:27]
wire [2:0] _dsizeOH1_T_1 = 3'h7; // @[package.scala:243:76]
wire [2:0] _old_gennum1_T_2 = 3'h7; // @[Fragmenter.scala:305:79]
wire [3:0] _old_gennum1_T_1 = 4'hF; // @[Fragmenter.scala:305:79]
wire [3:0] _acknum_T = 4'h0; // @[Fragmenter.scala:221:55]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_size = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_d_bits_size = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] dsizeOH_shiftAmount = 2'h0; // @[OneHot.scala:64:49]
wire [1:0] dFirst_size_hi_1 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] _dFirst_size_T_12 = 2'h0; // @[OneHot.scala:32:10]
wire [6:0] auto_anon_in_d_bits_source = 7'h0; // @[Fragmenter.scala:92:9]
wire [6:0] anonIn_d_bits_source = 7'h0; // @[MixedNode.scala:551:17]
wire [6:0] _dFirst_size_T_2 = 7'h0; // @[package.scala:241:35]
wire [6:0] _dFirst_size_T_4 = 7'h0; // @[package.scala:241:53]
wire [6:0] _anonIn_d_bits_source_T = 7'h0; // @[Fragmenter.scala:238:47]
wire [63:0] auto_anon_in_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_d_bits_data = 64'h0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] anonOut_d_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [10:0] auto_anon_out_d_bits_source = 11'h0; // @[Fragmenter.scala:92:9]
wire [10:0] anonOut_d_bits_source = 11'h0; // @[MixedNode.scala:542:17]
wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49]
wire [21:0] _find_T_2 = 22'h0; // @[Parameters.scala:137:46]
wire [21:0] _find_T_3 = 22'h0; // @[Parameters.scala:137:46]
wire [1:0] dFirst_size_lo_1 = 2'h1; // @[OneHot.scala:31:18]
wire [1:0] _dFirst_size_T_10 = 2'h1; // @[OneHot.scala:32:28]
wire [3:0] _dsizeOH_T = 4'h1; // @[OneHot.scala:65:12]
wire [3:0] dsizeOH = 4'h1; // @[OneHot.scala:65:27]
wire [3:0] dFirst_size_lo = 4'h1; // @[OneHot.scala:31:18]
wire [3:0] _dFirst_size_T_8 = 4'h1; // @[OneHot.scala:32:28]
wire [6:0] _dFirst_size_T_3 = 7'h1; // @[package.scala:241:40]
wire [6:0] _dFirst_size_T_6 = 7'h1; // @[package.scala:241:47]
wire [6:0] _dFirst_size_T_5 = 7'h7F; // @[package.scala:241:49]
wire [5:0] _dFirst_size_T = 6'h0; // @[Fragmenter.scala:218:47]
wire [5:0] _dFirst_size_T_1 = 6'h0; // @[Fragmenter.scala:218:69]
wire [5:0] _dsizeOH1_T = 6'h7; // @[package.scala:243:71]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [10:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [10:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [20:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
wire [7:0] _anonOut_a_bits_mask_T = anonIn_a_bits_mask; // @[Fragmenter.scala:325:31]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _anonOut_d_ready_T = anonIn_d_ready; // @[Fragmenter.scala:235:35]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9]
wire [10:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9]
wire [20:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9]
assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
wire [20:0] _find_T; // @[Parameters.scala:137:31]
wire [21:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}]
wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49]
wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31]
wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}]
wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71]
wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}]
wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30]
wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46]
wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46]
wire [2:0] old_gennum1 = _old_gennum1_T; // @[Fragmenter.scala:305:{30,48}]
wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40]
wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28]
wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}]
wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}]
wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}]
wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}]
wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}]
wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30]
wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31]
wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53]
wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}]
wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65]
wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}]
wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}]
wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}]
assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[20:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}]
assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
wire [7:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, 1'h1}; // @[Fragmenter.scala:274:30, :317:33]
assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33]
assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31]
TLMonitor_91 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a21d64s7k1z3u_1 repeater ( // @[Fragmenter.scala:274:30]
.clock (clock),
.reset (reset),
.io_repeat (_repeater_io_repeat_T_2), // @[Fragmenter.scala:314:41]
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_valid (anonOut_a_valid),
.io_deq_bits_opcode (_repeater_io_deq_bits_opcode),
.io_deq_bits_param (anonOut_a_bits_param),
.io_deq_bits_size (_repeater_io_deq_bits_size),
.io_deq_bits_source (_repeater_io_deq_bits_source),
.io_deq_bits_address (_repeater_io_deq_bits_address),
.io_deq_bits_corrupt (anonOut_a_bits_corrupt)
); // @[Fragmenter.scala:274:30]
assign anonOut_a_bits_opcode = _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
assign _find_T = _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module NoC( // @[NoC.scala:141:9]
input clock, // @[NoC.scala:141:9]
input reset, // @[NoC.scala:141:9]
output io_ingress_54_flit_ready, // @[NoC.scala:143:16]
input io_ingress_54_flit_valid, // @[NoC.scala:143:16]
input io_ingress_54_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_54_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_54_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_54_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_53_flit_ready, // @[NoC.scala:143:16]
input io_ingress_53_flit_valid, // @[NoC.scala:143:16]
input io_ingress_53_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_53_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_53_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_53_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_52_flit_ready, // @[NoC.scala:143:16]
input io_ingress_52_flit_valid, // @[NoC.scala:143:16]
input io_ingress_52_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_52_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_52_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_52_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_51_flit_ready, // @[NoC.scala:143:16]
input io_ingress_51_flit_valid, // @[NoC.scala:143:16]
input io_ingress_51_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_51_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_51_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_51_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_50_flit_ready, // @[NoC.scala:143:16]
input io_ingress_50_flit_valid, // @[NoC.scala:143:16]
input io_ingress_50_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_50_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_50_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_50_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_49_flit_ready, // @[NoC.scala:143:16]
input io_ingress_49_flit_valid, // @[NoC.scala:143:16]
input io_ingress_49_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_49_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_49_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_49_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_48_flit_ready, // @[NoC.scala:143:16]
input io_ingress_48_flit_valid, // @[NoC.scala:143:16]
input io_ingress_48_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_48_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_48_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_48_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_47_flit_ready, // @[NoC.scala:143:16]
input io_ingress_47_flit_valid, // @[NoC.scala:143:16]
input io_ingress_47_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_47_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_47_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_47_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_46_flit_ready, // @[NoC.scala:143:16]
input io_ingress_46_flit_valid, // @[NoC.scala:143:16]
input io_ingress_46_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_46_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_46_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_46_flit_bits_egress_id, // @[NoC.scala:143:16]
input io_ingress_45_flit_valid, // @[NoC.scala:143:16]
output io_ingress_44_flit_ready, // @[NoC.scala:143:16]
input io_ingress_44_flit_valid, // @[NoC.scala:143:16]
input io_ingress_44_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_44_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_44_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_43_flit_ready, // @[NoC.scala:143:16]
input io_ingress_43_flit_valid, // @[NoC.scala:143:16]
input io_ingress_43_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_43_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_43_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_43_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_42_flit_ready, // @[NoC.scala:143:16]
input io_ingress_42_flit_valid, // @[NoC.scala:143:16]
input io_ingress_42_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_42_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_42_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_42_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_41_flit_ready, // @[NoC.scala:143:16]
input io_ingress_41_flit_valid, // @[NoC.scala:143:16]
input io_ingress_41_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_41_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_41_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_40_flit_ready, // @[NoC.scala:143:16]
input io_ingress_40_flit_valid, // @[NoC.scala:143:16]
input io_ingress_40_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_40_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_40_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_40_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_39_flit_ready, // @[NoC.scala:143:16]
input io_ingress_39_flit_valid, // @[NoC.scala:143:16]
input io_ingress_39_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_39_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_39_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_39_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_38_flit_ready, // @[NoC.scala:143:16]
input io_ingress_38_flit_valid, // @[NoC.scala:143:16]
input io_ingress_38_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_38_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_38_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_37_flit_ready, // @[NoC.scala:143:16]
input io_ingress_37_flit_valid, // @[NoC.scala:143:16]
input io_ingress_37_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_37_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_37_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_37_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_36_flit_ready, // @[NoC.scala:143:16]
input io_ingress_36_flit_valid, // @[NoC.scala:143:16]
input io_ingress_36_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_36_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_36_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_36_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_35_flit_ready, // @[NoC.scala:143:16]
input io_ingress_35_flit_valid, // @[NoC.scala:143:16]
input io_ingress_35_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_35_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_35_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_34_flit_ready, // @[NoC.scala:143:16]
input io_ingress_34_flit_valid, // @[NoC.scala:143:16]
input io_ingress_34_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_34_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_34_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_34_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_33_flit_ready, // @[NoC.scala:143:16]
input io_ingress_33_flit_valid, // @[NoC.scala:143:16]
input io_ingress_33_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_33_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_33_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_33_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_32_flit_ready, // @[NoC.scala:143:16]
input io_ingress_32_flit_valid, // @[NoC.scala:143:16]
input io_ingress_32_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_32_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_32_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_31_flit_ready, // @[NoC.scala:143:16]
input io_ingress_31_flit_valid, // @[NoC.scala:143:16]
input io_ingress_31_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_31_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_31_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_31_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_30_flit_ready, // @[NoC.scala:143:16]
input io_ingress_30_flit_valid, // @[NoC.scala:143:16]
input io_ingress_30_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_30_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_30_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_30_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_29_flit_ready, // @[NoC.scala:143:16]
input io_ingress_29_flit_valid, // @[NoC.scala:143:16]
input io_ingress_29_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_29_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_29_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_28_flit_ready, // @[NoC.scala:143:16]
input io_ingress_28_flit_valid, // @[NoC.scala:143:16]
input io_ingress_28_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_28_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_28_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_28_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_27_flit_ready, // @[NoC.scala:143:16]
input io_ingress_27_flit_valid, // @[NoC.scala:143:16]
input io_ingress_27_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_27_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_27_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_27_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_26_flit_ready, // @[NoC.scala:143:16]
input io_ingress_26_flit_valid, // @[NoC.scala:143:16]
input io_ingress_26_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_26_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_26_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_25_flit_ready, // @[NoC.scala:143:16]
input io_ingress_25_flit_valid, // @[NoC.scala:143:16]
input io_ingress_25_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_25_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_25_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_25_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_24_flit_ready, // @[NoC.scala:143:16]
input io_ingress_24_flit_valid, // @[NoC.scala:143:16]
input io_ingress_24_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_24_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_24_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_24_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_23_flit_ready, // @[NoC.scala:143:16]
input io_ingress_23_flit_valid, // @[NoC.scala:143:16]
input io_ingress_23_flit_bits_head, // @[NoC.scala:143:16]
input [72:0] io_ingress_23_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_23_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_22_flit_ready, // @[NoC.scala:143:16]
input io_ingress_22_flit_valid, // @[NoC.scala:143:16]
input io_ingress_22_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_22_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_22_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_22_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_21_flit_ready, // @[NoC.scala:143:16]
input io_ingress_21_flit_valid, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_21_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_21_flit_bits_egress_id, // @[NoC.scala:143:16]
input io_ingress_20_flit_valid, // @[NoC.scala:143:16]
input io_ingress_19_flit_valid, // @[NoC.scala:143:16]
output io_ingress_18_flit_ready, // @[NoC.scala:143:16]
input io_ingress_18_flit_valid, // @[NoC.scala:143:16]
input io_ingress_18_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_18_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_18_flit_bits_payload, // @[NoC.scala:143:16]
input [5:0] io_ingress_18_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_17_flit_ready, // @[NoC.scala:143:16]
input io_ingress_17_flit_valid, // @[NoC.scala:143:16]
input io_ingress_17_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_17_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_17_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_17_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_15_flit_ready, // @[NoC.scala:143:16]
input io_ingress_15_flit_valid, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_15_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_15_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_13_flit_ready, // @[NoC.scala:143:16]
input io_ingress_13_flit_valid, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_13_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_13_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_9_flit_ready, // @[NoC.scala:143:16]
input io_ingress_9_flit_valid, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_9_flit_bits_payload, // @[NoC.scala:143:16]
input [3:0] io_ingress_9_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_6_flit_ready, // @[NoC.scala:143:16]
input io_ingress_6_flit_valid, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_6_flit_bits_payload, // @[NoC.scala:143:16]
input [3:0] io_ingress_6_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_3_flit_ready, // @[NoC.scala:143:16]
input io_ingress_3_flit_valid, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_3_flit_bits_payload, // @[NoC.scala:143:16]
input [3:0] io_ingress_3_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_0_flit_ready, // @[NoC.scala:143:16]
input io_ingress_0_flit_valid, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_0_flit_bits_payload, // @[NoC.scala:143:16]
input [3:0] io_ingress_0_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_egress_49_flit_valid, // @[NoC.scala:143:16]
output io_egress_49_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_49_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_49_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_48_flit_ready, // @[NoC.scala:143:16]
output io_egress_48_flit_valid, // @[NoC.scala:143:16]
output io_egress_48_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_48_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_48_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_47_flit_ready, // @[NoC.scala:143:16]
output io_egress_47_flit_valid, // @[NoC.scala:143:16]
output io_egress_47_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_47_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_47_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_46_flit_valid, // @[NoC.scala:143:16]
output io_egress_46_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_46_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_46_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_45_flit_ready, // @[NoC.scala:143:16]
output io_egress_45_flit_valid, // @[NoC.scala:143:16]
output io_egress_45_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_45_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_45_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_44_flit_ready, // @[NoC.scala:143:16]
output io_egress_44_flit_valid, // @[NoC.scala:143:16]
output io_egress_44_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_44_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_44_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_43_flit_valid, // @[NoC.scala:143:16]
output io_egress_43_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_43_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_43_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_42_flit_ready, // @[NoC.scala:143:16]
output io_egress_42_flit_valid, // @[NoC.scala:143:16]
output io_egress_42_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_42_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_42_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_41_flit_ready, // @[NoC.scala:143:16]
output io_egress_41_flit_valid, // @[NoC.scala:143:16]
output io_egress_41_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_41_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_41_flit_bits_payload, // @[NoC.scala:143:16]
output io_egress_40_flit_valid, // @[NoC.scala:143:16]
output io_egress_40_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_40_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_40_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_39_flit_ready, // @[NoC.scala:143:16]
output io_egress_39_flit_valid, // @[NoC.scala:143:16]
output io_egress_39_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_39_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_39_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_38_flit_ready, // @[NoC.scala:143:16]
output io_egress_38_flit_valid, // @[NoC.scala:143:16]
output io_egress_38_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_38_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_38_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_37_flit_ready, // @[NoC.scala:143:16]
output io_egress_37_flit_valid, // @[NoC.scala:143:16]
output io_egress_37_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_37_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_36_flit_ready, // @[NoC.scala:143:16]
output io_egress_36_flit_valid, // @[NoC.scala:143:16]
output io_egress_36_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_36_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_35_flit_ready, // @[NoC.scala:143:16]
output io_egress_35_flit_valid, // @[NoC.scala:143:16]
output io_egress_35_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_35_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_35_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_34_flit_ready, // @[NoC.scala:143:16]
output io_egress_34_flit_valid, // @[NoC.scala:143:16]
output io_egress_34_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_34_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_34_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_33_flit_ready, // @[NoC.scala:143:16]
output io_egress_33_flit_valid, // @[NoC.scala:143:16]
output io_egress_33_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_33_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_33_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_32_flit_ready, // @[NoC.scala:143:16]
output io_egress_32_flit_valid, // @[NoC.scala:143:16]
output io_egress_32_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_32_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_32_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_31_flit_ready, // @[NoC.scala:143:16]
output io_egress_31_flit_valid, // @[NoC.scala:143:16]
output io_egress_31_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_31_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_31_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_30_flit_ready, // @[NoC.scala:143:16]
output io_egress_30_flit_valid, // @[NoC.scala:143:16]
output io_egress_30_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_30_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_30_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_29_flit_ready, // @[NoC.scala:143:16]
output io_egress_29_flit_valid, // @[NoC.scala:143:16]
output io_egress_29_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_29_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_29_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_28_flit_ready, // @[NoC.scala:143:16]
output io_egress_28_flit_valid, // @[NoC.scala:143:16]
output io_egress_28_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_28_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_28_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_27_flit_ready, // @[NoC.scala:143:16]
output io_egress_27_flit_valid, // @[NoC.scala:143:16]
output io_egress_27_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_27_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_27_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_26_flit_ready, // @[NoC.scala:143:16]
output io_egress_26_flit_valid, // @[NoC.scala:143:16]
output io_egress_26_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_26_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_26_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_25_flit_ready, // @[NoC.scala:143:16]
output io_egress_25_flit_valid, // @[NoC.scala:143:16]
output io_egress_25_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_25_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_25_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_24_flit_ready, // @[NoC.scala:143:16]
output io_egress_24_flit_valid, // @[NoC.scala:143:16]
output io_egress_24_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_24_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_24_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_23_flit_ready, // @[NoC.scala:143:16]
output io_egress_23_flit_valid, // @[NoC.scala:143:16]
output io_egress_23_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_23_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_23_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_22_flit_ready, // @[NoC.scala:143:16]
output io_egress_22_flit_valid, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_22_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_21_flit_ready, // @[NoC.scala:143:16]
output io_egress_21_flit_valid, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_21_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_20_flit_ready, // @[NoC.scala:143:16]
output io_egress_20_flit_valid, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_20_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_19_flit_ready, // @[NoC.scala:143:16]
output io_egress_19_flit_valid, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_19_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_18_flit_ready, // @[NoC.scala:143:16]
output io_egress_18_flit_valid, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_18_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_17_flit_ready, // @[NoC.scala:143:16]
output io_egress_17_flit_valid, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_16_flit_ready, // @[NoC.scala:143:16]
output io_egress_16_flit_valid, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_15_flit_ready, // @[NoC.scala:143:16]
output io_egress_15_flit_valid, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_14_flit_ready, // @[NoC.scala:143:16]
output io_egress_14_flit_valid, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_14_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_13_flit_ready, // @[NoC.scala:143:16]
output io_egress_13_flit_valid, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_12_flit_ready, // @[NoC.scala:143:16]
output io_egress_12_flit_valid, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_11_flit_ready, // @[NoC.scala:143:16]
output io_egress_11_flit_valid, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_11_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_10_flit_ready, // @[NoC.scala:143:16]
output io_egress_10_flit_valid, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_9_flit_ready, // @[NoC.scala:143:16]
output io_egress_9_flit_valid, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_8_flit_ready, // @[NoC.scala:143:16]
output io_egress_8_flit_valid, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_8_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_7_flit_ready, // @[NoC.scala:143:16]
output io_egress_7_flit_valid, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_7_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_6_flit_ready, // @[NoC.scala:143:16]
output io_egress_6_flit_valid, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_5_flit_ready, // @[NoC.scala:143:16]
output io_egress_5_flit_valid, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_5_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_4_flit_ready, // @[NoC.scala:143:16]
output io_egress_4_flit_valid, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_3_flit_ready, // @[NoC.scala:143:16]
output io_egress_3_flit_valid, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_3_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_2_flit_ready, // @[NoC.scala:143:16]
output io_egress_2_flit_valid, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_1_flit_ready, // @[NoC.scala:143:16]
output io_egress_1_flit_valid, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_1_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_0_flit_ready, // @[NoC.scala:143:16]
output io_egress_0_flit_valid, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_tail, // @[NoC.scala:143:16]
input io_router_clocks_0_clock, // @[NoC.scala:143:16]
input io_router_clocks_0_reset, // @[NoC.scala:143:16]
input io_router_clocks_2_clock, // @[NoC.scala:143:16]
input io_router_clocks_2_reset, // @[NoC.scala:143:16]
input io_router_clocks_3_clock, // @[NoC.scala:143:16]
input io_router_clocks_3_reset, // @[NoC.scala:143:16]
input io_router_clocks_4_clock, // @[NoC.scala:143:16]
input io_router_clocks_4_reset, // @[NoC.scala:143:16]
input io_router_clocks_5_clock, // @[NoC.scala:143:16]
input io_router_clocks_5_reset, // @[NoC.scala:143:16]
input io_router_clocks_6_clock, // @[NoC.scala:143:16]
input io_router_clocks_6_reset, // @[NoC.scala:143:16]
input io_router_clocks_8_clock, // @[NoC.scala:143:16]
input io_router_clocks_8_reset, // @[NoC.scala:143:16]
input io_router_clocks_9_clock, // @[NoC.scala:143:16]
input io_router_clocks_9_reset, // @[NoC.scala:143:16]
input io_router_clocks_10_clock, // @[NoC.scala:143:16]
input io_router_clocks_10_reset, // @[NoC.scala:143:16]
input io_router_clocks_11_clock, // @[NoC.scala:143:16]
input io_router_clocks_11_reset, // @[NoC.scala:143:16]
input io_router_clocks_13_clock, // @[NoC.scala:143:16]
input io_router_clocks_13_reset, // @[NoC.scala:143:16]
input io_router_clocks_14_clock, // @[NoC.scala:143:16]
input io_router_clocks_14_reset, // @[NoC.scala:143:16]
input io_router_clocks_15_clock, // @[NoC.scala:143:16]
input io_router_clocks_15_reset, // @[NoC.scala:143:16]
input io_router_clocks_16_clock, // @[NoC.scala:143:16]
input io_router_clocks_16_reset, // @[NoC.scala:143:16]
input io_router_clocks_18_clock, // @[NoC.scala:143:16]
input io_router_clocks_18_reset, // @[NoC.scala:143:16]
input io_router_clocks_20_clock, // @[NoC.scala:143:16]
input io_router_clocks_20_reset, // @[NoC.scala:143:16]
input io_router_clocks_21_clock, // @[NoC.scala:143:16]
input io_router_clocks_21_reset, // @[NoC.scala:143:16]
input io_router_clocks_22_clock, // @[NoC.scala:143:16]
input io_router_clocks_22_reset, // @[NoC.scala:143:16]
input io_router_clocks_23_clock, // @[NoC.scala:143:16]
input io_router_clocks_23_reset, // @[NoC.scala:143:16]
input io_router_clocks_24_clock, // @[NoC.scala:143:16]
input io_router_clocks_24_reset, // @[NoC.scala:143:16]
input io_router_clocks_25_clock, // @[NoC.scala:143:16]
input io_router_clocks_25_reset, // @[NoC.scala:143:16]
input io_router_clocks_26_clock, // @[NoC.scala:143:16]
input io_router_clocks_26_reset, // @[NoC.scala:143:16]
input io_router_clocks_27_clock, // @[NoC.scala:143:16]
input io_router_clocks_27_reset, // @[NoC.scala:143:16]
input io_router_clocks_28_clock, // @[NoC.scala:143:16]
input io_router_clocks_28_reset, // @[NoC.scala:143:16]
input io_router_clocks_29_clock, // @[NoC.scala:143:16]
input io_router_clocks_29_reset, // @[NoC.scala:143:16]
input io_router_clocks_30_clock, // @[NoC.scala:143:16]
input io_router_clocks_30_reset, // @[NoC.scala:143:16]
input io_router_clocks_31_clock, // @[NoC.scala:143:16]
input io_router_clocks_31_reset, // @[NoC.scala:143:16]
input io_router_clocks_32_clock, // @[NoC.scala:143:16]
input io_router_clocks_32_reset, // @[NoC.scala:143:16]
input io_router_clocks_33_clock, // @[NoC.scala:143:16]
input io_router_clocks_33_reset, // @[NoC.scala:143:16]
input io_router_clocks_34_clock, // @[NoC.scala:143:16]
input io_router_clocks_34_reset, // @[NoC.scala:143:16]
input io_router_clocks_35_clock, // @[NoC.scala:143:16]
input io_router_clocks_35_reset, // @[NoC.scala:143:16]
input io_router_clocks_36_clock, // @[NoC.scala:143:16]
input io_router_clocks_36_reset, // @[NoC.scala:143:16]
input io_router_clocks_37_clock, // @[NoC.scala:143:16]
input io_router_clocks_37_reset, // @[NoC.scala:143:16]
input io_router_clocks_38_clock, // @[NoC.scala:143:16]
input io_router_clocks_38_reset // @[NoC.scala:143:16]
);
wire [4:0] _router_sink_domain_38_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_38_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_38_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_38_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_38_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_38_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_38_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_38_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_38_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_38_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_37_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_37_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_36_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_36_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_35_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_35_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_35_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_35_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_35_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_34_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_34_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_34_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_34_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_34_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_33_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_33_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_32_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_32_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_31_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_31_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_30_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_30_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_30_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_30_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_30_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_29_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_29_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_29_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_29_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_29_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_28_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_28_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_28_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_28_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_28_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_27_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_27_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_27_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_27_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_27_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_26_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_26_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_26_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_26_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_26_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_25_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_25_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_25_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_25_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_25_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_24_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_24_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_24_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_24_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_24_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_23_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_23_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_23_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_23_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_23_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_22_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_22_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_22_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_22_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_22_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_21_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_21_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_21_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_21_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_21_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_20_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_20_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_20_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_20_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_20_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_18_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_18_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_18_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_16_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_16_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_16_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_15_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_15_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_15_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_14_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_14_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_14_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_13_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_13_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_13_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_11_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_11_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_11_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_10_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_10_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_10_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_3; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_3; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_9_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_9_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_9_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_8_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_8_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_8_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_6_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_6_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_5_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_5_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_4_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_4_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_6; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_7; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_8; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_6; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_7; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_8; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_2_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_2_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_va_stall_5; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_debug_out_sa_stall_5; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [5:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [4:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [21:0] _router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
reg [63:0] debug_va_stall_ctr; // @[NoC.scala:163:37]
reg [63:0] debug_sa_stall_ctr; // @[NoC.scala:164:37]
wire [63:0] debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50]
always @(posedge clock) begin // @[NoC.scala:141:9]
if (reset) begin // @[NoC.scala:141:9]
debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37]
debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37]
end
else begin // @[NoC.scala:141:9]
debug_va_stall_ctr <=
debug_va_stall_ctr
+ {59'h0,
_router_sink_domain_auto_routers_debug_out_va_stall_0 + _router_sink_domain_auto_routers_debug_out_va_stall_1 + _router_sink_domain_auto_routers_debug_out_va_stall_4 + _router_sink_domain_auto_routers_debug_out_va_stall_5 + _router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _router_sink_domain_2_auto_routers_debug_out_va_stall_4 + _router_sink_domain_2_auto_routers_debug_out_va_stall_5 + _router_sink_domain_2_auto_routers_debug_out_va_stall_6 + _router_sink_domain_2_auto_routers_debug_out_va_stall_7 + _router_sink_domain_2_auto_routers_debug_out_va_stall_8 + _router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _router_sink_domain_5_auto_routers_debug_out_va_stall_2 + _router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _router_sink_domain_6_auto_routers_debug_out_va_stall_4 + _router_sink_domain_6_auto_routers_debug_out_va_stall_5 + _router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _router_sink_domain_8_auto_routers_debug_out_va_stall_4 + _router_sink_domain_8_auto_routers_debug_out_va_stall_5 + _router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _router_sink_domain_9_auto_routers_debug_out_va_stall_3 + _router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _router_sink_domain_10_auto_routers_debug_out_va_stall_3 + _router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _router_sink_domain_11_auto_routers_debug_out_va_stall_2
+ _router_sink_domain_11_auto_routers_debug_out_va_stall_3 + _router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _router_sink_domain_13_auto_routers_debug_out_va_stall_3 + _router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _router_sink_domain_14_auto_routers_debug_out_va_stall_1 + _router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _router_sink_domain_14_auto_routers_debug_out_va_stall_3 + _router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _router_sink_domain_15_auto_routers_debug_out_va_stall_1 + _router_sink_domain_15_auto_routers_debug_out_va_stall_2 + _router_sink_domain_15_auto_routers_debug_out_va_stall_3 + _router_sink_domain_16_auto_routers_debug_out_va_stall_0 + _router_sink_domain_16_auto_routers_debug_out_va_stall_1 + _router_sink_domain_16_auto_routers_debug_out_va_stall_2 + _router_sink_domain_16_auto_routers_debug_out_va_stall_3 + _router_sink_domain_18_auto_routers_debug_out_va_stall_0 + _router_sink_domain_18_auto_routers_debug_out_va_stall_1 + _router_sink_domain_18_auto_routers_debug_out_va_stall_2 + _router_sink_domain_18_auto_routers_debug_out_va_stall_3 + _router_sink_domain_20_auto_routers_debug_out_va_stall_0 + _router_sink_domain_20_auto_routers_debug_out_va_stall_1 + _router_sink_domain_21_auto_routers_debug_out_va_stall_0 + _router_sink_domain_21_auto_routers_debug_out_va_stall_1 + _router_sink_domain_22_auto_routers_debug_out_va_stall_0 + _router_sink_domain_22_auto_routers_debug_out_va_stall_1 + _router_sink_domain_23_auto_routers_debug_out_va_stall_0 + _router_sink_domain_23_auto_routers_debug_out_va_stall_1 + _router_sink_domain_24_auto_routers_debug_out_va_stall_0 + _router_sink_domain_24_auto_routers_debug_out_va_stall_1 + _router_sink_domain_25_auto_routers_debug_out_va_stall_0 + _router_sink_domain_25_auto_routers_debug_out_va_stall_1 + _router_sink_domain_26_auto_routers_debug_out_va_stall_0
+ _router_sink_domain_26_auto_routers_debug_out_va_stall_1 + _router_sink_domain_27_auto_routers_debug_out_va_stall_0 + _router_sink_domain_27_auto_routers_debug_out_va_stall_1 + _router_sink_domain_28_auto_routers_debug_out_va_stall_0 + _router_sink_domain_28_auto_routers_debug_out_va_stall_1 + _router_sink_domain_29_auto_routers_debug_out_va_stall_0 + _router_sink_domain_29_auto_routers_debug_out_va_stall_1 + _router_sink_domain_30_auto_routers_debug_out_va_stall_0 + _router_sink_domain_30_auto_routers_debug_out_va_stall_1 + _router_sink_domain_31_auto_routers_debug_out_va_stall_0 + _router_sink_domain_31_auto_routers_debug_out_va_stall_1 + _router_sink_domain_31_auto_routers_debug_out_va_stall_2 + _router_sink_domain_32_auto_routers_debug_out_va_stall_0 + _router_sink_domain_32_auto_routers_debug_out_va_stall_1 + _router_sink_domain_32_auto_routers_debug_out_va_stall_2 + _router_sink_domain_33_auto_routers_debug_out_va_stall_0 + _router_sink_domain_33_auto_routers_debug_out_va_stall_1 + _router_sink_domain_33_auto_routers_debug_out_va_stall_2 + _router_sink_domain_34_auto_routers_debug_out_va_stall_0 + _router_sink_domain_34_auto_routers_debug_out_va_stall_1 + _router_sink_domain_35_auto_routers_debug_out_va_stall_0 + _router_sink_domain_35_auto_routers_debug_out_va_stall_1 + _router_sink_domain_36_auto_routers_debug_out_va_stall_0 + _router_sink_domain_36_auto_routers_debug_out_va_stall_1 + _router_sink_domain_36_auto_routers_debug_out_va_stall_2 + _router_sink_domain_37_auto_routers_debug_out_va_stall_0 + _router_sink_domain_37_auto_routers_debug_out_va_stall_1 + _router_sink_domain_37_auto_routers_debug_out_va_stall_2 + _router_sink_domain_38_auto_routers_debug_out_va_stall_0 + _router_sink_domain_38_auto_routers_debug_out_va_stall_1}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}]
debug_sa_stall_ctr <=
debug_sa_stall_ctr
+ {59'h0,
_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_auto_routers_debug_out_sa_stall_5 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_5 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_6 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_7 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_8 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_5 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_5 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_2
+ _router_sink_domain_11_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_16_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_18_auto_routers_debug_out_sa_stall_3 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_20_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_21_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_22_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_23_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_24_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_24_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_25_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_26_auto_routers_debug_out_sa_stall_0
+ _router_sink_domain_26_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_27_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_28_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_28_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_29_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_29_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_30_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_30_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_31_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_31_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_31_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_32_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_32_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_32_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_33_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_33_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_33_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_34_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_34_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_35_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_35_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_36_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_36_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_36_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_37_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_37_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_37_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_38_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_38_auto_routers_debug_out_sa_stall_1}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_2( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File NBDcache.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
trait HasMissInfo extends Bundle with HasL1HellaCacheParameters {
val tag_match = Bool()
val old_meta = new L1Metadata
val way_en = Bits(nWays.W)
}
class L1DataReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val way_en = Bits(nWays.W)
val addr = Bits(untagBits.W)
}
class L1DataWriteReq(implicit p: Parameters) extends L1DataReadReq()(p) {
val wmask = Bits(rowWords.W)
val data = Bits(encRowBits.W)
}
class L1RefillReq(implicit p: Parameters) extends L1DataReadReq()(p)
class Replay(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class ReplayInternal(implicit p: Parameters) extends HellaCacheReqInternal()(p)
with HasL1HellaCacheParameters {
val sdq_id = UInt(log2Up(cfg.nSDQ).W)
}
class MSHRReq(implicit p: Parameters) extends Replay()(p) with HasMissInfo
class MSHRReqInternal(implicit p: Parameters) extends ReplayInternal()(p) with HasMissInfo
class WritebackReq(params: TLBundleParameters)(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val tag = Bits(tagBits.W)
val idx = Bits(idxBits.W)
val source = UInt(params.sourceBits.W)
val param = UInt(TLPermissions.cWidth.W)
val way_en = Bits(nWays.W)
val voluntary = Bool()
}
class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new HellaCacheReq))
val resp = Decoupled(new HellaCacheResp)
val mem_access = Decoupled(new TLBundleA(edge.bundle))
val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
val replay_next = Output(Bool())
val store_pending = Output(Bool())
})
def beatOffset(addr: UInt) = addr.extract(beatOffBits - 1, wordOffBits)
def wordFromBeat(addr: UInt, dat: UInt) = {
val shift = Cat(beatOffset(addr), 0.U((wordOffBits + log2Up(wordBytes)).W))
(dat >> shift)(wordBits - 1, 0)
}
val req = Reg(new HellaCacheReq)
val grant_word = Reg(UInt(wordBits.W))
val s_idle :: s_mem_access :: s_mem_ack :: s_resp_1 :: s_resp_2 :: Nil = Enum(5)
val state = RegInit(s_idle)
io.req.ready := (state === s_idle)
val loadgen = new LoadGen(req.size, req.signed, req.addr, grant_word, false.B, wordBytes)
val a_source = id.U
val a_address = req.addr
val a_size = req.size
val a_data = Fill(beatWords, req.data)
val get = edge.Get(a_source, a_address, a_size)._2
val put = edge.Put(a_source, a_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert(state === s_idle || !isAMO(req.cmd))
(0.U).asTypeOf(new TLBundleA(edge.bundle))
}
assert(state === s_idle || req.cmd =/= M_XSC)
io.mem_access.valid := (state === s_mem_access)
io.mem_access.bits := Mux(isAMO(req.cmd), atomics, Mux(isRead(req.cmd), get, put))
io.replay_next := state === s_resp_1 || (state === s_resp_2 && !io.resp.ready)
io.resp.valid := state === s_resp_2
io.resp.bits.addr := req.addr
io.resp.bits.idx.foreach(_ := req.idx.get)
io.resp.bits.tag := req.tag
io.resp.bits.cmd := req.cmd
io.resp.bits.size := req.size
io.resp.bits.signed := req.signed
io.resp.bits.dprv := req.dprv
io.resp.bits.dv := req.dv
io.resp.bits.mask := req.mask
io.resp.bits.has_data := isRead(req.cmd)
io.resp.bits.data := loadgen.data
io.resp.bits.data_raw := grant_word
io.resp.bits.data_word_bypass := loadgen.wordData
io.resp.bits.store_data := req.data
io.resp.bits.replay := true.B
io.store_pending := state =/= s_idle && isWrite(req.cmd)
when (io.req.fire) {
req := io.req.bits
state := s_mem_access
}
when (io.mem_access.fire) {
state := s_mem_ack
}
when (state === s_mem_ack && io.mem_ack.valid) {
state := Mux(req.no_resp || !isRead(req.cmd), s_idle, s_resp_1)
when (isRead(req.cmd)) {
grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
}
}
when (state === s_resp_1) {
state := s_resp_2
}
when (io.resp.fire) {
state := s_idle
}
}
class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val req_bits = Input(new MSHRReqInternal())
val idx_match = Output(Bool())
val tag = Output(Bits(tagBits.W))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Output(new L1RefillReq()) // Data is bypassed
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val replay = Decoupled(new ReplayInternal)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val probe_rdy = Output(Bool())
})
val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9)
val state = RegInit(s_invalid)
val req = Reg(new MSHRReqInternal)
val req_idx = req.addr(untagBits-1,blockOffBits)
val req_tag = req.addr >> untagBits
val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits)
val new_coh = RegInit(ClientMetadata.onReset)
val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)
val grow_param = new_coh.onAccess(req.cmd)._2
val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param)
// We only accept secondary misses if we haven't yet sent an Acquire to outer memory
// or if the Acquire that was sent will obtain a Grant with sufficient permissions
// to let us replay this new request. I.e. we don't handle multiple outstanding
// Acquires on the same block for now.
val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =
new_coh.onSecondaryAccess(req.cmd, io.req_bits.cmd)
val states_before_refill = Seq(s_wb_req, s_wb_resp, s_meta_clear)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val sec_rdy = idx_match &&
(state.isOneOf(states_before_refill) ||
(state.isOneOf(s_refill_req, s_refill_resp) &&
!cmd_requires_second_acquire && !refill_done))
val rpq = Module(new Queue(new ReplayInternal, cfg.nRPQ))
rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(io.req_bits.cmd)
rpq.io.enq.bits := io.req_bits
rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid
val acked = Reg(Bool())
when (io.mem_grant.valid) { acked := true.B }
when (state === s_drain_rpq && !rpq.io.deq.valid) {
state := s_invalid
}
when (state === s_meta_write_resp) {
// this wait state allows us to catch RAW hazards on the tags via nack_victim
state := s_drain_rpq
}
when (state === s_meta_write_req && io.meta_write.ready) {
state := s_meta_write_resp
}
when (state === s_refill_resp && refill_done) {
new_coh := coh_on_grant
state := s_meta_write_req
}
when (io.mem_acquire.fire) { // s_refill_req
state := s_refill_resp
}
when (state === s_meta_clear && io.meta_write.ready) {
state := s_refill_req
}
when (state === s_wb_resp && io.wb_req.ready && acked) {
state := s_meta_clear
}
when (io.wb_req.fire) { // s_wb_req
state := s_wb_resp
}
when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
//If we get a secondary miss that needs more permissions before we've sent
// out the primary miss's Acquire, we can upgrade the permissions we're
// going to ask for in s_refill_req
req.cmd := dirtier_cmd
when (is_hit_again) {
new_coh := dirtier_coh
}
}
when (io.req_pri_val && io.req_pri_rdy) {
req := io.req_bits
acked := false.B
val old_coh = io.req_bits.old_meta.coh
val needs_wb = old_coh.onCacheControl(M_FLUSH)._1
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd)
when (io.req_bits.tag_match) {
when (is_hit) { // set dirty bit
new_coh := coh_on_hit
state := s_meta_write_req
}.otherwise { // upgrade permissions
new_coh := old_coh
state := s_refill_req
}
}.otherwise { // writback if necessary and refill
new_coh := ClientMetadata.onReset
state := Mux(needs_wb, s_wb_req, s_meta_clear)
}
}
val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1))
val can_finish = state.isOneOf(s_invalid, s_refill_req)
grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits)
grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits)
io.mem_finish.valid := grantackq.io.deq.valid && can_finish
io.mem_finish.bits := grantackq.io.deq.bits
grantackq.io.deq.ready := io.mem_finish.ready && can_finish
io.idx_match := (state =/= s_invalid) && idx_match
io.refill.way_en := req.way_en
io.refill.addr := req_block_addr | refill_address_inc
io.tag := req_tag
io.req_pri_rdy := state === s_invalid
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := !idx_match || (!state.isOneOf(states_before_refill) && meta_hazard === 0.U)
io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear)
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tag := io.tag
io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh)
io.meta_write.bits.data.tag := io.tag
io.meta_write.bits.way_en := req.way_en
io.wb_req.valid := state === s_wb_req
io.wb_req.bits.source := id.U
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.param := shrink_param
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.voluntary := true.B
io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = id.U,
toAddress = Cat(io.tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2
io.meta_read.valid := state === s_drain_rpq
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := io.tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid
io.replay.bits := rpq.io.deq.bits
io.replay.bits.phys := true.B
io.replay.bits.addr := Cat(io.tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
when (!io.meta_read.ready) {
rpq.io.deq.ready := false.B
io.replay.bits.cmd := M_FLUSH_ALL /* nop */
}
}
class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new MSHRReq))
val resp = Decoupled(new HellaCacheResp)
val secondary_miss = Output(Bool())
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Valid(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Output(new L1RefillReq())
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val replay = Decoupled(new Replay)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val probe_rdy = Output(Bool())
val fence_rdy = Output(Bool())
val replay_next = Output(Bool())
val store_pending = Output(Bool())
})
// determine if the request is cacheable or not
val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes.U)
val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))
when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
val idxMatch = Wire(Vec(cfg.nMSHRs, Bool()))
val tagList = Wire(Vec(cfg.nMSHRs, Bits(tagBits.W)))
val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
val wbTagList = Wire(Vec(cfg.nMSHRs, Bits()))
val refillMux = Wire(Vec(cfg.nMSHRs, new L1RefillReq))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, cfg.nMSHRs))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, cfg.nMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))
val replay_arb = Module(new Arbiter(new ReplayInternal, cfg.nMSHRs))
val alloc_arb = Module(new Arbiter(Bool(), cfg.nMSHRs))
alloc_arb.io.in.foreach(_.bits := DontCare)
var idx_match = false.B
var pri_rdy = false.B
var sec_rdy = false.B
io.fence_rdy := true.B
io.probe_rdy := true.B
val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new MSHR(i))
idxMatch(i) := mshr.io.idx_match
tagList(i) := mshr.io.tag
wbTagList(i) := mshr.io.wb_req.bits.tag
alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
mshr.io.req_pri_val := alloc_arb.io.in(i).ready
mshr.io.req_sec_val := io.req.valid && sdq_rdy && tag_match
mshr.io.req_bits.viewAsSupertype(new HellaCacheReqInternal) := io.req.bits.viewAsSupertype(new HellaCacheReqInternal)
mshr.io.req_bits.tag_match := io.req.bits.tag_match
mshr.io.req_bits.old_meta := io.req.bits.old_meta
mshr.io.req_bits.way_en := io.req.bits.way_en
mshr.io.req_bits.sdq_id := sdq_alloc_id
meta_read_arb.io.in(i) <> mshr.io.meta_read
meta_write_arb.io.in(i) <> mshr.io.meta_write
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
mshr.io.mem_grant.valid := io.mem_grant.valid && io.mem_grant.bits.source === i.U
mshr.io.mem_grant.bits := io.mem_grant.bits
refillMux(i) := mshr.io.refill
pri_rdy = pri_rdy || mshr.io.req_pri_rdy
sec_rdy = sec_rdy || mshr.io.req_sec_rdy
idx_match = idx_match || mshr.io.idx_match
when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B }
when (!mshr.io.probe_rdy) { io.probe_rdy := false.B }
mshr
}
alloc_arb.io.out.ready := io.req.valid && sdq_rdy && cacheable && !idx_match
io.meta_read <> meta_read_arb.io.out
io.meta_write <> meta_write_arb.io.out
io.wb_req <> wb_req_arb.io.out
val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
mmio_alloc_arb.io.in.foreach(_.bits := DontCare)
val resp_arb = Module(new Arbiter(new HellaCacheResp, nIOMSHRs))
var mmio_rdy = false.B
io.replay_next := false.B
val mmios = (0 until nIOMSHRs) map { i =>
val id = cfg.nMSHRs + i
val mshr = Module(new IOMSHR(id))
mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
mshr.io.req.bits := io.req.bits
mmio_rdy = mmio_rdy || mshr.io.req.ready
mshr.io.mem_ack.bits := io.mem_grant.bits
mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U
resp_arb.io.in(i) <> mshr.io.resp
when (!mshr.io.req.ready) { io.fence_rdy := false.B }
when (mshr.io.replay_next) { io.replay_next := true.B }
mshr
}
mmio_alloc_arb.io.out.ready := io.req.valid && !cacheable
TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))
io.store_pending := sdq_val =/= 0.U || mmios.map(_.io.store_pending).orR
io.resp <> resp_arb.io.out
io.req.ready := Mux(!cacheable,
mmio_rdy,
sdq_rdy && Mux(idx_match, tag_match && sec_rdy, pri_rdy))
io.secondary_miss := idx_match
io.refill := refillMux(io.mem_grant.bits.source)
val free_sdq = io.replay.fire && isWrite(io.replay.bits.cmd)
io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq))
io.replay.bits.mask := 0.U
io.replay.valid := replay_arb.io.out.valid
replay_arb.io.out.ready := io.replay.ready
io.replay.bits.viewAsSupertype(new HellaCacheReqInternal) <> replay_arb.io.out.bits.viewAsSupertype(new HellaCacheReqInternal)
when (io.replay.valid || sdq_enq) {
sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)
}
}
class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))
val meta_read = Decoupled(new L1MetaReadReq)
val data_req = Decoupled(new L1DataReadReq)
val data_resp = Input(Bits(encRowBits.W))
val release = Decoupled(new TLBundleC(edge.bundle))
})
val req = Reg(new WritebackReq(edge.bundle))
val active = RegInit(false.B)
val r1_data_req_fired = RegInit(false.B)
val r2_data_req_fired = RegInit(false.B)
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) //TODO Zero width
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)
io.release.valid := false.B
when (active) {
r1_data_req_fired := false.B
r2_data_req_fired := r1_data_req_fired
when (io.data_req.fire && io.meta_read.fire) {
r1_data_req_fired := true.B
data_req_cnt := data_req_cnt + 1.U
}
when (r2_data_req_fired) {
io.release.valid := true.B
when(!io.release.ready) {
r1_data_req_fired := false.B
r2_data_req_fired := false.B
data_req_cnt := data_req_cnt - Mux[UInt]((refillCycles > 1).B && r1_data_req_fired, 2.U, 1.U)
}
when(!r1_data_req_fired) {
// We're done if this is the final data request and the Release can be sent
active := data_req_cnt < refillCycles.U || !io.release.ready
}
}
}
when (io.req.fire) {
active := true.B
data_req_cnt := 0.U
req := io.req.bits
}
io.req.ready := !active
val fire = active && data_req_cnt < refillCycles.U
// We reissue the meta read as it sets up the mux ctrl for s2_data_muxed
io.meta_read.valid := fire
io.meta_read.bits.idx := req.idx
io.meta_read.bits.tag := req.tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.data_req.valid := fire
io.data_req.bits.way_en := req.way_en
io.data_req.bits.addr := (if(refillCycles > 1)
Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))
else req.idx) << rowOffBits
val r_address = Cat(req.tag, req.idx) << blockOffBits
val probeResponse = edge.ProbeAck(
fromSource = req.source,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
reportPermissions = req.param,
data = io.data_resp)
val voluntaryRelease = edge.Release(
fromSource = req.source,
toAddress = r_address,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = req.param,
data = io.data_resp)._2
io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)
}
class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))
val rep = Decoupled(new TLBundleC(edge.bundle))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val way_en = Input(Bits(nWays.W))
val mshr_rdy = Input(Bool())
val block_state = Input(new ClientMetadata())
})
val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::
s_mshr_resp :: s_release :: s_writeback_req :: s_writeback_resp ::
s_meta_write :: Nil) = Enum(9)
val state = RegInit(s_invalid)
val req = Reg(new TLBundleB(edge.bundle))
val req_idx = req.address(idxMSB, idxLSB)
val req_tag = req.address >> untagBits
val way_en = Reg(Bits())
val tag_matches = way_en.orR
val old_coh = Reg(new ClientMetadata)
val miss_coh = ClientMetadata.onReset
val reply_coh = Mux(tag_matches, old_coh, miss_coh)
val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)
io.req.ready := state === s_invalid
io.rep.valid := state === s_release
io.rep.bits := edge.ProbeAck(req, report_param)
assert(!io.rep.valid || !edge.hasData(io.rep.bits),
"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it")
io.meta_read.valid := state === s_meta_read
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := ~(0.U(nWays.W))
io.meta_write.valid := state === s_meta_write
io.meta_write.bits.way_en := way_en
io.meta_write.bits.idx := req_idx
io.meta_write.bits.tag := req_tag
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.data.coh := new_coh
io.wb_req.valid := state === s_writeback_req
io.wb_req.bits.source := req.source
io.wb_req.bits.idx := req_idx
io.wb_req.bits.tag := req_tag
io.wb_req.bits.param := report_param
io.wb_req.bits.way_en := way_en
io.wb_req.bits.voluntary := false.B
// state === s_invalid
when (io.req.fire) {
state := s_meta_read
req := io.req.bits
}
// state === s_meta_read
when (io.meta_read.fire) {
state := s_meta_resp
}
// we need to wait one cycle for the metadata to be read from the array
when (state === s_meta_resp) {
state := s_mshr_req
}
when (state === s_mshr_req) {
old_coh := io.block_state
way_en := io.way_en
// if the read didn't go through, we need to retry
state := Mux(io.mshr_rdy, s_mshr_resp, s_meta_read)
}
when (state === s_mshr_resp) {
state := Mux(tag_matches && is_dirty, s_writeback_req, s_release)
}
when (state === s_release && io.rep.ready) {
state := Mux(tag_matches, s_meta_write, s_invalid)
}
// state === s_writeback_req
when (io.wb_req.fire) {
state := s_writeback_resp
}
// wait for the writeback request to finish before updating the metadata
when (state === s_writeback_resp && io.wb_req.ready) {
state := s_meta_write
}
when (io.meta_write.fire) {
state := s_invalid
}
}
class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val read = Flipped(Decoupled(new L1DataReadReq))
val write = Flipped(Decoupled(new L1DataWriteReq))
val resp = Output(Vec(nWays, Bits(encRowBits.W)))
})
val waddr = io.write.bits.addr >> rowOffBits
val raddr = io.read.bits.addr >> rowOffBits
if (doNarrowRead) {
for (w <- 0 until nWays by rowWords) {
val wway_en = io.write.bits.way_en(w+rowWords-1,w)
val rway_en = io.read.bits.way_en(w+rowWords-1,w)
val resp = Wire(Vec(rowWords, Bits(encRowBits.W)))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (i <- 0 until resp.size) {
val array = DescribedSRAM(
name = s"array_${w}_${i}",
desc = "Non-blocking DCache Data Array",
size = nSets * refillCycles,
data = Vec(rowWords, Bits(encDataBits.W))
)
when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) {
val data = VecInit.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, wway_en.asBools)
}
resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt
}
for (dw <- 0 until rowWords) {
val r = VecInit(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
val resp_mux =
if (r.size == 1) r
else VecInit(r(r_raddr(rowOffBits-1,wordOffBits)), r.tail:_*)
io.resp(w+dw) := resp_mux.asUInt
}
}
} else {
for (w <- 0 until nWays) {
val array = DescribedSRAM(
name = s"array_${w}",
desc = "Non-blocking DCache Data Array",
size = nSets * refillCycles,
data = Vec(rowWords, Bits(encDataBits.W))
)
when (io.write.bits.way_en(w) && io.write.valid) {
val data = VecInit.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, io.write.bits.wmask.asBools)
}
io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
}
}
io.read.ready := true.B
io.write.ready := true.B
}
class NonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) {
override lazy val module = new NonBlockingDCacheModule(this)
}
class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule(outer) {
require(isPow2(nWays)) // TODO: relax this
require(dataScratchpadSize == 0)
require(!usingVM || untagBits <= pgIdxBits, s"untagBits($untagBits) > pgIdxBits($pgIdxBits)")
require(!cacheParams.separateUncachedResp)
// ECC is only supported on the data array
require(cacheParams.tagCode.isInstanceOf[IdentityCode])
val dECC = cacheParams.dataCode
io.cpu := DontCare
io.errors := DontCare
val wb = Module(new WritebackUnit)
val prober = Module(new ProbeUnit)
val mshrs = Module(new MSHRFile)
io.tlb_port.req.ready := true.B
io.cpu.req.ready := true.B
val s1_valid = RegNext(io.cpu.req.fire, false.B)
val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B)
val s1_tlb_req = RegEnable(io.tlb_port.req.bits, io.tlb_port.req.fire)
val s1_req = Reg(new HellaCacheReq)
val s1_valid_masked = s1_valid && !io.cpu.s1_kill
val s1_replay = RegInit(false.B)
val s1_clk_en = Reg(Bool())
val s1_sfence = s1_req.cmd === M_SFENCE
val s2_valid = RegNext(s1_valid_masked && !s1_sfence, false.B) && !io.cpu.s2_xcpt.asUInt.orR
val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B)
val s2_req = Reg(new HellaCacheReq)
val s2_replay = RegNext(s1_replay, false.B) && s2_req.cmd =/= M_FLUSH_ALL
val s2_recycle = Wire(Bool())
val s2_valid_masked = Wire(Bool())
val s3_valid = RegInit(false.B)
val s3_req = Reg(new HellaCacheReq)
val s3_way = Reg(Bits())
val s1_recycled = RegEnable(s2_recycle, false.B, s1_clk_en)
val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd)
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
// check for unsupported operations
assert(!s1_valid || !s1_req.cmd.isOneOf(M_PWR))
val dtlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays)))
io.ptw <> dtlb.io.ptw
dtlb.io.kill := io.cpu.s2_kill
dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && s1_readwrite
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.vaddr := s1_req.addr
dtlb.io.req.bits.size := s1_req.size
dtlb.io.req.bits.cmd := s1_req.cmd
dtlb.io.req.bits.prv := s1_req.dprv
dtlb.io.req.bits.v := s1_req.dv
when (s1_tlb_req_valid) { dtlb.io.req.bits := s1_tlb_req }
when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B }
dtlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence
dtlb.io.sfence.bits.rs1 := s1_req.size(0)
dtlb.io.sfence.bits.rs2 := s1_req.size(1)
dtlb.io.sfence.bits.addr := s1_req.addr
dtlb.io.sfence.bits.asid := io.cpu.s1_data.data
dtlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV
dtlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG
when (io.cpu.req.valid) {
s1_req := io.cpu.req.bits
}
when (wb.io.meta_read.valid) {
s1_req.addr := Cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) << blockOffBits
s1_req.phys := true.B
}
when (prober.io.meta_read.valid) {
s1_req.addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits
s1_req.phys := true.B
}
when (mshrs.io.replay.valid) {
s1_req := mshrs.io.replay.bits
}
when (s2_recycle) {
s1_req := s2_req
}
val s1_addr = Mux(s1_req.phys, s1_req.addr, dtlb.io.resp.paddr)
io.tlb_port.s1_resp := dtlb.io.resp
when (s1_clk_en) {
s2_req.size := s1_req.size
s2_req.signed := s1_req.signed
s2_req.phys := s1_req.phys
s2_req.addr := s1_addr
s2_req.no_resp := s1_req.no_resp
when (s1_write) {
s2_req.data := Mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.s1_data.data)
}
when (s1_recycled) { s2_req.data := s1_req.data }
s2_req.tag := s1_req.tag
s2_req.cmd := s1_req.cmd
}
// tags
def onReset = L1Metadata(0.U, ClientMetadata.onReset)
val meta = Module(new L1MetadataArray(() => onReset ))
val metaReadArb = Module(new Arbiter(new L1MetaReadReq, 5))
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
meta.io.read <> metaReadArb.io.out
meta.io.write <> metaWriteArb.io.out
// data
val data = Module(new DataArray)
val readArb = Module(new Arbiter(new L1DataReadReq, 4))
val writeArb = Module(new Arbiter(new L1DataWriteReq, 2))
data.io.write.valid := writeArb.io.out.valid
writeArb.io.out.ready := data.io.write.ready
data.io.write.bits := writeArb.io.out.bits
val wdata_encoded = (0 until rowWords).map(i => dECC.encode(writeArb.io.out.bits.data(coreDataBits*(i+1)-1,coreDataBits*i)))
data.io.write.bits.data := wdata_encoded.asUInt
// tag read for new requests
metaReadArb.io.in(4).valid := io.cpu.req.valid
metaReadArb.io.in(4).bits.idx := io.cpu.req.bits.addr >> blockOffBits
metaReadArb.io.in(4).bits.tag := io.cpu.req.bits.addr >> untagBits
metaReadArb.io.in(4).bits.way_en := ~0.U(nWays.W)
when (!metaReadArb.io.in(4).ready) { io.cpu.req.ready := false.B }
// data read for new requests
readArb.io.in(3).valid := io.cpu.req.valid
readArb.io.in(3).bits.addr := io.cpu.req.bits.addr
readArb.io.in(3).bits.way_en := ~0.U(nWays.W)
when (!readArb.io.in(3).ready) { io.cpu.req.ready := false.B }
// recycled requests
metaReadArb.io.in(0).valid := s2_recycle
metaReadArb.io.in(0).bits.idx := s2_req.addr >> blockOffBits
metaReadArb.io.in(0).bits.way_en := ~0.U(nWays.W)
metaReadArb.io.in(0).bits.tag := s2_req.tag
readArb.io.in(0).valid := s2_recycle
readArb.io.in(0).bits.addr := s2_req.addr
readArb.io.in(0).bits.way_en := ~0.U(nWays.W)
// tag check and way muxing
def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> untagBits)).asUInt
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && meta.io.resp(w).coh.isValid()).asUInt
s1_clk_en := metaReadArb.io.out.valid //TODO: should be metaReadArb.io.out.fire, but triggers Verilog backend bug
val s1_writeback = s1_clk_en && !s1_valid && !s1_replay
val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
val s2_tag_match = s2_tag_match_way.orR
val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
val (s2_has_permission, _, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
val s2_hit = s2_tag_match && s2_has_permission && s2_hit_state === s2_new_hit_state
// load-reserved/store-conditional
val lrsc_count = RegInit(0.U)
val lrsc_valid = lrsc_count > lrscBackoff.U
val lrsc_addr = Reg(UInt())
val (s2_lr, s2_sc) = (s2_req.cmd === M_XLR, s2_req.cmd === M_XSC)
val s2_lrsc_addr_match = lrsc_valid && lrsc_addr === (s2_req.addr >> blockOffBits)
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match
when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }
when (s2_valid_masked && s2_hit || s2_replay) {
when (s2_lr) {
lrsc_count := lrscCycles.U - 1.U
lrsc_addr := s2_req.addr >> blockOffBits
}
when (lrsc_count > 0.U) {
lrsc_count := 0.U
}
}
when (s2_valid_masked && !(s2_tag_match && s2_has_permission) && s2_lrsc_addr_match) {
lrsc_count := 0.U
}
val s2_data = Wire(Vec(nWays, Bits(encRowBits.W)))
for (w <- 0 until nWays) {
val regs = Reg(Vec(rowWords, Bits(encDataBits.W)))
val en1 = s1_clk_en && s1_tag_eq_way(w)
for (i <- 0 until regs.size) {
val en = en1 && (((i == 0).B || !doNarrowRead.B) || s1_writeback)
when (en) { regs(i) := data.io.resp(w) >> encDataBits*i }
}
s2_data(w) := regs.asUInt
}
val s2_data_muxed = Mux1H(s2_tag_match_way, s2_data)
val s2_data_decoded = (0 until rowWords).map(i => dECC.decode(s2_data_muxed(encDataBits*(i+1)-1,encDataBits*i)))
val s2_data_corrected = s2_data_decoded.map(_.corrected).asUInt
val s2_data_uncorrected = s2_data_decoded.map(_.uncorrected).asUInt
val s2_word_idx = if(doNarrowRead) 0.U else s2_req.addr(log2Up(rowWords*coreDataBytes)-1,log2Up(wordBytes))
val s2_data_correctable = s2_data_decoded.map(_.correctable).asUInt(s2_word_idx)
// store/amo hits
s3_valid := (s2_valid_masked && s2_hit || s2_replay) && !s2_sc_fail && isWrite(s2_req.cmd)
val amoalu = Module(new AMOALU(xLen))
when ((s2_valid || s2_replay) && (isWrite(s2_req.cmd) || s2_data_correctable)) {
s3_req := s2_req
s3_req.data := Mux(s2_data_correctable, s2_data_corrected, amoalu.io.out)
s3_way := s2_tag_match_way
}
writeArb.io.in(0).bits.addr := s3_req.addr
writeArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))
writeArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)
writeArb.io.in(0).valid := s3_valid
writeArb.io.in(0).bits.way_en := s3_way
// replacement policy
val replacer = cacheParams.replacement
val s1_replaced_way_en = UIntToOH(replacer.way)
val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
// miss handling
mshrs.io.req.valid := s2_valid_masked && !s2_hit && (isPrefetch(s2_req.cmd) || isRead(s2_req.cmd) || isWrite(s2_req.cmd))
mshrs.io.req.bits.viewAsSupertype(new Replay) := s2_req.viewAsSupertype(new HellaCacheReq)
mshrs.io.req.bits.tag_match := s2_tag_match
mshrs.io.req.bits.old_meta := Mux(s2_tag_match, L1Metadata(s2_repl_meta.tag, s2_hit_state), s2_repl_meta)
mshrs.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
mshrs.io.req.bits.data := s2_req.data
when (mshrs.io.req.fire) { replacer.miss }
tl_out.a <> mshrs.io.mem_acquire
// replays
readArb.io.in(1).valid := mshrs.io.replay.valid
readArb.io.in(1).bits.addr := mshrs.io.replay.bits.addr
readArb.io.in(1).bits.way_en := ~0.U(nWays.W)
mshrs.io.replay.ready := readArb.io.in(1).ready
s1_replay := mshrs.io.replay.valid && readArb.io.in(1).ready
metaReadArb.io.in(1) <> mshrs.io.meta_read
metaWriteArb.io.in(0) <> mshrs.io.meta_write
// probes and releases
prober.io.req.valid := tl_out.b.valid && !lrsc_valid
tl_out.b.ready := prober.io.req.ready && !lrsc_valid
prober.io.req.bits := tl_out.b.bits
prober.io.way_en := s2_tag_match_way
prober.io.block_state := s2_hit_state
metaReadArb.io.in(2) <> prober.io.meta_read
metaWriteArb.io.in(1) <> prober.io.meta_write
prober.io.mshr_rdy := mshrs.io.probe_rdy
// refills
val grant_has_data = edge.hasData(tl_out.d.bits)
mshrs.io.mem_grant.valid := tl_out.d.fire
mshrs.io.mem_grant.bits := tl_out.d.bits
tl_out.d.ready := writeArb.io.in(1).ready || !grant_has_data
/* The last clause here is necessary in order to prevent the responses for
* the IOMSHRs from being written into the data array. It works because the
* IOMSHR ids start right the ones for the regular MSHRs. */
writeArb.io.in(1).valid := tl_out.d.valid && grant_has_data &&
tl_out.d.bits.source < cfg.nMSHRs.U
writeArb.io.in(1).bits.addr := mshrs.io.refill.addr
writeArb.io.in(1).bits.way_en := mshrs.io.refill.way_en
writeArb.io.in(1).bits.wmask := ~0.U(rowWords.W)
writeArb.io.in(1).bits.data := tl_out.d.bits.data(encRowBits-1,0)
data.io.read <> readArb.io.out
readArb.io.out.ready := !tl_out.d.valid || tl_out.d.ready // insert bubble if refill gets blocked
tl_out.e <> mshrs.io.mem_finish
// writebacks
val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))
wbArb.io.in(0) <> prober.io.wb_req
wbArb.io.in(1) <> mshrs.io.wb_req
wb.io.req <> wbArb.io.out
metaReadArb.io.in(3) <> wb.io.meta_read
readArb.io.in(2) <> wb.io.data_req
wb.io.data_resp := s2_data_corrected
TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)
// store->load bypassing
val s4_valid = RegNext(s3_valid, false.B)
val s4_req = RegEnable(s3_req, s3_valid && metaReadArb.io.out.valid)
val bypasses = List(
((s2_valid_masked || s2_replay) && !s2_sc_fail, s2_req, amoalu.io.out),
(s3_valid, s3_req, s3_req.data),
(s4_valid, s4_req, s4_req.data)
).map(r => (r._1 && (s1_addr >> wordOffBits === r._2.addr >> wordOffBits) && isWrite(r._2.cmd), r._3))
val s2_store_bypass_data = Reg(Bits(coreDataBits.W))
val s2_store_bypass = Reg(Bool())
when (s1_clk_en) {
s2_store_bypass := false.B
when (bypasses.map(_._1).reduce(_||_)) {
s2_store_bypass_data := PriorityMux(bypasses)
s2_store_bypass := true.B
}
}
// load data subword mux/sign extension
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, 0.U(log2Up(coreDataBits).W))
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word, s2_sc, wordBytes)
amoalu.io.mask := new StoreGen(s2_req.size, s2_req.addr, 0.U, xLen/8).mask
amoalu.io.cmd := s2_req.cmd
amoalu.io.lhs := s2_data_word
amoalu.io.rhs := s2_req.data
// nack it like it's hot
val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || io.cpu.s2_nack || s1_tlb_req_valid ||
s1_req.addr(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready
val s2_nack_hit = RegEnable(s1_nack, s1_valid || s1_replay)
when (s2_nack_hit) { mshrs.io.req.valid := false.B }
val s2_nack_victim = s2_hit && mshrs.io.secondary_miss
val s2_nack_miss = !s2_hit && !mshrs.io.req.ready
val s2_nack = s2_nack_hit || s2_nack_victim || s2_nack_miss
s2_valid_masked := s2_valid && !s2_nack && !io.cpu.s2_kill
val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable
val s2_recycle_next = RegInit(false.B)
when (s1_valid || s1_replay) { s2_recycle_next := s2_recycle_ecc }
s2_recycle := s2_recycle_ecc || s2_recycle_next
// after a nack, block until nack condition resolves to save energy
val block_miss = RegInit(false.B)
block_miss := (s2_valid || block_miss) && s2_nack_miss
when (block_miss || s1_nack) {
io.cpu.req.ready := false.B
}
val cache_resp = Wire(Valid(new HellaCacheResp))
cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable
cache_resp.bits.addr := s2_req.addr
cache_resp.bits.idx.foreach(_ := s2_req.idx.get)
cache_resp.bits.tag := s2_req.tag
cache_resp.bits.cmd := s2_req.cmd
cache_resp.bits.size := s2_req.size
cache_resp.bits.signed := s2_req.signed
cache_resp.bits.dprv := s2_req.dprv
cache_resp.bits.dv := s2_req.dv
cache_resp.bits.data_word_bypass := loadgen.wordData
cache_resp.bits.data_raw := s2_data_word
cache_resp.bits.mask := s2_req.mask
cache_resp.bits.has_data := isRead(s2_req.cmd)
cache_resp.bits.data := loadgen.data | s2_sc_fail
cache_resp.bits.store_data := s2_req.data
cache_resp.bits.replay := s2_replay
val uncache_resp = Wire(Valid(new HellaCacheResp))
uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid
mshrs.io.resp.ready := RegNext(!(s1_valid || s1_replay))
io.cpu.s2_nack := s2_valid && s2_nack
io.cpu.resp := Mux(mshrs.io.resp.ready, uncache_resp, cache_resp)
io.cpu.resp.bits.data_word_bypass := loadgen.wordData
io.cpu.resp.bits.data_raw := s2_data_word
io.cpu.ordered := mshrs.io.fence_rdy && !s1_valid && !s2_valid
io.cpu.store_pending := mshrs.io.store_pending
io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
val s1_xcpt_valid = dtlb.io.req.valid && !s1_nack
val s1_xcpt = dtlb.io.resp
io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_clk_en), 0.U.asTypeOf(s1_xcpt))
io.cpu.s2_uncached := false.B
io.cpu.s2_paddr := s2_req.addr
// performance events
io.cpu.perf.acquire := edge.done(tl_out.a)
io.cpu.perf.release := edge.done(tl_out.c)
io.cpu.perf.tlbMiss := io.ptw.req.fire
// no clock-gating support
io.cpu.clock_enabled := true.B
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File AMOALU.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
}
| module IOMSHR( // @[NBDcache.scala:52:7]
input clock, // @[NBDcache.scala:52:7]
input reset, // @[NBDcache.scala:52:7]
output io_req_ready, // @[NBDcache.scala:53:14]
input io_req_valid, // @[NBDcache.scala:53:14]
input [39:0] io_req_bits_addr, // @[NBDcache.scala:53:14]
input [6:0] io_req_bits_tag, // @[NBDcache.scala:53:14]
input [4:0] io_req_bits_cmd, // @[NBDcache.scala:53:14]
input [1:0] io_req_bits_size, // @[NBDcache.scala:53:14]
input io_req_bits_signed, // @[NBDcache.scala:53:14]
input [1:0] io_req_bits_dprv, // @[NBDcache.scala:53:14]
input io_req_bits_dv, // @[NBDcache.scala:53:14]
input io_req_bits_phys, // @[NBDcache.scala:53:14]
input io_req_bits_no_resp, // @[NBDcache.scala:53:14]
input io_req_bits_no_alloc, // @[NBDcache.scala:53:14]
input io_req_bits_no_xcpt, // @[NBDcache.scala:53:14]
input [63:0] io_req_bits_data, // @[NBDcache.scala:53:14]
input [7:0] io_req_bits_mask, // @[NBDcache.scala:53:14]
input io_resp_ready, // @[NBDcache.scala:53:14]
output io_resp_valid, // @[NBDcache.scala:53:14]
output [39:0] io_resp_bits_addr, // @[NBDcache.scala:53:14]
output [6:0] io_resp_bits_tag, // @[NBDcache.scala:53:14]
output [4:0] io_resp_bits_cmd, // @[NBDcache.scala:53:14]
output [1:0] io_resp_bits_size, // @[NBDcache.scala:53:14]
output io_resp_bits_signed, // @[NBDcache.scala:53:14]
output [1:0] io_resp_bits_dprv, // @[NBDcache.scala:53:14]
output io_resp_bits_dv, // @[NBDcache.scala:53:14]
output [63:0] io_resp_bits_data, // @[NBDcache.scala:53:14]
output [7:0] io_resp_bits_mask, // @[NBDcache.scala:53:14]
output io_resp_bits_has_data, // @[NBDcache.scala:53:14]
output [63:0] io_resp_bits_data_word_bypass, // @[NBDcache.scala:53:14]
output [63:0] io_resp_bits_data_raw, // @[NBDcache.scala:53:14]
output [63:0] io_resp_bits_store_data, // @[NBDcache.scala:53:14]
input io_mem_access_ready, // @[NBDcache.scala:53:14]
output io_mem_access_valid, // @[NBDcache.scala:53:14]
output [2:0] io_mem_access_bits_opcode, // @[NBDcache.scala:53:14]
output [2:0] io_mem_access_bits_param, // @[NBDcache.scala:53:14]
output [3:0] io_mem_access_bits_size, // @[NBDcache.scala:53:14]
output [1:0] io_mem_access_bits_source, // @[NBDcache.scala:53:14]
output [31:0] io_mem_access_bits_address, // @[NBDcache.scala:53:14]
output [7:0] io_mem_access_bits_mask, // @[NBDcache.scala:53:14]
output [63:0] io_mem_access_bits_data, // @[NBDcache.scala:53:14]
input io_mem_ack_valid, // @[NBDcache.scala:53:14]
input [2:0] io_mem_ack_bits_opcode, // @[NBDcache.scala:53:14]
input [1:0] io_mem_ack_bits_param, // @[NBDcache.scala:53:14]
input [3:0] io_mem_ack_bits_size, // @[NBDcache.scala:53:14]
input [1:0] io_mem_ack_bits_source, // @[NBDcache.scala:53:14]
input [2:0] io_mem_ack_bits_sink, // @[NBDcache.scala:53:14]
input io_mem_ack_bits_denied, // @[NBDcache.scala:53:14]
input [63:0] io_mem_ack_bits_data, // @[NBDcache.scala:53:14]
input io_mem_ack_bits_corrupt, // @[NBDcache.scala:53:14]
output io_replay_next, // @[NBDcache.scala:53:14]
output io_store_pending // @[NBDcache.scala:53:14]
);
wire io_req_valid_0 = io_req_valid; // @[NBDcache.scala:52:7]
wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[NBDcache.scala:52:7]
wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[NBDcache.scala:52:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[NBDcache.scala:52:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[NBDcache.scala:52:7]
wire io_req_bits_signed_0 = io_req_bits_signed; // @[NBDcache.scala:52:7]
wire [1:0] io_req_bits_dprv_0 = io_req_bits_dprv; // @[NBDcache.scala:52:7]
wire io_req_bits_dv_0 = io_req_bits_dv; // @[NBDcache.scala:52:7]
wire io_req_bits_phys_0 = io_req_bits_phys; // @[NBDcache.scala:52:7]
wire io_req_bits_no_resp_0 = io_req_bits_no_resp; // @[NBDcache.scala:52:7]
wire io_req_bits_no_alloc_0 = io_req_bits_no_alloc; // @[NBDcache.scala:52:7]
wire io_req_bits_no_xcpt_0 = io_req_bits_no_xcpt; // @[NBDcache.scala:52:7]
wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[NBDcache.scala:52:7]
wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[NBDcache.scala:52:7]
wire io_resp_ready_0 = io_resp_ready; // @[NBDcache.scala:52:7]
wire io_mem_access_ready_0 = io_mem_access_ready; // @[NBDcache.scala:52:7]
wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[NBDcache.scala:52:7]
wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[NBDcache.scala:52:7]
wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[NBDcache.scala:52:7]
wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[NBDcache.scala:52:7]
wire [1:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[NBDcache.scala:52:7]
wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[NBDcache.scala:52:7]
wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[NBDcache.scala:52:7]
wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[NBDcache.scala:52:7]
wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[NBDcache.scala:52:7]
wire io_resp_bits_replay = 1'h1; // @[NBDcache.scala:52:7]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_access_bits_corrupt = 1'h0; // @[NBDcache.scala:52:7]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29]
wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _atomics_WIRE_corrupt = 1'h0; // @[NBDcache.scala:86:38]
wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_3_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_5_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_7_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_9_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_11_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_13_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _atomics_T_15_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire atomics_corrupt = 1'h0; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[NBDcache.scala:104:57]
wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[NBDcache.scala:104:28]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire [6:0] grant_word_shift = 7'h0; // @[NBDcache.scala:65:20]
wire [1:0] get_source = 2'h2; // @[Edges.scala:460:17]
wire [1:0] put_source = 2'h2; // @[Edges.scala:480:17]
wire [1:0] atomics_a_source = 2'h2; // @[Edges.scala:534:17]
wire [1:0] atomics_a_1_source = 2'h2; // @[Edges.scala:534:17]
wire [1:0] atomics_a_2_source = 2'h2; // @[Edges.scala:534:17]
wire [1:0] atomics_a_3_source = 2'h2; // @[Edges.scala:534:17]
wire [1:0] atomics_a_4_source = 2'h2; // @[Edges.scala:517:17]
wire [1:0] atomics_a_5_source = 2'h2; // @[Edges.scala:517:17]
wire [1:0] atomics_a_6_source = 2'h2; // @[Edges.scala:517:17]
wire [1:0] atomics_a_7_source = 2'h2; // @[Edges.scala:517:17]
wire [1:0] atomics_a_8_source = 2'h2; // @[Edges.scala:517:17]
wire [1:0] _io_mem_access_bits_T_42_source = 2'h2; // @[NBDcache.scala:104:57]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[NBDcache.scala:86:38]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[NBDcache.scala:86:38]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[NBDcache.scala:104:57]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[NBDcache.scala:86:38]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[NBDcache.scala:86:38]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[NBDcache.scala:86:38]
wire [1:0] _atomics_WIRE_source = 2'h0; // @[NBDcache.scala:86:38]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[NBDcache.scala:86:38]
wire _io_req_ready_T; // @[NBDcache.scala:74:26]
wire _io_resp_valid_T; // @[NBDcache.scala:107:26]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_resp_bits_has_data_T_24; // @[Consts.scala:89:68]
wire [63:0] _io_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16]
wire _io_mem_access_valid_T; // @[NBDcache.scala:103:33]
wire [2:0] _io_mem_access_bits_T_43_opcode; // @[NBDcache.scala:104:28]
wire [2:0] _io_mem_access_bits_T_43_param; // @[NBDcache.scala:104:28]
wire [3:0] _io_mem_access_bits_T_43_size; // @[NBDcache.scala:104:28]
wire [1:0] _io_mem_access_bits_T_43_source; // @[NBDcache.scala:104:28]
wire [31:0] _io_mem_access_bits_T_43_address; // @[NBDcache.scala:104:28]
wire [7:0] _io_mem_access_bits_T_43_mask; // @[NBDcache.scala:104:28]
wire [63:0] _io_mem_access_bits_T_43_data; // @[NBDcache.scala:104:28]
wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[NBDcache.scala:52:7, :66:10]
wire _io_replay_next_T_4; // @[NBDcache.scala:106:40]
wire _io_store_pending_T_24; // @[NBDcache.scala:123:40]
wire io_req_ready_0; // @[NBDcache.scala:52:7]
wire [39:0] io_resp_bits_addr_0; // @[NBDcache.scala:52:7]
wire [6:0] io_resp_bits_tag_0; // @[NBDcache.scala:52:7]
wire [4:0] io_resp_bits_cmd_0; // @[NBDcache.scala:52:7]
wire [1:0] io_resp_bits_size_0; // @[NBDcache.scala:52:7]
wire io_resp_bits_signed_0; // @[NBDcache.scala:52:7]
wire [1:0] io_resp_bits_dprv_0; // @[NBDcache.scala:52:7]
wire io_resp_bits_dv_0; // @[NBDcache.scala:52:7]
wire [63:0] io_resp_bits_data_0; // @[NBDcache.scala:52:7]
wire [7:0] io_resp_bits_mask_0; // @[NBDcache.scala:52:7]
wire io_resp_bits_has_data_0; // @[NBDcache.scala:52:7]
wire [63:0] io_resp_bits_data_word_bypass_0; // @[NBDcache.scala:52:7]
wire [63:0] io_resp_bits_data_raw_0; // @[NBDcache.scala:52:7]
wire [63:0] io_resp_bits_store_data_0; // @[NBDcache.scala:52:7]
wire io_resp_valid_0; // @[NBDcache.scala:52:7]
wire [2:0] io_mem_access_bits_opcode_0; // @[NBDcache.scala:52:7]
wire [2:0] io_mem_access_bits_param_0; // @[NBDcache.scala:52:7]
wire [3:0] io_mem_access_bits_size_0; // @[NBDcache.scala:52:7]
wire [1:0] io_mem_access_bits_source_0; // @[NBDcache.scala:52:7]
wire [31:0] io_mem_access_bits_address_0; // @[NBDcache.scala:52:7]
wire [7:0] io_mem_access_bits_mask_0; // @[NBDcache.scala:52:7]
wire [63:0] io_mem_access_bits_data_0; // @[NBDcache.scala:52:7]
wire io_mem_access_valid_0; // @[NBDcache.scala:52:7]
wire io_replay_next_0; // @[NBDcache.scala:52:7]
wire io_store_pending_0; // @[NBDcache.scala:52:7]
reg [39:0] req_addr; // @[NBDcache.scala:69:16]
assign io_resp_bits_addr_0 = req_addr; // @[NBDcache.scala:52:7, :69:16]
wire [39:0] _get_legal_T_14 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _put_legal_T_14 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_4 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_58 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_112 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_166 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_220 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_274 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_328 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_382 = req_addr; // @[NBDcache.scala:69:16]
wire [39:0] _atomics_legal_T_436 = req_addr; // @[NBDcache.scala:69:16]
reg [6:0] req_tag; // @[NBDcache.scala:69:16]
assign io_resp_bits_tag_0 = req_tag; // @[NBDcache.scala:52:7, :69:16]
reg [4:0] req_cmd; // @[NBDcache.scala:69:16]
assign io_resp_bits_cmd_0 = req_cmd; // @[NBDcache.scala:52:7, :69:16]
reg [1:0] req_size; // @[NBDcache.scala:69:16]
assign io_resp_bits_size_0 = req_size; // @[NBDcache.scala:52:7, :69:16]
wire [1:0] size = req_size; // @[NBDcache.scala:69:16]
reg req_signed; // @[NBDcache.scala:69:16]
assign io_resp_bits_signed_0 = req_signed; // @[NBDcache.scala:52:7, :69:16]
reg [1:0] req_dprv; // @[NBDcache.scala:69:16]
assign io_resp_bits_dprv_0 = req_dprv; // @[NBDcache.scala:52:7, :69:16]
reg req_dv; // @[NBDcache.scala:69:16]
assign io_resp_bits_dv_0 = req_dv; // @[NBDcache.scala:52:7, :69:16]
reg req_phys; // @[NBDcache.scala:69:16]
reg req_no_resp; // @[NBDcache.scala:69:16]
reg req_no_alloc; // @[NBDcache.scala:69:16]
reg req_no_xcpt; // @[NBDcache.scala:69:16]
reg [63:0] req_data; // @[NBDcache.scala:69:16]
assign io_resp_bits_store_data_0 = req_data; // @[NBDcache.scala:52:7, :69:16]
wire [63:0] put_data = req_data; // @[Edges.scala:480:17]
wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17]
reg [7:0] req_mask; // @[NBDcache.scala:69:16]
assign io_resp_bits_mask_0 = req_mask; // @[NBDcache.scala:52:7, :69:16]
reg [63:0] grant_word; // @[NBDcache.scala:70:23]
assign io_resp_bits_data_raw_0 = grant_word; // @[NBDcache.scala:52:7, :70:23]
reg [2:0] state; // @[NBDcache.scala:73:22]
assign _io_req_ready_T = ~(|state); // @[NBDcache.scala:73:22, :74:26]
assign io_req_ready_0 = _io_req_ready_T; // @[NBDcache.scala:52:7, :74:26]
wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31]
assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31]
assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31]
assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31]
assign _atomics_legal_T_47 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31]
assign _atomics_legal_T_101 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31]
assign _atomics_legal_T_155 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31]
assign _atomics_legal_T_209 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31]
assign _atomics_legal_T_263 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31]
assign _atomics_legal_T_317 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31]
assign _atomics_legal_T_371 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31]
assign _atomics_legal_T_425 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31]
assign _atomics_legal_T_479 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31]
assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46]
wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31]
assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31]
assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31]
assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31]
assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31]
assign _atomics_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31]
assign _atomics_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31]
assign _atomics_legal_T_73 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31]
assign _atomics_legal_T_78 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31]
assign _atomics_legal_T_127 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31]
assign _atomics_legal_T_132 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31]
assign _atomics_legal_T_181 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31]
assign _atomics_legal_T_186 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31]
assign _atomics_legal_T_235 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31]
assign _atomics_legal_T_240 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31]
assign _atomics_legal_T_289 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31]
assign _atomics_legal_T_294 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31]
assign _atomics_legal_T_343 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31]
assign _atomics_legal_T_348 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31]
assign _atomics_legal_T_397 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31]
assign _atomics_legal_T_402 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31]
assign _atomics_legal_T_451 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31]
assign _atomics_legal_T_456 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46]
wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46]
wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31]
assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31]
assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31]
assign _atomics_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31]
assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31]
assign _atomics_legal_T_137 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31]
assign _atomics_legal_T_191 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31]
assign _atomics_legal_T_245 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31]
assign _atomics_legal_T_299 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31]
assign _atomics_legal_T_353 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31]
assign _atomics_legal_T_407 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31]
assign _atomics_legal_T_461 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46]
wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[NBDcache.scala:69:16]
wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31]
assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31]
assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31]
assign _atomics_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31]
assign _atomics_legal_T_88 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31]
assign _atomics_legal_T_142 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31]
assign _atomics_legal_T_196 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31]
assign _atomics_legal_T_250 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31]
assign _atomics_legal_T_304 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31]
assign _atomics_legal_T_358 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31]
assign _atomics_legal_T_412 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31]
assign _atomics_legal_T_466 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46]
wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42]
wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42]
wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42]
wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42]
wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42]
wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_5 = {2'h0, req_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_6 = {1'h0, req_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &req_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_word_bypass_shifted_T = req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[NBDcache.scala:69:16]
wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31]
assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31]
assign _atomics_legal_T_63 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31]
assign _atomics_legal_T_117 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31]
assign _atomics_legal_T_171 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31]
assign _atomics_legal_T_225 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31]
assign _atomics_legal_T_279 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31]
assign _atomics_legal_T_333 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31]
assign _atomics_legal_T_387 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31]
assign _atomics_legal_T_441 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[NBDcache.scala:69:16]
wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31]
assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31]
assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31]
assign _atomics_legal_T_68 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31]
assign _atomics_legal_T_122 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31]
assign _atomics_legal_T_176 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31]
assign _atomics_legal_T_230 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31]
assign _atomics_legal_T_284 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31]
assign _atomics_legal_T_338 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31]
assign _atomics_legal_T_392 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31]
assign _atomics_legal_T_446 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46]
wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46]
wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46]
wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46]
wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46]
wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42]
wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42]
wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42]
wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42]
wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42]
wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46]
wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &req_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46]
wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46]
wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46]
wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46]
wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46]
wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46]
wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46]
wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_39 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42]
wire _atomics_legal_T_40 = _atomics_legal_T_39 | _atomics_legal_T_18; // @[Parameters.scala:685:42]
wire _atomics_legal_T_41 = _atomics_legal_T_40 | _atomics_legal_T_23; // @[Parameters.scala:685:42]
wire _atomics_legal_T_42 = _atomics_legal_T_41 | _atomics_legal_T_28; // @[Parameters.scala:685:42]
wire _atomics_legal_T_43 = _atomics_legal_T_42 | _atomics_legal_T_33; // @[Parameters.scala:685:42]
wire _atomics_legal_T_44 = _atomics_legal_T_43 | _atomics_legal_T_38; // @[Parameters.scala:685:42]
wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46]
wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46]
wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46]
wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46]
wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46]
wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46]
wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46]
wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46]
wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_93 = _atomics_legal_T_62 | _atomics_legal_T_67; // @[Parameters.scala:685:42]
wire _atomics_legal_T_94 = _atomics_legal_T_93 | _atomics_legal_T_72; // @[Parameters.scala:685:42]
wire _atomics_legal_T_95 = _atomics_legal_T_94 | _atomics_legal_T_77; // @[Parameters.scala:685:42]
wire _atomics_legal_T_96 = _atomics_legal_T_95 | _atomics_legal_T_82; // @[Parameters.scala:685:42]
wire _atomics_legal_T_97 = _atomics_legal_T_96 | _atomics_legal_T_87; // @[Parameters.scala:685:42]
wire _atomics_legal_T_98 = _atomics_legal_T_97 | _atomics_legal_T_92; // @[Parameters.scala:685:42]
wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46]
wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46]
wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46]
wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46]
wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46]
wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46]
wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46]
wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46]
wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_147 = _atomics_legal_T_116 | _atomics_legal_T_121; // @[Parameters.scala:685:42]
wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_126; // @[Parameters.scala:685:42]
wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_131; // @[Parameters.scala:685:42]
wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_136; // @[Parameters.scala:685:42]
wire _atomics_legal_T_151 = _atomics_legal_T_150 | _atomics_legal_T_141; // @[Parameters.scala:685:42]
wire _atomics_legal_T_152 = _atomics_legal_T_151 | _atomics_legal_T_146; // @[Parameters.scala:685:42]
wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46]
wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46]
wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46]
wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46]
wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46]
wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46]
wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46]
wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46]
wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_201 = _atomics_legal_T_170 | _atomics_legal_T_175; // @[Parameters.scala:685:42]
wire _atomics_legal_T_202 = _atomics_legal_T_201 | _atomics_legal_T_180; // @[Parameters.scala:685:42]
wire _atomics_legal_T_203 = _atomics_legal_T_202 | _atomics_legal_T_185; // @[Parameters.scala:685:42]
wire _atomics_legal_T_204 = _atomics_legal_T_203 | _atomics_legal_T_190; // @[Parameters.scala:685:42]
wire _atomics_legal_T_205 = _atomics_legal_T_204 | _atomics_legal_T_195; // @[Parameters.scala:685:42]
wire _atomics_legal_T_206 = _atomics_legal_T_205 | _atomics_legal_T_200; // @[Parameters.scala:685:42]
wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46]
wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46]
wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46]
wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46]
wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46]
wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46]
wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46]
wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46]
wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_255 = _atomics_legal_T_224 | _atomics_legal_T_229; // @[Parameters.scala:685:42]
wire _atomics_legal_T_256 = _atomics_legal_T_255 | _atomics_legal_T_234; // @[Parameters.scala:685:42]
wire _atomics_legal_T_257 = _atomics_legal_T_256 | _atomics_legal_T_239; // @[Parameters.scala:685:42]
wire _atomics_legal_T_258 = _atomics_legal_T_257 | _atomics_legal_T_244; // @[Parameters.scala:685:42]
wire _atomics_legal_T_259 = _atomics_legal_T_258 | _atomics_legal_T_249; // @[Parameters.scala:685:42]
wire _atomics_legal_T_260 = _atomics_legal_T_259 | _atomics_legal_T_254; // @[Parameters.scala:685:42]
wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46]
wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46]
wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46]
wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46]
wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46]
wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46]
wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46]
wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46]
wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_309 = _atomics_legal_T_278 | _atomics_legal_T_283; // @[Parameters.scala:685:42]
wire _atomics_legal_T_310 = _atomics_legal_T_309 | _atomics_legal_T_288; // @[Parameters.scala:685:42]
wire _atomics_legal_T_311 = _atomics_legal_T_310 | _atomics_legal_T_293; // @[Parameters.scala:685:42]
wire _atomics_legal_T_312 = _atomics_legal_T_311 | _atomics_legal_T_298; // @[Parameters.scala:685:42]
wire _atomics_legal_T_313 = _atomics_legal_T_312 | _atomics_legal_T_303; // @[Parameters.scala:685:42]
wire _atomics_legal_T_314 = _atomics_legal_T_313 | _atomics_legal_T_308; // @[Parameters.scala:685:42]
wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46]
wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46]
wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46]
wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46]
wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46]
wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46]
wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46]
wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46]
wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_363 = _atomics_legal_T_332 | _atomics_legal_T_337; // @[Parameters.scala:685:42]
wire _atomics_legal_T_364 = _atomics_legal_T_363 | _atomics_legal_T_342; // @[Parameters.scala:685:42]
wire _atomics_legal_T_365 = _atomics_legal_T_364 | _atomics_legal_T_347; // @[Parameters.scala:685:42]
wire _atomics_legal_T_366 = _atomics_legal_T_365 | _atomics_legal_T_352; // @[Parameters.scala:685:42]
wire _atomics_legal_T_367 = _atomics_legal_T_366 | _atomics_legal_T_357; // @[Parameters.scala:685:42]
wire _atomics_legal_T_368 = _atomics_legal_T_367 | _atomics_legal_T_362; // @[Parameters.scala:685:42]
wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46]
wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46]
wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46]
wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46]
wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46]
wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46]
wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46]
wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46]
wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_417 = _atomics_legal_T_386 | _atomics_legal_T_391; // @[Parameters.scala:685:42]
wire _atomics_legal_T_418 = _atomics_legal_T_417 | _atomics_legal_T_396; // @[Parameters.scala:685:42]
wire _atomics_legal_T_419 = _atomics_legal_T_418 | _atomics_legal_T_401; // @[Parameters.scala:685:42]
wire _atomics_legal_T_420 = _atomics_legal_T_419 | _atomics_legal_T_406; // @[Parameters.scala:685:42]
wire _atomics_legal_T_421 = _atomics_legal_T_420 | _atomics_legal_T_411; // @[Parameters.scala:685:42]
wire _atomics_legal_T_422 = _atomics_legal_T_421 | _atomics_legal_T_416; // @[Parameters.scala:685:42]
wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46]
wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46]
wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46]
wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46]
wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46]
wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46]
wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46]
wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46]
wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_471 = _atomics_legal_T_440 | _atomics_legal_T_445; // @[Parameters.scala:685:42]
wire _atomics_legal_T_472 = _atomics_legal_T_471 | _atomics_legal_T_450; // @[Parameters.scala:685:42]
wire _atomics_legal_T_473 = _atomics_legal_T_472 | _atomics_legal_T_455; // @[Parameters.scala:685:42]
wire _atomics_legal_T_474 = _atomics_legal_T_473 | _atomics_legal_T_460; // @[Parameters.scala:685:42]
wire _atomics_legal_T_475 = _atomics_legal_T_474 | _atomics_legal_T_465; // @[Parameters.scala:685:42]
wire _atomics_legal_T_476 = _atomics_legal_T_475 | _atomics_legal_T_470; // @[Parameters.scala:685:42]
wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46]
wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire _T_17 = req_cmd == 5'h4; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T; // @[NBDcache.scala:86:67]
assign _atomics_T = _T_17; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T; // @[package.scala:16:47]
assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47]
wire _io_mem_access_bits_T_24; // @[package.scala:16:47]
assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_7; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_7 = _T_17; // @[package.scala:16:47]
wire _io_store_pending_T_6; // @[package.scala:16:47]
assign _io_store_pending_T_6 = _T_17; // @[package.scala:16:47]
wire _state_T_7; // @[package.scala:16:47]
assign _state_T_7 = _T_17; // @[package.scala:16:47]
wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_1_opcode; // @[NBDcache.scala:86:67]
assign _atomics_T_1_opcode = _GEN_9; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_1_param; // @[NBDcache.scala:86:67]
assign _atomics_T_1_param = _GEN_9; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_1_source = {_atomics_T, 1'h0}; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire _T_18 = req_cmd == 5'h9; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_2; // @[NBDcache.scala:86:67]
assign _atomics_T_2 = _T_18; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_1; // @[package.scala:16:47]
assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47]
wire _io_mem_access_bits_T_25; // @[package.scala:16:47]
assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_8; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_8 = _T_18; // @[package.scala:16:47]
wire _io_store_pending_T_7; // @[package.scala:16:47]
assign _io_store_pending_T_7 = _T_18; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _T_18; // @[package.scala:16:47]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_3_source = _atomics_T_2 ? 2'h2 : _atomics_T_1_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire _T_19 = req_cmd == 5'hA; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_4; // @[NBDcache.scala:86:67]
assign _atomics_T_4 = _T_19; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_2; // @[package.scala:16:47]
assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47]
wire _io_mem_access_bits_T_26; // @[package.scala:16:47]
assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_9; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_9 = _T_19; // @[package.scala:16:47]
wire _io_store_pending_T_8; // @[package.scala:16:47]
assign _io_store_pending_T_8 = _T_19; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _T_19; // @[package.scala:16:47]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_5_source = _atomics_T_4 ? 2'h2 : _atomics_T_3_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire _T_20 = req_cmd == 5'hB; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_6; // @[NBDcache.scala:86:67]
assign _atomics_T_6 = _T_20; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_3; // @[package.scala:16:47]
assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47]
wire _io_mem_access_bits_T_27; // @[package.scala:16:47]
assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_10; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_10 = _T_20; // @[package.scala:16:47]
wire _io_store_pending_T_9; // @[package.scala:16:47]
assign _io_store_pending_T_9 = _T_20; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _T_20; // @[package.scala:16:47]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_7_source = _atomics_T_6 ? 2'h2 : _atomics_T_5_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire _T_24 = req_cmd == 5'h8; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_8; // @[NBDcache.scala:86:67]
assign _atomics_T_8 = _T_24; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_7; // @[package.scala:16:47]
assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47]
wire _io_mem_access_bits_T_31; // @[package.scala:16:47]
assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_14; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_14 = _T_24; // @[package.scala:16:47]
wire _io_store_pending_T_13; // @[package.scala:16:47]
assign _io_store_pending_T_13 = _T_24; // @[package.scala:16:47]
wire _state_T_14; // @[package.scala:16:47]
assign _state_T_14 = _T_24; // @[package.scala:16:47]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_9_source = _atomics_T_8 ? 2'h2 : _atomics_T_7_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire _T_25 = req_cmd == 5'hC; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_10; // @[NBDcache.scala:86:67]
assign _atomics_T_10 = _T_25; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_8; // @[package.scala:16:47]
assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47]
wire _io_mem_access_bits_T_32; // @[package.scala:16:47]
assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_15; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_15 = _T_25; // @[package.scala:16:47]
wire _io_store_pending_T_14; // @[package.scala:16:47]
assign _io_store_pending_T_14 = _T_25; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _T_25; // @[package.scala:16:47]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_11_source = _atomics_T_10 ? 2'h2 : _atomics_T_9_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire _T_26 = req_cmd == 5'hD; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_12; // @[NBDcache.scala:86:67]
assign _atomics_T_12 = _T_26; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_9; // @[package.scala:16:47]
assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47]
wire _io_mem_access_bits_T_33; // @[package.scala:16:47]
assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_16; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_16 = _T_26; // @[package.scala:16:47]
wire _io_store_pending_T_15; // @[package.scala:16:47]
assign _io_store_pending_T_15 = _T_26; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _T_26; // @[package.scala:16:47]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_13_source = _atomics_T_12 ? 2'h2 : _atomics_T_11_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire _T_27 = req_cmd == 5'hE; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_14; // @[NBDcache.scala:86:67]
assign _atomics_T_14 = _T_27; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_10; // @[package.scala:16:47]
assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47]
wire _io_mem_access_bits_T_34; // @[package.scala:16:47]
assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_17; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_17 = _T_27; // @[package.scala:16:47]
wire _io_store_pending_T_16; // @[package.scala:16:47]
assign _io_store_pending_T_16 = _T_27; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _T_27; // @[package.scala:16:47]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[NBDcache.scala:86:67]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[NBDcache.scala:86:67]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_15_source = _atomics_T_14 ? 2'h2 : _atomics_T_13_source; // @[NBDcache.scala:86:67]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire _T_28 = req_cmd == 5'hF; // @[NBDcache.scala:69:16, :86:67]
wire _atomics_T_16; // @[NBDcache.scala:86:67]
assign _atomics_T_16 = _T_28; // @[NBDcache.scala:86:67]
wire _io_mem_access_bits_T_11; // @[package.scala:16:47]
assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47]
wire _io_mem_access_bits_T_35; // @[package.scala:16:47]
assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47]
wire _io_resp_bits_has_data_T_18; // @[package.scala:16:47]
assign _io_resp_bits_has_data_T_18 = _T_28; // @[package.scala:16:47]
wire _io_store_pending_T_17; // @[package.scala:16:47]
assign _io_store_pending_T_17 = _T_28; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _T_28; // @[package.scala:16:47]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[NBDcache.scala:86:67]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[NBDcache.scala:86:67]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire [1:0] atomics_source = _atomics_T_16 ? 2'h2 : _atomics_T_15_source; // @[NBDcache.scala:86:67]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLWidthWidget4( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [7:0] _anonOut_a_bits_mask_T_5 = 8'hFF; // @[WidthWidget.scala:85:119]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [5:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [5:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] anonOut_a_bits_mask_odata_0 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47]
wire [3:0] anonOut_a_bits_mask_odata_1 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47]
wire [31:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire [31:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47]
wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
wire [5:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
wire cated_bits_sink; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
wire cated_bits_denied; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [17:0] _limit_T = 18'h7 << anonIn_a_bits_size; // @[package.scala:243:71]
wire [2:0] _limit_T_1 = _limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire limit = _limit_T_2[2]; // @[package.scala:243:46]
reg count; // @[WidthWidget.scala:40:27]
wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = ~count; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56]
wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonIn_a_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35]
wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35]
assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24]
wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24]
wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29]
reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [31:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire [31:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [31:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35]
assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12]
wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_size > 4'h2; // @[Misc.scala:206:21]
wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26]
wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20]
wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10]
reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [3:0] anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24]
wire [3:0] anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 ? anonOut_a_bits_mask_odata_0 : anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [3:0] anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 ? anonOut_a_bits_mask_odata_1 : anonIn_a_bits_mask; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [7:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 8'hFF; // @[WidthWidget.scala:73:12, :85:93]
assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10]
assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25]
assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [63:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [31:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[63:32]; // @[Repeater.scala:36:26]
wire [31:0] _cated_bits_data_T_1 = anonOut_d_bits_data[31:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25]
wire [17:0] _repeat_limit_T = 18'h7 << cated_bits_size; // @[package.scala:243:71]
wire [2:0] _repeat_limit_T_1 = _repeat_limit_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire repeat_limit = _repeat_limit_T_2[2]; // @[package.scala:243:46]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24]
wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24]
reg repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_1; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_2; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_3; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_4; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_5; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_6; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_7; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_8; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_9; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_10; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_11; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_12; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_13; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_14; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_15; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_16; // @[WidthWidget.scala:187:27]
reg repeat_sel_sel_sources_32; // @[WidthWidget.scala:187:27]
wire repeat_sel_sel_a_sel = anonIn_a_bits_address[2]; // @[WidthWidget.scala:188:38]
wire _repeat_sel_sel_bypass_T = anonIn_a_bits_source == cated_bits_source; // @[WidthWidget.scala:161:25, :200:53]
wire repeat_sel_sel_bypass = anonIn_a_valid & _repeat_sel_sel_bypass_T; // @[WidthWidget.scala:200:{33,53}]
reg repeat_sel_hold_r; // @[WidthWidget.scala:121:47]
wire [63:0] _GEN = {{repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_32}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {1'h0}, {repeat_sel_sel_sources_16}, {repeat_sel_sel_sources_15}, {repeat_sel_sel_sources_14}, {repeat_sel_sel_sources_13}, {repeat_sel_sel_sources_12}, {repeat_sel_sel_sources_11}, {repeat_sel_sel_sources_10}, {repeat_sel_sel_sources_9}, {repeat_sel_sel_sources_8}, {repeat_sel_sel_sources_7}, {repeat_sel_sel_sources_6}, {repeat_sel_sel_sources_5}, {repeat_sel_sel_sources_4}, {repeat_sel_sel_sources_3}, {repeat_sel_sel_sources_2}, {repeat_sel_sel_sources_1}, {repeat_sel_sel_sources_0}}; // @[WidthWidget.scala:121:47, :187:27]
wire repeat_sel_hold = repeat_first ? _GEN[cated_bits_source] : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :161:25]
wire _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18]
wire repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}]
wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24]
wire [31:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[31:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [31:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[63:32]; // @[WidthWidget.scala:128:55, :161:25]
wire [31:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonIn_d_bits_data = repeat_index ? repeat_anonIn_d_bits_data_mux_1 : repeat_anonIn_d_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
count <= 1'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
repeat_count <= 1'h0; // @[WidthWidget.scala:105:26]
end
else begin // @[WidthWidget.scala:27:9]
if (_T) begin // @[Decoupled.scala:51:35]
count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
end
if (_anonOut_a_bits_data_T_2) // @[WidthWidget.scala:69:23]
anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
if (_anonOut_a_bits_mask_T_3) // @[WidthWidget.scala:69:23]
anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h0) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h1) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_1 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h2) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_2 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h3) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_3 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h4) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_4 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h5) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_5 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h6) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_6 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h7) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_7 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h8) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_8 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h9) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_9 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hA) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_10 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hB) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_11 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hC) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_12 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hD) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_13 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hE) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_14 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'hF) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_15 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h10) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_16 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (_repeat_sel_sel_T & anonIn_a_bits_source == 6'h20) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_32 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38]
if (repeat_first) // @[WidthWidget.scala:106:25]
repeat_sel_hold_r <= _GEN[cated_bits_source]; // @[WidthWidget.scala:121:47, :161:25]
always @(posedge)
TLMonitor_2 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleD_a32d64s6k1z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonOut_d_ready),
.io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (anonOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_sink (cated_bits_sink),
.io_deq_bits_denied (cated_bits_denied),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1332 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1332; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1332; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1405 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1405; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1405; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1405; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1258 = _T_1332 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1258 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1258 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1258 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1258 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1258 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1304 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1304 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1273 = _T_1405 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1273 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1273 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1273 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1376 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1376 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1358 = _T_1405 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1358 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1358 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1358 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File AtomicAutomata.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.util.leftOR
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operations.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
val node = TLAdapterNode(
managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
m.v1copy(
supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical),
mayDenyGet = m.mayDenyGet || m.mayDenyPut)
})})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes
// To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, beatBytes)
val managersNeedingHelp = managers.filter { m =>
m.supportsPutFull.contains(ourSupport) &&
m.supportsGet.contains(ourSupport) &&
((logical && !m.supportsLogical .contains(ourSupport)) ||
(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
!passthrough) // we will do atomics for everyone we can
}
// Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph.
// (But they must also ensure no sideband operations can get between the read and write.)
val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) }
require(violations.isEmpty,
s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," +
"but the following violations were found:\n" +
violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n"))
// We cannot add atomics to a non-FIFO manager
managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
// We need to preserve FIFO semantics across FIFO domains, not managers
// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
// Don't overprovision the CAM
val camSize = min(domainsNeedingHelp.size, concurrency)
// Compact the fifoIds to only those we care about
def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)
// CAM entry state machine
val FREE = 0.U // unused waiting on Atomic from A
val GET = 3.U // Get sent down A waiting on AccessDataAck from D
val AMO = 2.U // AccessDataAck sent up D waiting for A availability
val ACK = 1.U // Put sent down A waiting for PutAck from D
val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size)
// Do we need to do anything at all?
if (camSize > 0) {
val initval = Wire(new TLAtomicAutomata.CAM_S(params))
initval.state := FREE
val cam_s = RegInit(VecInit.fill(camSize)(initval))
val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params)))
val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params)))
val cam_free = cam_s.map(_.state === FREE)
val cam_amo = cam_s.map(_.state === AMO)
val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries
// Can the manager already handle this message?
val a_address = edgeIn.address(in.a.bits)
val a_size = edgeIn.size(in.a.bits)
val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size)
val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size)
val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B))
// Must we do a Put?
val a_cam_any_put = cam_amo.reduce(_ || _)
val a_cam_por_put = cam_amo.scanLeft(false.B)(_||_).init
val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
val a_cam_a = PriorityMux(cam_amo, cam_a)
val a_cam_d = PriorityMux(cam_amo, cam_d)
val a_a = a_cam_a.bits.data
val a_d = a_cam_d.data
// Does the A request conflict with an inflight AMO?
val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U)
val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
// (Where) are we are allocating in the CAM?
val a_cam_any_free = cam_free.reduce(_ || _)
val a_cam_por_free = cam_free.scanLeft(false.B)(_||_).init
val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
// Logical AMO
val indexes = Seq.tabulate(beatBytes*8) { i => Cat(a_a(i,i), a_d(i,i)) }
val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse)
// Arithmetic AMO
val unsigned = a_cam_a.bits.param(1)
val take_max = a_cam_a.bits.param(0)
val adder = a_cam_a.bits.param(2)
val mask = a_cam_a.bits.mask
val signSel = ~(~mask | (mask >> 1))
val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8*i+7,8*i+7) } .reverse)
val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8*i+7,8*i+7) } .reverse)
// Move the selected sign bit into the first byte position it will extend
val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0)
val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0)
val signext_a = FillInterleaved(8, leftOR(signbit_a))
val signext_d = FillInterleaved(8, leftOR(signbit_d))
// NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic
val wide_mask = FillInterleaved(8, mask)
val a_a_ext = (a_a & wide_mask) | signext_a
val a_d_ext = (a_d & wide_mask) | signext_d
val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext)
val adder_out = a_a_ext + a_d_inv
val h = 8*beatBytes-1 // now sign-extended; use biggest bit
val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal
val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq)
val pick_a = take_max === a_bigger
val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d))
// AMO result data
val amo_data =
if (!logical) arith_out else
if (!arithmetic) logic_out else
Mux(a_cam_a.bits.opcode(0), logic_out, arith_out)
// Potentially mutate the message from inner
val source_i = Wire(chiselTypeOf(in.a))
val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
in.a.ready := source_i.ready && a_allow
source_i.valid := in.a.valid && a_allow
source_i.bits := in.a.bits
when (!a_isSupported) { // minimal mux difference
source_i.bits.opcode := TLMessages.Get
source_i.bits.param := 0.U
}
// Potentially take the message from the CAM
val source_c = Wire(chiselTypeOf(in.a))
source_c.valid := a_cam_any_put
source_c.bits := edgeOut.Put(
fromSource = a_cam_a.bits.source,
toAddress = edgeIn.address(a_cam_a.bits),
lgSize = a_cam_a.bits.size,
data = amo_data,
corrupt = a_cam_a.bits.corrupt || a_cam_d.corrupt)._2
source_c.bits.user :<= a_cam_a.bits.user
source_c.bits.echo :<= a_cam_a.bits.echo
// Finishing an AMO from the CAM has highest priority
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i))
// Capture the A state into the CAM
when (source_i.fire && !a_isSupported) {
(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
when (en) {
r.fifoId := a_fifoId
r.bits := in.a.bits
r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
TLAtomics.AND -> 0x8.U,
TLAtomics.OR -> 0xe.U,
TLAtomics.XOR -> 0x6.U,
TLAtomics.SWAP -> 0xc.U))
}
}
(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := GET
}
}
}
// Advance the put state
when (source_c.fire) {
(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
when (en) {
r.state := ACK
}
}
}
// We need to deal with a potential D response in the same cycle as the A request
val d_first = edgeOut.first(out.d)
val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied))
val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt))
val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else
out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported
val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
val d_ack = out.d.bits.opcode === TLMessages.AccessAck
when (out.d.fire && d_first) {
(d_cam_sel zip cam_d) foreach { case (en, r) =>
when (en && d_ackd) {
r.data := out.d.bits.data
r.denied := out.d.bits.denied
r.corrupt := out.d.bits.corrupt
}
}
(d_cam_sel zip cam_s) foreach { case (en, r) =>
when (en) {
// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
r.state := Mux(d_ackd, AMO, FREE)
}
}
}
val d_drop = d_first && d_ackd && d_cam_sel_any
val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ || _)
in.d.valid := out.d.valid && !d_drop
out.d.ready := in.d.ready || d_drop
in.d.bits := out.d.bits
when (d_replace) { // minimal muxes
in.d.bits.opcode := TLMessages.AccessAckData
in.d.bits.data := d_cam_data
in.d.bits.corrupt := d_cam_corrupt || out.d.bits.denied
in.d.bits.denied := d_cam_denied || out.d.bits.denied
}
} else {
out.a.valid := in.a.valid
in.a.ready := out.a.ready
out.a.bits := in.a.bits
in.d.valid := out.d.valid
out.d.ready := in.d.ready
in.d.bits := out.d.bits
}
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
in.b.valid := out.b.valid
out.b.ready := in.b.ready
in.b.bits := out.b.bits
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAtomicAutomata
{
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) {
override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_")
})
atomics.node
}
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
class CAM_S(val params: CAMParams) extends Bundle {
val state = UInt(2.W)
}
class CAM_A(val params: CAMParams) extends Bundle {
val bits = new TLBundleA(params.a)
val fifoId = UInt(log2Up(params.domainsNeedingHelp).W)
val lut = UInt(4.W)
}
class CAM_D(val params: CAMParams) extends Bundle {
val data = UInt(params.a.dataBits.W)
val denied = Bool()
val corrupt = Bool()
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
// Confirm that the AtomicAutomata combines read + write errors
import TLMessages._
val test = new RequestPattern({a: TLBundleA =>
val doesA = a.opcode === ArithmeticData || a.opcode === LogicalData
val doesR = a.opcode === Get || doesA
val doesW = a.opcode === PutFullData || a.opcode === PutPartialData || doesA
(doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) ||
(doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a))
})
(ram.node
:= TLErrorEvaluator(test)
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= TLErrorEvaluator(test, testOn=true, testOff=true)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File RegField.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.util.{DecoupledIO, ReadyValidIO}
import org.json4s.JsonDSL._
import org.json4s.JsonAST.JValue
import freechips.rocketchip.util.{SimpleRegIO}
case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
object RegReadFn
{
// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
// iready may combinationally depend on oready
// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
// effects must become visible on the cycle after ovalid && oready
// data is only inspected when ovalid && oready
implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
new RegReadFn(false, x)
implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
RegReadFn((ivalid, oready) => {
x.request.valid := ivalid
x.response.ready := oready
(x.request.ready, x.response.valid, x.response.bits)
})
// (ready: Bool) => (valid: Bool, data: UInt)
// valid must not combinationally depend on ready
// effects must become visible on the cycle after valid && ready
implicit def apply(x: Bool => (Bool, UInt)) =
new RegReadFn(true, { case (_, oready) =>
val (ovalid, data) = x(oready)
(true.B, ovalid, data)
})
// read from a ReadyValidIO (only safe if there is a consistent source of data)
implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) })
// read from a register
implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (true.B, x))
// noop
implicit def apply(x: Unit):RegReadFn = RegReadFn(0.U)
}
case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
object RegWriteFn
{
// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
// iready may combinationally depend on both oready and data
// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
// effects must become visible on the cycle after ovalid && oready
// data should only be used for an effect when ivalid && iready
implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
new RegWriteFn(false, x)
implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
RegWriteFn((ivalid, oready, data) => {
x.request.valid := ivalid
x.request.bits := data
x.response.ready := oready
(x.request.ready, x.response.valid)
})
// (valid: Bool, data: UInt) => (ready: Bool)
// ready may combinationally depend on data (but not valid)
// effects must become visible on the cycle after valid && ready
implicit def apply(x: (Bool, UInt) => Bool) =
// combinational => data valid on oready
new RegWriteFn(true, { case (_, oready, data) =>
(true.B, x(oready, data))
})
// write to a DecoupledIO (only safe if there is a consistent sink draining data)
// NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid
implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
// updates a register (or adds a mux to a wire)
implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; true.B })
// noop
implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { true.B })
}
case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc])
{
require (width >= 0, s"RegField width must be >= 0, not $width")
def pipelined = !read.combinational || !write.combinational
def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R)))
def toJson(byteOffset: Int, bitOffset: Int): JValue = {
( ("byteOffset" -> s"0x${byteOffset.toHexString}") ~
("bitOffset" -> bitOffset) ~
("bitWidth" -> width) ~
("name" -> desc.map(_.name)) ~
("description" -> desc.map{ d=> if (d.desc == "") None else Some(d.desc)}) ~
("resetValue" -> desc.map{_.reset}) ~
("group" -> desc.map{_.group}) ~
("groupDesc" -> desc.map{_.groupDesc}) ~
("accessType" -> desc.map {d => d.access.toString}) ~
("writeType" -> desc.map {d => d.wrType.map(_.toString)}) ~
("readAction" -> desc.map {d => d.rdAction.map(_.toString)}) ~
("volatile" -> desc.map {d => if (d.volatile) Some(true) else None}) ~
("enumerations" -> desc.map {d =>
Option(d.enumerations.map { case (key, (name, edesc)) =>
(("value" -> key) ~ ("name" -> name) ~ ("description" -> edesc))
}).filter(_.nonEmpty)}) )
}
}
object RegField
{
// Byte address => sequence of bitfields, lowest index => lowest address
type Map = (Int, Seq[RegField])
def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved))
def apply(n: Int, desc: RegFieldDesc) : RegField = apply(n, (), (), Some(desc))
def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))
def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None)
def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc))
def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None)
def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R)))
def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None)
def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W)))
// This RegField allows 'set' to set bits in 'reg'.
// and to clear bits when the bus writes bits of value 1.
// Setting takes priority over clearing.
def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField =
RegField(n, reg, RegWriteFn((valid, data) => { reg := (~((~reg) | Mux(valid, data, 0.U))) | set; true.B }),
desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)})
// This RegField wraps an explicit register
// (e.g. Black-Boxed Register) to create a R/W register.
def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField =
RegField(n, bb.q, RegWriteFn((valid, data) => {
bb.en := valid
bb.d := data
true.B
}), desc)
// Create byte-sized read-write RegFields out of a large UInt register.
// It is updated when any of the (implemented) bytes are written, the non-written
// bytes are just copied over from their current value.
// Because the RegField are all byte-sized, this is also suitable when a register is larger
// than the intended bus width of the device (atomic updates are impossible).
def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = {
require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.")
val numFullBytes = reg.getWidth/8
val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0
val numPadBytes = numBytes - numFullBytes - numPartialBytes
val pad = reg | 0.U((8*numBytes).W)
val oldBytes = VecInit.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
val newBytes = WireDefault(oldBytes)
val valids = WireDefault(VecInit.fill(numBytes) { false.B })
when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => {
valids(i) := valid
when (valid) {newBytes(i) := data}
true.B
})
val fullBytes = Seq.tabulate(numFullBytes) { i =>
val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")}
RegField(8, oldBytes(i), wrFn(i), newDesc)}
val partialBytes = if (numPartialBytes > 0) {
val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")}
Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc),
RegField(8 - (reg.getWidth % 8)))
} else Nil
val padBytes = Seq.fill(numPadBytes){RegField(8)}
fullBytes ++ partialBytes ++ padBytes
}
def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = {
val width = reg.getWidth
require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits")
bytes(reg, width/8, desc)
}
def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None)
def bytes(reg: UInt): Seq[RegField] = bytes(reg, None)
}
trait HasRegMap
{
def regmap(mapping: RegField.Map*): Unit
val interrupts: Vec[Bool]
}
// See Example.scala for an example of how to use regmap
File PeripheryBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices}
import freechips.rocketchip.diplomacy.BufferParams
import freechips.rocketchip.tilelink.{
RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode,
TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge
}
import freechips.rocketchip.util.Location
case class BusAtomics(
arithmetic: Boolean = true,
buffer: BufferParams = BufferParams.default,
widenBytes: Option[Int] = None
)
case class PeripheryBusParams(
beatBytes: Int,
blockBytes: Int,
atomics: Option[BusAtomics] = Some(BusAtomics()),
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with HasRegionReplicatorParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = {
val pbus = LazyModule(new PeripheryBus(this, loc.name))
pbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> pbus)
pbus
}
}
class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
override lazy val desiredName = s"PeripheryBus_$name"
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
private val node: TLNode = params.atomics.map { pa =>
val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in")))
val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out")))
val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node)
(out_xbar.node
:*= fixer_node
:*= TLBuffer(pa.buffer)
:*= (pa.widenBytes.filter(_ > beatBytes).map { w =>
TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name))
} .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) })
:*= in_xbar.node)
} .getOrElse { TLXbar() :*= fixer.node }
def inwardNode: TLInwardNode = node
def outwardNode: TLOutwardNode = node
def busView: TLEdge = fixer.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File BootAddrReg.scala:
package testchipip.boot
import chisel3._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
case class BootAddrRegParams(
defaultBootAddress: BigInt = 0x80000000L, // This should be DRAM_BASE
bootRegAddress: BigInt = 0x1000,
slaveWhere: TLBusWrapperLocation = PBUS
)
case object BootAddrRegKey extends Field[Option[BootAddrRegParams]](None)
trait CanHavePeripheryBootAddrReg { this: BaseSubsystem =>
p(BootAddrRegKey).map { params =>
val tlbus = locateTLBusWrapper(params.slaveWhere)
val device = new SimpleDevice("boot-address-reg", Nil)
tlbus {
val node = TLRegisterNode(Seq(AddressSet(params.bootRegAddress, 4096-1)), device, "reg/control", beatBytes=tlbus.beatBytes)
tlbus.coupleTo("boot-address-reg") { node := TLFragmenter(tlbus, Some("BootAddrReg")) := _ }
InModuleBody {
val bootAddrReg = RegInit(params.defaultBootAddress.U(64.W))
node.regmap(0 -> RegField.bytes(bootAddrReg))
}
}
}
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File LazyScope.scala:
package org.chipsalliance.diplomacy.lazymodule
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
/** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. */
trait LazyScope {
this: LazyModule =>
override def toString: String = s"LazyScope named $name"
/** Evaluate `body` in the current [[LazyModule.scope]] */
def apply[T](body: => T): T = {
// Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function,
// [[LazyModule.scope]] will be altered.
val saved = LazyModule.scope
// [[LazyModule.scope]] stack push.
LazyModule.scope = Some(this)
// Evaluate [[body]] in the current `scope`, saving the result to [[out]].
val out = body
// Check that the `scope` after evaluating `body` is the same as when we started.
require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!")
require(
LazyModule.scope.get eq this,
s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed"
)
// [[LazyModule.scope]] stack pop.
LazyModule.scope = saved
out
}
}
/** Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can
* be instantiated and connected.
*
* It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this
* scope.
*/
object LazyScope {
/** Create a [[LazyScope]] with an implicit instance name.
*
* @param body
* code executed within the generated [[SimpleLazyModule]].
* @param valName
* instance name of generated [[SimpleLazyModule]].
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
body: => T
)(
implicit valName: ValName,
p: Parameters
): T = {
apply(valName.value, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicitly defined instance name.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String
)(body: => T
)(
implicit p: Parameters
): T = {
apply(name, "SimpleLazyModule", None)(body)(p)
}
/** Create a [[LazyScope]] with an explicit instance and class name, and control inlining.
*
* @param name
* instance name of generated [[SimpleLazyModule]].
* @param desiredModuleName
* class name of generated [[SimpleLazyModule]].
* @param overrideInlining
* tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined.
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def apply[T](
name: String,
desiredModuleName: String,
overrideInlining: Option[Boolean] = None
)(body: => T
)(
implicit p: Parameters
): T = {
val scope = LazyModule(new SimpleLazyModule with LazyScope {
override lazy val desiredName = desiredModuleName
override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined)
}).suggestName(name)
scope {
body
}
}
/** Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it.
*
* For example, we might want to control a set of children's clocks but then not keep the parent wrapper.
*
* @param body
* code executed within the generated `SimpleLazyModule`
* @param p
* [[Parameters]] propagated to [[SimpleLazyModule]].
*/
def inline[T](
body: => T
)(
implicit p: Parameters
): T = {
apply("noname", "ShouldBeInlined", Some(false))(body)(p)
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module PeripheryBus_pbus( // @[ClockDomain.scala:14:9]
input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire nodeIn_d_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_a_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_a_bits_size; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_ready; // @[MixedNode.scala:542:17]
wire in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [6:0] in_xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [6:0] in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29]
wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0 = auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0 = auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] fixer_auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] fixer_anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] in_xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] in_xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] in_xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer_auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire fixer_anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire in_xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire in_xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire in_xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire in_xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire in_xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire in_xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire in_xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire in_xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire in_xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire in_xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire in_xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire in_xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53]
wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] in_xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] in_xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] in_xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] in_xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] in_xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] in_xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire [2:0] in_xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] in_xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] in_xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] in_xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] in_xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] in_xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] in_xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] in_xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire in_xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire in_xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire in_xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire in_xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire in_xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire in_xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire in_xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire in_xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire in_xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire in_xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire in_xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire in_xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire in_xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire in_xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire in_xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire in_xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire in_xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire [28:0] in_xbar__addressC_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__addressC_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar__requestCIO_T = 29'h0; // @[Parameters.scala:137:31]
wire [28:0] in_xbar__requestBOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__requestBOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar__beatsBO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__beatsBO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar__beatsCI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__beatsCI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar__portsBIO_WIRE_bits_address = 29'h0; // @[Bundles.scala:264:74]
wire [28:0] in_xbar__portsBIO_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:264:61]
wire [28:0] in_xbar_portsBIO_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [28:0] in_xbar__portsCOI_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] in_xbar__portsCOI_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] in_xbar_portsCOI_filtered_0_bits_address = 29'h0; // @[Xbar.scala:352:24]
wire [6:0] in_xbar__addressC_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__addressC_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar__requestBOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__requestBOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar__requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29]
wire [6:0] in_xbar_requestBOI_uncommonBits = 7'h0; // @[Parameters.scala:52:56]
wire [6:0] in_xbar__beatsBO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__beatsBO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar__beatsCI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__beatsCI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar__portsBIO_WIRE_bits_source = 7'h0; // @[Bundles.scala:264:74]
wire [6:0] in_xbar__portsBIO_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:264:61]
wire [6:0] in_xbar_portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [6:0] in_xbar__portsCOI_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] in_xbar__portsCOI_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] in_xbar_portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24]
wire [7:0] in_xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] in_xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] in_xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] in_xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] in_xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] in_xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] in_xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] in_xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] in_xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestAIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestAIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestCIO_T_1 = 30'h0; // @[Parameters.scala:137:41]
wire [29:0] in_xbar__requestCIO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] in_xbar__requestCIO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46]
wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_10 = fixer__a_id_T_4; // @[Mux.scala:30:73]
wire [28:0] fixer__a_id_T_5 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46]
wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] fixer__a_id_T_11 = {fixer__a_id_T_9, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_12 = {1'h0, fixer__a_id_T_10} | fixer__a_id_T_11; // @[Mux.scala:30:73]
wire [1:0] fixer_a_id = fixer__a_id_T_12; // @[Mux.scala:30:73]
wire fixer_a_noDomain = fixer_a_id == 2'h0; // @[Mux.scala:30:73]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__a_first_beats1_decode_T = 13'h3F << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [12:0] fixer__d_first_beats1_decode_T = 13'h3F << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [5:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [3:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_31; // @[FIFOFixer.scala:79:27]
reg fixer_flight_32; // @[FIFOFixer.scala:79:27]
reg fixer_flight_33; // @[FIFOFixer.scala:79:27]
reg fixer_flight_34; // @[FIFOFixer.scala:79:27]
reg fixer_flight_35; // @[FIFOFixer.scala:79:27]
reg fixer_flight_36; // @[FIFOFixer.scala:79:27]
reg fixer_flight_37; // @[FIFOFixer.scala:79:27]
reg fixer_flight_38; // @[FIFOFixer.scala:79:27]
reg fixer_flight_39; // @[FIFOFixer.scala:79:27]
reg fixer_flight_40; // @[FIFOFixer.scala:79:27]
reg fixer_flight_41; // @[FIFOFixer.scala:79:27]
reg fixer_flight_42; // @[FIFOFixer.scala:79:27]
reg fixer_flight_43; // @[FIFOFixer.scala:79:27]
reg fixer_flight_44; // @[FIFOFixer.scala:79:27]
reg fixer_flight_45; // @[FIFOFixer.scala:79:27]
reg fixer_flight_46; // @[FIFOFixer.scala:79:27]
reg fixer_flight_47; // @[FIFOFixer.scala:79:27]
reg fixer_flight_48; // @[FIFOFixer.scala:79:27]
reg fixer_flight_49; // @[FIFOFixer.scala:79:27]
reg fixer_flight_50; // @[FIFOFixer.scala:79:27]
reg fixer_flight_51; // @[FIFOFixer.scala:79:27]
reg fixer_flight_52; // @[FIFOFixer.scala:79:27]
reg fixer_flight_53; // @[FIFOFixer.scala:79:27]
reg fixer_flight_54; // @[FIFOFixer.scala:79:27]
reg fixer_flight_55; // @[FIFOFixer.scala:79:27]
reg fixer_flight_56; // @[FIFOFixer.scala:79:27]
reg fixer_flight_57; // @[FIFOFixer.scala:79:27]
reg fixer_flight_58; // @[FIFOFixer.scala:79:27]
reg fixer_flight_59; // @[FIFOFixer.scala:79:27]
reg fixer_flight_60; // @[FIFOFixer.scala:79:27]
reg fixer_flight_61; // @[FIFOFixer.scala:79:27]
reg fixer_flight_62; // @[FIFOFixer.scala:79:27]
reg fixer_flight_63; // @[FIFOFixer.scala:79:27]
reg fixer_flight_64; // @[FIFOFixer.scala:79:27]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire in_xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_a_valid = in_xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_opcode = in_xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_param = in_xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonIn_a_bits_size = in_xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_anonIn_a_bits_source = in_xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_anonIn_a_bits_address = in_xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_anonIn_a_bits_mask = in_xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_anonIn_a_bits_data = in_xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_a_bits_corrupt = in_xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_d_ready = in_xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] in_xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] in_xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] in_xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] in_xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] in_xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire in_xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire in_xbar_anonOut_a_ready = in_xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] in_xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] in_xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] in_xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] in_xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] in_xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire in_xbar_anonOut_d_valid = in_xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonOut_d_bits_opcode = in_xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_anonOut_d_bits_param = in_xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_anonOut_d_bits_size = in_xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_anonOut_d_bits_source = in_xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_sink = in_xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_denied = in_xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_anonOut_d_bits_data = in_xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_anonOut_d_bits_corrupt = in_xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire in_xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_out_0_a_ready = in_xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire in_xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_valid = in_xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_opcode = in_xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_param = in_xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_size = in_xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_source = in_xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [28:0] in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_address = in_xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_mask = in_xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_data = in_xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_a_bits_corrupt = in_xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign in_xbar_auto_anon_out_d_ready = in_xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire in_xbar_out_0_d_valid = in_xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_out_0_d_bits_opcode = in_xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] in_xbar_out_0_d_bits_param = in_xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_out_0_d_bits_size = in_xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [6:0] in_xbar_out_0_d_bits_source = in_xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire in_xbar__out_0_d_bits_sink_T = in_xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire in_xbar_out_0_d_bits_denied = in_xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] in_xbar_out_0_d_bits_data = in_xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire in_xbar_out_0_d_bits_corrupt = in_xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire in_xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_a_ready = in_xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_xbar_in_0_a_valid = in_xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_opcode = in_xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_param = in_xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_in_0_a_bits_size = in_xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [6:0] in_xbar__in_0_a_bits_source_T = in_xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [28:0] in_xbar_in_0_a_bits_address = in_xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_xbar_in_0_a_bits_mask = in_xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_xbar_in_0_a_bits_data = in_xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_xbar_in_0_a_bits_corrupt = in_xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_xbar_in_0_d_ready = in_xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_valid = in_xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_opcode = in_xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_param = in_xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_size = in_xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [6:0] in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_xbar_auto_anon_in_d_bits_source = in_xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_sink = in_xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_denied = in_xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_data = in_xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign in_xbar_auto_anon_in_d_bits_corrupt = in_xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_a_ready = in_xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire in_xbar__portsAOI_filtered_0_valid_T_1 = in_xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_opcode = in_xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_param = in_xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] in_xbar_portsAOI_filtered_0_bits_size = in_xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [6:0] in_xbar_portsAOI_filtered_0_bits_source = in_xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [28:0] in_xbar__requestAIO_T = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [28:0] in_xbar_portsAOI_filtered_0_bits_address = in_xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] in_xbar_portsAOI_filtered_0_bits_mask = in_xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] in_xbar_portsAOI_filtered_0_bits_data = in_xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsAOI_filtered_0_bits_corrupt = in_xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsDIO_filtered_0_ready = in_xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_valid = in_xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_opcode = in_xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_param = in_xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_size = in_xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [6:0] in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign in_xbar__anonIn_d_bits_source_T = in_xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_sink = in_xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_denied = in_xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_data = in_xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign in_xbar_anonIn_d_bits_corrupt = in_xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign in_xbar_in_0_a_bits_source = in_xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign in_xbar_anonIn_d_bits_source = in_xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_xbar_portsAOI_filtered_0_ready = in_xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign in_xbar_anonOut_a_valid = in_xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_opcode = in_xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_param = in_xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_size = in_xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_source = in_xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_address = in_xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_mask = in_xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_data = in_xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_a_bits_corrupt = in_xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign in_xbar_anonOut_d_ready = in_xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire in_xbar__portsDIO_filtered_0_valid_T_1 = in_xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign in_xbar_portsDIO_filtered_0_bits_opcode = in_xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_param = in_xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_size = in_xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [6:0] in_xbar__requestDOI_uncommonBits_T = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign in_xbar_portsDIO_filtered_0_bits_source = in_xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_sink = in_xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_denied = in_xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_data = in_xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsDIO_filtered_0_bits_corrupt = in_xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_d_bits_sink = in_xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [29:0] in_xbar__requestAIO_T_1 = {1'h0, in_xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [6:0] in_xbar_requestDOI_uncommonBits = in_xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] in_xbar__beatsAI_decode_T = 13'h3F << in_xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] in_xbar__beatsAI_decode_T_1 = in_xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] in_xbar__beatsAI_decode_T_2 = ~in_xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] in_xbar_beatsAI_decode = in_xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire in_xbar__beatsAI_opdata_T = in_xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire in_xbar_beatsAI_opdata = ~in_xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] in_xbar_beatsAI_0 = in_xbar_beatsAI_opdata ? in_xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] in_xbar__beatsDO_decode_T = 13'h3F << in_xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] in_xbar__beatsDO_decode_T_1 = in_xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] in_xbar__beatsDO_decode_T_2 = ~in_xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] in_xbar_beatsDO_decode = in_xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire in_xbar_beatsDO_opdata = in_xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] in_xbar_beatsDO_0 = in_xbar_beatsDO_opdata ? in_xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign in_xbar_in_0_a_ready = in_xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_out_0_a_valid = in_xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_opcode = in_xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_param = in_xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_size = in_xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_source = in_xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_address = in_xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_mask = in_xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_data = in_xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_out_0_a_bits_corrupt = in_xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_portsAOI_filtered_0_valid = in_xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign in_xbar_out_0_d_ready = in_xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign in_xbar_in_0_d_valid = in_xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_opcode = in_xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_param = in_xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_size = in_xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_source = in_xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_sink = in_xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_denied = in_xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_data = in_xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_in_0_d_bits_corrupt = in_xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign in_xbar_portsDIO_filtered_0_valid = in_xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
wire [2:0] nodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [12:0] nodeIn_a_bits_address; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
reg [63:0] bootAddrReg; // @[BootAddrReg.scala:27:34]
wire [63:0] pad = bootAddrReg; // @[BootAddrReg.scala:27:34]
wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}]
wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57]
wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}]
wire [7:0] _out_T_7 = oldBytes_0; // @[RegisterRouter.scala:87:24]
wire [7:0] newBytes_0; // @[RegField.scala:152:31]
wire [7:0] newBytes_1; // @[RegField.scala:152:31]
wire [7:0] newBytes_2; // @[RegField.scala:152:31]
wire [7:0] newBytes_3; // @[RegField.scala:152:31]
wire [7:0] newBytes_4; // @[RegField.scala:152:31]
wire [7:0] newBytes_5; // @[RegField.scala:152:31]
wire [7:0] newBytes_6; // @[RegField.scala:152:31]
wire [7:0] newBytes_7; // @[RegField.scala:152:31]
wire out_f_woready; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire valids_0; // @[RegField.scala:153:29]
wire valids_1; // @[RegField.scala:153:29]
wire valids_2; // @[RegField.scala:153:29]
wire valids_3; // @[RegField.scala:153:29]
wire valids_4; // @[RegField.scala:153:29]
wire valids_5; // @[RegField.scala:153:29]
wire valids_6; // @[RegField.scala:153:29]
wire valids_7; // @[RegField.scala:153:29]
wire [15:0] bootAddrReg_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52]
wire [15:0] bootAddrReg_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52]
wire [31:0] bootAddrReg_lo = {bootAddrReg_lo_hi, bootAddrReg_lo_lo}; // @[RegField.scala:154:52]
wire [15:0] bootAddrReg_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52]
wire [15:0] bootAddrReg_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52]
wire [31:0] bootAddrReg_hi = {bootAddrReg_hi_hi, bootAddrReg_hi_lo}; // @[RegField.scala:154:52]
wire [63:0] _bootAddrReg_T = {bootAddrReg_hi, bootAddrReg_lo}; // @[RegField.scala:154:52]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [9:0] _in_bits_index_T = nodeIn_a_bits_address[12:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
assign out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
assign valids_0 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_2 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign newBytes_0 = out_f_woready ? _out_T_2 : oldBytes_0; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = _out_T_8; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
assign out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
assign valids_1 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_9 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
assign newBytes_1 = out_f_woready_1 ? _out_T_9 : oldBytes_1; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend = {oldBytes_1, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_14 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_15 = _out_T_14; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = _out_T_15; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
assign valids_2 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
assign newBytes_2 = out_f_woready_2 ? _out_T_16 : oldBytes_2; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_1 = {oldBytes_2, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_21 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_22 = _out_T_21; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = _out_T_22; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
assign valids_3 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_23 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
assign newBytes_3 = out_f_woready_3 ? _out_T_23 : oldBytes_3; // @[RegisterRouter.scala:87:24]
wire _out_T_24 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_2 = {oldBytes_3, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_28 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_29 = _out_T_28; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_3 = _out_T_29; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_4 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_4 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
assign valids_4 = out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_30 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
assign newBytes_4 = out_f_woready_4 ? _out_T_30 : oldBytes_4; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_3 = {oldBytes_4, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_35 = out_prepend_3; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_4 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_5 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_5 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
assign valids_5 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_37 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24]
assign newBytes_5 = out_f_woready_5 ? _out_T_37 : oldBytes_5; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [47:0] out_prepend_4 = {oldBytes_5, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_42 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_5 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_6 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_6 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
assign valids_6 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_44 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24]
assign newBytes_6 = out_f_woready_6 ? _out_T_44 : oldBytes_6; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire [55:0] out_prepend_5 = {oldBytes_6, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_49 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_T_50 = _out_T_49; // @[RegisterRouter.scala:87:24]
wire [55:0] _out_prepend_T_6 = _out_T_50; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_7 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_7 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
assign valids_7 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_51 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24]
assign newBytes_7 = out_f_woready_7 ? _out_T_51 : oldBytes_7; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_6 = {oldBytes_7, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_56 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_57 = _out_T_56; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_57; // @[MuxLiteral.scala:49:48]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 3'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35]
bootAddrReg <= 64'h80000000; // @[BootAddrReg.scala:27:34]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27]
bootAddrReg <= _bootAddrReg_T; // @[BootAddrReg.scala:27:34]
end
always @(posedge)
FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_pbus_out_i1_o2_a29d64s7k1z3u out_xbar ( // @[PeripheryBus.scala:57:30]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (fixer_auto_anon_out_a_ready),
.auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_valid (fixer_auto_anon_out_d_valid),
.auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode),
.auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size),
.auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source),
.auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data),
.auto_anon_out_1_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data) // @[LazyScope.scala:98:27]
); // @[PeripheryBus.scala:57:30]
TLBuffer_a29d64s7k1z3u buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29]
.auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9]
.auto_out_a_valid (fixer_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (fixer_auto_anon_in_d_ready),
.auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data) // @[FIFOFixer.scala:50:9]
); // @[Buffer.scala:75:28]
TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (in_xbar_auto_anon_out_a_ready),
.auto_in_a_valid (in_xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (in_xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (in_xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (in_xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (in_xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (in_xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (in_xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (in_xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (in_xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (in_xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (in_xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (in_xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (in_xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (in_xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (in_xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (in_xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (in_xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (in_xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (in_xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_atomics_auto_out_a_valid),
.auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_atomics_auto_out_a_bits_param),
.auto_out_a_bits_size (_atomics_auto_out_a_bits_size),
.auto_out_a_bits_source (_atomics_auto_out_a_bits_source),
.auto_out_a_bits_address (_atomics_auto_out_a_bits_address),
.auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask),
.auto_out_a_bits_data (_atomics_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt),
.auto_out_d_ready (_atomics_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28]
); // @[AtomicAutomata.scala:289:29]
TLBuffer_a29d64s7k1z3u_1 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (bus_xingOut_a_ready),
.auto_in_a_valid (bus_xingOut_a_valid), // @[MixedNode.scala:542:17]
.auto_in_a_bits_opcode (bus_xingOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_a_bits_param (bus_xingOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_in_a_bits_size (bus_xingOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_in_a_bits_source (bus_xingOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_in_a_bits_address (bus_xingOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_in_a_bits_mask (bus_xingOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_in_a_bits_data (bus_xingOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_in_a_bits_corrupt (bus_xingOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_in_d_ready (bus_xingOut_d_ready), // @[MixedNode.scala:542:17]
.auto_in_d_valid (bus_xingOut_d_valid),
.auto_in_d_bits_opcode (bus_xingOut_d_bits_opcode),
.auto_in_d_bits_param (bus_xingOut_d_bits_param),
.auto_in_d_bits_size (bus_xingOut_d_bits_size),
.auto_in_d_bits_source (bus_xingOut_d_bits_source),
.auto_in_d_bits_sink (bus_xingOut_d_bits_sink),
.auto_in_d_bits_denied (bus_xingOut_d_bits_denied),
.auto_in_d_bits_data (bus_xingOut_d_bits_data),
.auto_in_d_bits_corrupt (bus_xingOut_d_bits_corrupt),
.auto_out_a_ready (in_xbar_auto_anon_in_a_ready), // @[Xbar.scala:74:9]
.auto_out_a_valid (in_xbar_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (in_xbar_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (in_xbar_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (in_xbar_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (in_xbar_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (in_xbar_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (in_xbar_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (in_xbar_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (in_xbar_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (in_xbar_auto_anon_in_d_ready),
.auto_out_d_valid (in_xbar_auto_anon_in_d_valid), // @[Xbar.scala:74:9]
.auto_out_d_bits_opcode (in_xbar_auto_anon_in_d_bits_opcode), // @[Xbar.scala:74:9]
.auto_out_d_bits_param (in_xbar_auto_anon_in_d_bits_param), // @[Xbar.scala:74:9]
.auto_out_d_bits_size (in_xbar_auto_anon_in_d_bits_size), // @[Xbar.scala:74:9]
.auto_out_d_bits_source (in_xbar_auto_anon_in_d_bits_source), // @[Xbar.scala:74:9]
.auto_out_d_bits_sink (in_xbar_auto_anon_in_d_bits_sink), // @[Xbar.scala:74:9]
.auto_out_d_bits_denied (in_xbar_auto_anon_in_d_bits_denied), // @[Xbar.scala:74:9]
.auto_out_d_bits_data (in_xbar_auto_anon_in_d_bits_data), // @[Xbar.scala:74:9]
.auto_out_d_bits_corrupt (in_xbar_auto_anon_in_d_bits_corrupt) // @[Xbar.scala:74:9]
); // @[Buffer.scala:75:28]
TLInterconnectCoupler_pbus_to_bootaddressreg coupler_to_bootaddressreg ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_a_valid (nodeIn_a_valid),
.auto_fragmenter_anon_out_a_bits_opcode (nodeIn_a_bits_opcode),
.auto_fragmenter_anon_out_a_bits_param (nodeIn_a_bits_param),
.auto_fragmenter_anon_out_a_bits_size (nodeIn_a_bits_size),
.auto_fragmenter_anon_out_a_bits_source (nodeIn_a_bits_source),
.auto_fragmenter_anon_out_a_bits_address (nodeIn_a_bits_address),
.auto_fragmenter_anon_out_a_bits_mask (nodeIn_a_bits_mask),
.auto_fragmenter_anon_out_a_bits_data (nodeIn_a_bits_data),
.auto_fragmenter_anon_out_a_bits_corrupt (nodeIn_a_bits_corrupt),
.auto_fragmenter_anon_out_d_ready (nodeIn_d_ready),
.auto_fragmenter_anon_out_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_fragmenter_anon_out_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_tl_in_a_ready (_coupler_to_bootaddressreg_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_bootaddressreg_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_bootaddressreg_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_bootaddressreg_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_bootaddressreg_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_pbus_to_device_named_uart_0 coupler_to_device_named_uart_0 ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_control_xing_out_a_ready (auto_coupler_to_device_named_uart_0_control_xing_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_a_valid (auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0),
.auto_control_xing_out_a_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0),
.auto_control_xing_out_a_bits_param (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0),
.auto_control_xing_out_a_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0),
.auto_control_xing_out_a_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0),
.auto_control_xing_out_a_bits_address (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0),
.auto_control_xing_out_a_bits_mask (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0),
.auto_control_xing_out_a_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0),
.auto_control_xing_out_a_bits_corrupt (auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0),
.auto_control_xing_out_d_ready (auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0),
.auto_control_xing_out_d_valid (auto_coupler_to_device_named_uart_0_control_xing_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_opcode (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_size (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_source (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_control_xing_out_d_bits_data (auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_device_named_uart_0_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_device_named_uart_0_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_device_named_uart_0_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLMonitor_11 monitor ( // @[Nodes.scala:27:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid = auto_coupler_to_device_named_uart_0_control_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt = auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready = auto_coupler_to_device_named_uart_0_control_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_1( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1263 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1278 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_31( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59]
wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14]
wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27]
wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25]
wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21]
wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28]
wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1081 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1081; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1081; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1004 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1004; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1004; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1081 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46]
wire _T_1053 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1053 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1022 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}]
assign d_clr = _T_1022 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1022 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1022 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1125 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1125 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1107 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}]
assign d_clr_1 = _T_1107 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1107 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1107 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
File AsyncCrossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.CrossingWrapper
import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property}
class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule
{
def this(x: Int)(implicit p: Parameters) = this(Some(x))
def this()(implicit p: Parameters) = this(None)
val node = TLAsyncSourceNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
val psync = sync.getOrElse(edgeOut.manager.async.sync)
val params = edgeOut.manager.async.copy(sync = psync)
out.a <> ToAsyncBundle(in.a, params)
in.d <> FromAsyncBundle(out.d, psync)
property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A")
property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D")
if (bce) {
in.b <> FromAsyncBundle(out.b, psync)
out.c <> ToAsyncBundle(in.c, params)
out.e <> ToAsyncBundle(in.e, params)
property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B")
property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C")
property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E")
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ridx := 0.U
out.c.widx := 0.U
out.e.widx := 0.U
}
}
}
}
class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSinkNode(params)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
out.a <> FromAsyncBundle(in.a, params.sync)
in.d <> ToAsyncBundle(out.d, params)
property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A")
property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D")
if (bce) {
in.b <> ToAsyncBundle(out.b, params)
out.c <> FromAsyncBundle(in.c, params.sync)
out.e <> FromAsyncBundle(in.e, params.sync)
property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B")
property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C")
property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E")
} else {
in.b.widx := 0.U
in.c.ridx := 0.U
in.e.ridx := 0.U
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLAsyncCrossingSource
{
def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None)
def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync))
def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode =
{
val asource = LazyModule(new TLAsyncCrossingSource(sync))
asource.node
}
}
object TLAsyncCrossingSink
{
def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) =
{
val asink = LazyModule(new TLAsyncCrossingSink(params))
asink.node
}
}
@deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule
{
val source = LazyModule(new TLAsyncCrossingSource())
val sink = LazyModule(new TLAsyncCrossingSink(params))
val node = NodeHandle(source.node, sink.node)
sink.node := source.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val in_clock = Input(Clock())
val in_reset = Input(Bool())
val out_clock = Input(Clock())
val out_reset = Input(Bool())
})
source.module.clock := io.in_clock
source.module.reset := io.in_reset
sink.module.clock := io.out_clock
sink.module.reset := io.out_reset
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val fuzz = LazyModule(new TLFuzzer(txns))
val island = LazyModule(new CrossingWrapper(params))
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
// Shove the RAM into another clock domain
val clocks = Module(new Pow2ClockDivider(2))
island.module.clock := clocks.io.clock_out
}
}
class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module)
val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module)
io.finished := dut_wide.io.finished && dut_narrow.io.finished
dut_wide.io.start := io.start
dut_narrow.io.start := io.start
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLAsyncCrossingSource_a32d64s5k3z4u( // @[AsyncCrossing.scala:23:9]
input clock, // @[AsyncCrossing.scala:23:9]
input reset, // @[AsyncCrossing.scala:23:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_0_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_0_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_0_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_0_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_1_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_1_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_1_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_1_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_1_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_1_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_1_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_2_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_2_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_2_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_2_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_2_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_2_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_2_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_3_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_3_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_3_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_3_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_3_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_3_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_3_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_4_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_4_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_4_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_4_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_4_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_4_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_4_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_5_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_5_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_5_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_5_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_5_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_5_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_5_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_6_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_6_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_6_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_6_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_6_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_6_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_6_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_7_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_mem_7_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_mem_7_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_7_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_mem_7_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_mem_7_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_mem_7_corrupt, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_a_ridx, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_0_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_1_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_1_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_1_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_1_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_1_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_1_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_1_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_1_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_2_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_2_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_2_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_2_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_2_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_2_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_2_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_2_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_3_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_3_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_3_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_3_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_3_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_3_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_3_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_3_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_4_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_4_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_4_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_4_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_4_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_4_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_4_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_4_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_5_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_5_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_5_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_5_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_5_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_5_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_5_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_5_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_6_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_6_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_6_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_6_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_6_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_6_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_6_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_6_corrupt, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_7_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_7_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_mem_7_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_mem_7_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_7_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_7_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_mem_7_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_7_corrupt, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_d_ridx, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_widx, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_param_0 = auto_out_d_mem_0_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_sink_0 = auto_out_d_mem_0_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_denied_0 = auto_out_d_mem_0_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_corrupt_0 = auto_out_d_mem_0_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_1_opcode_0 = auto_out_d_mem_1_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_1_param_0 = auto_out_d_mem_1_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_1_size_0 = auto_out_d_mem_1_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_1_source_0 = auto_out_d_mem_1_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_1_sink_0 = auto_out_d_mem_1_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_1_denied_0 = auto_out_d_mem_1_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_1_data_0 = auto_out_d_mem_1_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_1_corrupt_0 = auto_out_d_mem_1_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_2_opcode_0 = auto_out_d_mem_2_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_2_param_0 = auto_out_d_mem_2_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_2_size_0 = auto_out_d_mem_2_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_2_source_0 = auto_out_d_mem_2_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_2_sink_0 = auto_out_d_mem_2_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_2_denied_0 = auto_out_d_mem_2_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_2_data_0 = auto_out_d_mem_2_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_2_corrupt_0 = auto_out_d_mem_2_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_3_opcode_0 = auto_out_d_mem_3_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_3_param_0 = auto_out_d_mem_3_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_3_size_0 = auto_out_d_mem_3_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_3_source_0 = auto_out_d_mem_3_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_3_sink_0 = auto_out_d_mem_3_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_3_denied_0 = auto_out_d_mem_3_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_3_data_0 = auto_out_d_mem_3_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_3_corrupt_0 = auto_out_d_mem_3_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_4_opcode_0 = auto_out_d_mem_4_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_4_param_0 = auto_out_d_mem_4_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_4_size_0 = auto_out_d_mem_4_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_4_source_0 = auto_out_d_mem_4_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_4_sink_0 = auto_out_d_mem_4_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_4_denied_0 = auto_out_d_mem_4_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_4_data_0 = auto_out_d_mem_4_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_4_corrupt_0 = auto_out_d_mem_4_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_5_opcode_0 = auto_out_d_mem_5_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_5_param_0 = auto_out_d_mem_5_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_5_size_0 = auto_out_d_mem_5_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_5_source_0 = auto_out_d_mem_5_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_5_sink_0 = auto_out_d_mem_5_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_5_denied_0 = auto_out_d_mem_5_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_5_data_0 = auto_out_d_mem_5_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_5_corrupt_0 = auto_out_d_mem_5_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_6_opcode_0 = auto_out_d_mem_6_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_6_param_0 = auto_out_d_mem_6_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_6_size_0 = auto_out_d_mem_6_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_6_source_0 = auto_out_d_mem_6_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_6_sink_0 = auto_out_d_mem_6_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_6_denied_0 = auto_out_d_mem_6_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_6_data_0 = auto_out_d_mem_6_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_6_corrupt_0 = auto_out_d_mem_6_corrupt; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_7_opcode_0 = auto_out_d_mem_7_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_7_param_0 = auto_out_d_mem_7_param; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_mem_7_size_0 = auto_out_d_mem_7_size; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_d_mem_7_source_0 = auto_out_d_mem_7_source; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_7_sink_0 = auto_out_d_mem_7_sink; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_7_denied_0 = auto_out_d_mem_7_denied; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_d_mem_7_data_0 = auto_out_d_mem_7_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_7_corrupt_0 = auto_out_d_mem_7_corrupt; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_1_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_2_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_3_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_4_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_5_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_6_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_7_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_1_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_2_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_3_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_4_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_5_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_6_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_7_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_1_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_2_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_3_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_4_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_5_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_6_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_7_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_out_b_mem_0_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_1_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_2_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_3_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_4_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_5_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_6_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_b_mem_7_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_0_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_1_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_2_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_3_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_4_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_5_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_6_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_c_mem_7_data = 64'h0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_b_mem_0_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_1_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_2_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_3_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_4_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_5_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_6_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_b_mem_7_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_0_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_1_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_2_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_3_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_4_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_5_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_6_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_mem_7_data = 64'h0; // @[MixedNode.scala:542:17]
wire [7:0] auto_out_b_mem_0_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_1_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_2_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_3_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_4_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_5_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_6_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_b_mem_7_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_0_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_1_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_2_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_3_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_4_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_5_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_6_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeOut_b_mem_7_mask = 8'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_0_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_1_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_2_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_3_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_4_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_5_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_6_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_7_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_0_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_1_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_2_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_3_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_4_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_5_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_6_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_7_address = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_0_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_1_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_2_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_3_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_4_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_5_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_6_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_b_mem_7_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_0_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_1_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_2_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_3_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_4_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_5_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_6_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_7_address = 32'h0; // @[MixedNode.scala:542:17]
wire [4:0] auto_out_b_mem_0_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_1_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_2_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_3_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_4_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_5_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_6_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_b_mem_7_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_0_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_1_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_2_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_3_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_4_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_5_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_6_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_c_mem_7_source = 5'h0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_b_mem_0_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_1_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_2_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_3_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_4_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_5_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_6_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_b_mem_7_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_0_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_1_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_2_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_3_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_4_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_5_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_6_source = 5'h0; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_c_mem_7_source = 5'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_out_b_mem_0_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_1_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_2_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_3_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_4_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_5_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_6_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_mem_7_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_ridx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_b_widx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_0_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_1_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_2_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_3_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_4_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_5_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_6_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_mem_7_size = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_ridx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_c_widx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_e_ridx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_e_widx = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_b_mem_0_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_1_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_2_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_3_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_4_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_5_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_6_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_mem_7_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_ridx = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_b_widx = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_0_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_1_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_2_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_3_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_4_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_5_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_6_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_mem_7_size = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_ridx = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_widx = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_ridx = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_widx = 4'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_1_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_2_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_3_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_4_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_5_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_6_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_7_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_1_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_2_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_3_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_4_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_5_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_6_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_7_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_1_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_2_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_3_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_4_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_5_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_6_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_7_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_1_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_1_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_2_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_2_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_3_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_3_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_4_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_4_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_5_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_5_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_6_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_6_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_7_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_7_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_0_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_1_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_2_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_3_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_4_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_5_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_6_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_e_mem_7_sink = 3'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_1_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_2_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_3_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_4_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_5_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_6_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_7_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_1_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_1_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_2_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_2_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_3_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_3_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_4_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_4_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_5_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_5_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_6_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_6_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_7_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_7_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_0_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_1_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_2_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_3_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_4_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_5_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_6_sink = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_mem_7_sink = 3'h0; // @[MixedNode.scala:542:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_0_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_0_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_0_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_0_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_0_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_1_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_1_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_1_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_1_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_1_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_1_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_1_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_1_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_2_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_2_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_2_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_2_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_2_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_2_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_2_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_2_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_3_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_3_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_3_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_3_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_3_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_3_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_3_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_3_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_4_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_4_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_4_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_4_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_4_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_4_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_4_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_4_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_5_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_5_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_5_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_5_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_5_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_5_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_5_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_5_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_6_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_6_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_6_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_6_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_6_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_6_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_6_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_6_corrupt; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_7_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_mem_7_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_mem_7_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_mem_7_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_7_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_mem_7_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_mem_7_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_7_corrupt; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_a_widx; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_0_param = auto_out_d_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_sink = auto_out_d_mem_0_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_denied = auto_out_d_mem_0_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_corrupt = auto_out_d_mem_0_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_1_opcode = auto_out_d_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_1_param = auto_out_d_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_1_size = auto_out_d_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_1_source = auto_out_d_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_1_sink = auto_out_d_mem_1_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_1_denied = auto_out_d_mem_1_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_1_data = auto_out_d_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_1_corrupt = auto_out_d_mem_1_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_2_opcode = auto_out_d_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_2_param = auto_out_d_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_2_size = auto_out_d_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_2_source = auto_out_d_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_2_sink = auto_out_d_mem_2_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_2_denied = auto_out_d_mem_2_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_2_data = auto_out_d_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_2_corrupt = auto_out_d_mem_2_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_3_opcode = auto_out_d_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_3_param = auto_out_d_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_3_size = auto_out_d_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_3_source = auto_out_d_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_3_sink = auto_out_d_mem_3_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_3_denied = auto_out_d_mem_3_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_3_data = auto_out_d_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_3_corrupt = auto_out_d_mem_3_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_4_opcode = auto_out_d_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_4_param = auto_out_d_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_4_size = auto_out_d_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_4_source = auto_out_d_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_4_sink = auto_out_d_mem_4_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_4_denied = auto_out_d_mem_4_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_4_data = auto_out_d_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_4_corrupt = auto_out_d_mem_4_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_5_opcode = auto_out_d_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_5_param = auto_out_d_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_5_size = auto_out_d_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_5_source = auto_out_d_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_5_sink = auto_out_d_mem_5_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_5_denied = auto_out_d_mem_5_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_5_data = auto_out_d_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_5_corrupt = auto_out_d_mem_5_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_6_opcode = auto_out_d_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_6_param = auto_out_d_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_6_size = auto_out_d_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_6_source = auto_out_d_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_6_sink = auto_out_d_mem_6_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_6_denied = auto_out_d_mem_6_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_6_data = auto_out_d_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_6_corrupt = auto_out_d_mem_6_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_7_opcode = auto_out_d_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_7_param = auto_out_d_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_mem_7_size = auto_out_d_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] nodeOut_d_mem_7_source = auto_out_d_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_7_sink = auto_out_d_mem_7_sink_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_7_denied = auto_out_d_mem_7_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] nodeOut_d_mem_7_data = auto_out_d_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_7_corrupt = auto_out_d_mem_7_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_d_ridx; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_0_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_1_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_1_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_2_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_2_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_3_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_3_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_4_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_4_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_5_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_5_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_6_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_6_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
wire [4:0] auto_out_a_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
wire [7:0] auto_out_a_mem_7_mask_0; // @[AsyncCrossing.scala:23:9]
wire [63:0] auto_out_a_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_7_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_param_0 = nodeOut_a_mem_0_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_size_0 = nodeOut_a_mem_0_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_source_0 = nodeOut_a_mem_0_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_mask_0 = nodeOut_a_mem_0_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_corrupt_0 = nodeOut_a_mem_0_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_opcode_0 = nodeOut_a_mem_1_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_param_0 = nodeOut_a_mem_1_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_size_0 = nodeOut_a_mem_1_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_source_0 = nodeOut_a_mem_1_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_address_0 = nodeOut_a_mem_1_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_mask_0 = nodeOut_a_mem_1_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_data_0 = nodeOut_a_mem_1_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_corrupt_0 = nodeOut_a_mem_1_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_opcode_0 = nodeOut_a_mem_2_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_param_0 = nodeOut_a_mem_2_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_size_0 = nodeOut_a_mem_2_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_source_0 = nodeOut_a_mem_2_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_address_0 = nodeOut_a_mem_2_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_mask_0 = nodeOut_a_mem_2_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_data_0 = nodeOut_a_mem_2_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_corrupt_0 = nodeOut_a_mem_2_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_opcode_0 = nodeOut_a_mem_3_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_param_0 = nodeOut_a_mem_3_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_size_0 = nodeOut_a_mem_3_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_source_0 = nodeOut_a_mem_3_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_address_0 = nodeOut_a_mem_3_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_mask_0 = nodeOut_a_mem_3_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_data_0 = nodeOut_a_mem_3_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_corrupt_0 = nodeOut_a_mem_3_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_opcode_0 = nodeOut_a_mem_4_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_param_0 = nodeOut_a_mem_4_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_size_0 = nodeOut_a_mem_4_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_source_0 = nodeOut_a_mem_4_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_address_0 = nodeOut_a_mem_4_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_mask_0 = nodeOut_a_mem_4_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_data_0 = nodeOut_a_mem_4_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_corrupt_0 = nodeOut_a_mem_4_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_opcode_0 = nodeOut_a_mem_5_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_param_0 = nodeOut_a_mem_5_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_size_0 = nodeOut_a_mem_5_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_source_0 = nodeOut_a_mem_5_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_address_0 = nodeOut_a_mem_5_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_mask_0 = nodeOut_a_mem_5_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_data_0 = nodeOut_a_mem_5_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_corrupt_0 = nodeOut_a_mem_5_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_opcode_0 = nodeOut_a_mem_6_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_param_0 = nodeOut_a_mem_6_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_size_0 = nodeOut_a_mem_6_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_source_0 = nodeOut_a_mem_6_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_address_0 = nodeOut_a_mem_6_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_mask_0 = nodeOut_a_mem_6_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_data_0 = nodeOut_a_mem_6_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_corrupt_0 = nodeOut_a_mem_6_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_opcode_0 = nodeOut_a_mem_7_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_param_0 = nodeOut_a_mem_7_param; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_size_0 = nodeOut_a_mem_7_size; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_source_0 = nodeOut_a_mem_7_source; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_address_0 = nodeOut_a_mem_7_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_mask_0 = nodeOut_a_mem_7_mask; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_data_0 = nodeOut_a_mem_7_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_corrupt_0 = nodeOut_a_mem_7_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
TLMonitor_10 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncQueueSource_TLBundleA_a32d64s5k3z4u nodeOut_a_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_async_mem_0_opcode (nodeOut_a_mem_0_opcode),
.io_async_mem_0_param (nodeOut_a_mem_0_param),
.io_async_mem_0_size (nodeOut_a_mem_0_size),
.io_async_mem_0_source (nodeOut_a_mem_0_source),
.io_async_mem_0_address (nodeOut_a_mem_0_address),
.io_async_mem_0_mask (nodeOut_a_mem_0_mask),
.io_async_mem_0_data (nodeOut_a_mem_0_data),
.io_async_mem_0_corrupt (nodeOut_a_mem_0_corrupt),
.io_async_mem_1_opcode (nodeOut_a_mem_1_opcode),
.io_async_mem_1_param (nodeOut_a_mem_1_param),
.io_async_mem_1_size (nodeOut_a_mem_1_size),
.io_async_mem_1_source (nodeOut_a_mem_1_source),
.io_async_mem_1_address (nodeOut_a_mem_1_address),
.io_async_mem_1_mask (nodeOut_a_mem_1_mask),
.io_async_mem_1_data (nodeOut_a_mem_1_data),
.io_async_mem_1_corrupt (nodeOut_a_mem_1_corrupt),
.io_async_mem_2_opcode (nodeOut_a_mem_2_opcode),
.io_async_mem_2_param (nodeOut_a_mem_2_param),
.io_async_mem_2_size (nodeOut_a_mem_2_size),
.io_async_mem_2_source (nodeOut_a_mem_2_source),
.io_async_mem_2_address (nodeOut_a_mem_2_address),
.io_async_mem_2_mask (nodeOut_a_mem_2_mask),
.io_async_mem_2_data (nodeOut_a_mem_2_data),
.io_async_mem_2_corrupt (nodeOut_a_mem_2_corrupt),
.io_async_mem_3_opcode (nodeOut_a_mem_3_opcode),
.io_async_mem_3_param (nodeOut_a_mem_3_param),
.io_async_mem_3_size (nodeOut_a_mem_3_size),
.io_async_mem_3_source (nodeOut_a_mem_3_source),
.io_async_mem_3_address (nodeOut_a_mem_3_address),
.io_async_mem_3_mask (nodeOut_a_mem_3_mask),
.io_async_mem_3_data (nodeOut_a_mem_3_data),
.io_async_mem_3_corrupt (nodeOut_a_mem_3_corrupt),
.io_async_mem_4_opcode (nodeOut_a_mem_4_opcode),
.io_async_mem_4_param (nodeOut_a_mem_4_param),
.io_async_mem_4_size (nodeOut_a_mem_4_size),
.io_async_mem_4_source (nodeOut_a_mem_4_source),
.io_async_mem_4_address (nodeOut_a_mem_4_address),
.io_async_mem_4_mask (nodeOut_a_mem_4_mask),
.io_async_mem_4_data (nodeOut_a_mem_4_data),
.io_async_mem_4_corrupt (nodeOut_a_mem_4_corrupt),
.io_async_mem_5_opcode (nodeOut_a_mem_5_opcode),
.io_async_mem_5_param (nodeOut_a_mem_5_param),
.io_async_mem_5_size (nodeOut_a_mem_5_size),
.io_async_mem_5_source (nodeOut_a_mem_5_source),
.io_async_mem_5_address (nodeOut_a_mem_5_address),
.io_async_mem_5_mask (nodeOut_a_mem_5_mask),
.io_async_mem_5_data (nodeOut_a_mem_5_data),
.io_async_mem_5_corrupt (nodeOut_a_mem_5_corrupt),
.io_async_mem_6_opcode (nodeOut_a_mem_6_opcode),
.io_async_mem_6_param (nodeOut_a_mem_6_param),
.io_async_mem_6_size (nodeOut_a_mem_6_size),
.io_async_mem_6_source (nodeOut_a_mem_6_source),
.io_async_mem_6_address (nodeOut_a_mem_6_address),
.io_async_mem_6_mask (nodeOut_a_mem_6_mask),
.io_async_mem_6_data (nodeOut_a_mem_6_data),
.io_async_mem_6_corrupt (nodeOut_a_mem_6_corrupt),
.io_async_mem_7_opcode (nodeOut_a_mem_7_opcode),
.io_async_mem_7_param (nodeOut_a_mem_7_param),
.io_async_mem_7_size (nodeOut_a_mem_7_size),
.io_async_mem_7_source (nodeOut_a_mem_7_source),
.io_async_mem_7_address (nodeOut_a_mem_7_address),
.io_async_mem_7_mask (nodeOut_a_mem_7_mask),
.io_async_mem_7_data (nodeOut_a_mem_7_data),
.io_async_mem_7_corrupt (nodeOut_a_mem_7_corrupt),
.io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_a_widx),
.io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_a_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSink_TLBundleD_a32d64s5k3z4u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt),
.io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_0_param (nodeOut_d_mem_0_param), // @[MixedNode.scala:542:17]
.io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17]
.io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17]
.io_async_mem_0_sink (nodeOut_d_mem_0_sink), // @[MixedNode.scala:542:17]
.io_async_mem_0_denied (nodeOut_d_mem_0_denied), // @[MixedNode.scala:542:17]
.io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17]
.io_async_mem_0_corrupt (nodeOut_d_mem_0_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_1_opcode (nodeOut_d_mem_1_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_1_param (nodeOut_d_mem_1_param), // @[MixedNode.scala:542:17]
.io_async_mem_1_size (nodeOut_d_mem_1_size), // @[MixedNode.scala:542:17]
.io_async_mem_1_source (nodeOut_d_mem_1_source), // @[MixedNode.scala:542:17]
.io_async_mem_1_sink (nodeOut_d_mem_1_sink), // @[MixedNode.scala:542:17]
.io_async_mem_1_denied (nodeOut_d_mem_1_denied), // @[MixedNode.scala:542:17]
.io_async_mem_1_data (nodeOut_d_mem_1_data), // @[MixedNode.scala:542:17]
.io_async_mem_1_corrupt (nodeOut_d_mem_1_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_2_opcode (nodeOut_d_mem_2_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_2_param (nodeOut_d_mem_2_param), // @[MixedNode.scala:542:17]
.io_async_mem_2_size (nodeOut_d_mem_2_size), // @[MixedNode.scala:542:17]
.io_async_mem_2_source (nodeOut_d_mem_2_source), // @[MixedNode.scala:542:17]
.io_async_mem_2_sink (nodeOut_d_mem_2_sink), // @[MixedNode.scala:542:17]
.io_async_mem_2_denied (nodeOut_d_mem_2_denied), // @[MixedNode.scala:542:17]
.io_async_mem_2_data (nodeOut_d_mem_2_data), // @[MixedNode.scala:542:17]
.io_async_mem_2_corrupt (nodeOut_d_mem_2_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_3_opcode (nodeOut_d_mem_3_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_3_param (nodeOut_d_mem_3_param), // @[MixedNode.scala:542:17]
.io_async_mem_3_size (nodeOut_d_mem_3_size), // @[MixedNode.scala:542:17]
.io_async_mem_3_source (nodeOut_d_mem_3_source), // @[MixedNode.scala:542:17]
.io_async_mem_3_sink (nodeOut_d_mem_3_sink), // @[MixedNode.scala:542:17]
.io_async_mem_3_denied (nodeOut_d_mem_3_denied), // @[MixedNode.scala:542:17]
.io_async_mem_3_data (nodeOut_d_mem_3_data), // @[MixedNode.scala:542:17]
.io_async_mem_3_corrupt (nodeOut_d_mem_3_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_4_opcode (nodeOut_d_mem_4_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_4_param (nodeOut_d_mem_4_param), // @[MixedNode.scala:542:17]
.io_async_mem_4_size (nodeOut_d_mem_4_size), // @[MixedNode.scala:542:17]
.io_async_mem_4_source (nodeOut_d_mem_4_source), // @[MixedNode.scala:542:17]
.io_async_mem_4_sink (nodeOut_d_mem_4_sink), // @[MixedNode.scala:542:17]
.io_async_mem_4_denied (nodeOut_d_mem_4_denied), // @[MixedNode.scala:542:17]
.io_async_mem_4_data (nodeOut_d_mem_4_data), // @[MixedNode.scala:542:17]
.io_async_mem_4_corrupt (nodeOut_d_mem_4_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_5_opcode (nodeOut_d_mem_5_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_5_param (nodeOut_d_mem_5_param), // @[MixedNode.scala:542:17]
.io_async_mem_5_size (nodeOut_d_mem_5_size), // @[MixedNode.scala:542:17]
.io_async_mem_5_source (nodeOut_d_mem_5_source), // @[MixedNode.scala:542:17]
.io_async_mem_5_sink (nodeOut_d_mem_5_sink), // @[MixedNode.scala:542:17]
.io_async_mem_5_denied (nodeOut_d_mem_5_denied), // @[MixedNode.scala:542:17]
.io_async_mem_5_data (nodeOut_d_mem_5_data), // @[MixedNode.scala:542:17]
.io_async_mem_5_corrupt (nodeOut_d_mem_5_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_6_opcode (nodeOut_d_mem_6_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_6_param (nodeOut_d_mem_6_param), // @[MixedNode.scala:542:17]
.io_async_mem_6_size (nodeOut_d_mem_6_size), // @[MixedNode.scala:542:17]
.io_async_mem_6_source (nodeOut_d_mem_6_source), // @[MixedNode.scala:542:17]
.io_async_mem_6_sink (nodeOut_d_mem_6_sink), // @[MixedNode.scala:542:17]
.io_async_mem_6_denied (nodeOut_d_mem_6_denied), // @[MixedNode.scala:542:17]
.io_async_mem_6_data (nodeOut_d_mem_6_data), // @[MixedNode.scala:542:17]
.io_async_mem_6_corrupt (nodeOut_d_mem_6_corrupt), // @[MixedNode.scala:542:17]
.io_async_mem_7_opcode (nodeOut_d_mem_7_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_7_param (nodeOut_d_mem_7_param), // @[MixedNode.scala:542:17]
.io_async_mem_7_size (nodeOut_d_mem_7_size), // @[MixedNode.scala:542:17]
.io_async_mem_7_source (nodeOut_d_mem_7_source), // @[MixedNode.scala:542:17]
.io_async_mem_7_sink (nodeOut_d_mem_7_sink), // @[MixedNode.scala:542:17]
.io_async_mem_7_denied (nodeOut_d_mem_7_denied), // @[MixedNode.scala:542:17]
.io_async_mem_7_data (nodeOut_d_mem_7_data), // @[MixedNode.scala:542:17]
.io_async_mem_7_corrupt (nodeOut_d_mem_7_corrupt), // @[MixedNode.scala:542:17]
.io_async_ridx (nodeOut_d_ridx),
.io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17]
.io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid),
.io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17]
.io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_param = auto_out_a_mem_0_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_size = auto_out_a_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_source = auto_out_a_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_mask = auto_out_a_mem_0_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_corrupt = auto_out_a_mem_0_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_opcode = auto_out_a_mem_1_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_param = auto_out_a_mem_1_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_size = auto_out_a_mem_1_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_source = auto_out_a_mem_1_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_address = auto_out_a_mem_1_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_mask = auto_out_a_mem_1_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_data = auto_out_a_mem_1_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_1_corrupt = auto_out_a_mem_1_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_opcode = auto_out_a_mem_2_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_param = auto_out_a_mem_2_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_size = auto_out_a_mem_2_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_source = auto_out_a_mem_2_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_address = auto_out_a_mem_2_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_mask = auto_out_a_mem_2_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_data = auto_out_a_mem_2_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_2_corrupt = auto_out_a_mem_2_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_opcode = auto_out_a_mem_3_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_param = auto_out_a_mem_3_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_size = auto_out_a_mem_3_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_source = auto_out_a_mem_3_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_address = auto_out_a_mem_3_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_mask = auto_out_a_mem_3_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_data = auto_out_a_mem_3_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_3_corrupt = auto_out_a_mem_3_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_opcode = auto_out_a_mem_4_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_param = auto_out_a_mem_4_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_size = auto_out_a_mem_4_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_source = auto_out_a_mem_4_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_address = auto_out_a_mem_4_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_mask = auto_out_a_mem_4_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_data = auto_out_a_mem_4_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_4_corrupt = auto_out_a_mem_4_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_opcode = auto_out_a_mem_5_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_param = auto_out_a_mem_5_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_size = auto_out_a_mem_5_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_source = auto_out_a_mem_5_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_address = auto_out_a_mem_5_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_mask = auto_out_a_mem_5_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_data = auto_out_a_mem_5_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_5_corrupt = auto_out_a_mem_5_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_opcode = auto_out_a_mem_6_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_param = auto_out_a_mem_6_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_size = auto_out_a_mem_6_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_source = auto_out_a_mem_6_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_address = auto_out_a_mem_6_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_mask = auto_out_a_mem_6_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_data = auto_out_a_mem_6_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_6_corrupt = auto_out_a_mem_6_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_opcode = auto_out_a_mem_7_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_param = auto_out_a_mem_7_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_size = auto_out_a_mem_7_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_source = auto_out_a_mem_7_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_address = auto_out_a_mem_7_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_mask = auto_out_a_mem_7_mask_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_data = auto_out_a_mem_7_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_7_corrupt = auto_out_a_mem_7_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_32( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_122( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_160( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_177 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Control.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) {
val ctrlnode = TLRegisterNode(
address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)),
device = outer.device,
concurrency = 1, // Only one flush at a time (else need to track who answers)
beatBytes = control.beatBytes)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val flush_match = Input(Bool())
val flush_req = Decoupled(UInt(64.W))
val flush_resp = Input(Bool())
})
// Flush directive
val flushInValid = RegInit(false.B)
val flushInAddress = Reg(UInt(64.W))
val flushOutValid = RegInit(false.B)
val flushOutReady = WireInit(init = false.B)
when (flushOutReady) { flushOutValid := false.B }
when (io.flush_resp) { flushOutValid := true.B }
when (io.flush_req.ready) { flushInValid := false.B }
io.flush_req.valid := flushInValid
io.flush_req.bits := flushInAddress
when (!io.flush_match && flushInValid) {
flushInValid := false.B
flushOutValid := true.B
}
val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data << 4 }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache"))
val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache"))
// Information about the cache configuration
val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks",
"Number of banks in the cache", reset=Some(outer.node.edges.in.size)))
val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways",
"Number of ways per bank", reset=Some(outer.cache.ways)))
val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets",
"Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets))))
val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes",
"Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes))))
val regmap = ctrlnode.regmap(
0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)),
0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil),
0x240 -> Seq(flush32)
)
}
}
| module InclusiveCacheControl( // @[Control.scala:38:9]
input clock, // @[Control.scala:38:9]
input reset, // @[Control.scala:38:9]
output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_flush_match, // @[Control.scala:39:16]
input io_flush_req_ready, // @[Control.scala:39:16]
output io_flush_req_valid, // @[Control.scala:39:16]
output [63:0] io_flush_req_bits, // @[Control.scala:39:16]
input io_flush_resp // @[Control.scala:39:16]
);
wire _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
wire out_backSel_3; // @[RegisterRouter.scala:87:24]
wire out_backSel_2; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_enq_ready; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_back_front_q_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801};
reg flushInValid; // @[Control.scala:45:33]
reg [63:0] flushInAddress; // @[Control.scala:46:29]
reg flushOutValid; // @[Control.scala:47:33]
wire in_bits_read = auto_ctrl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
wire _out_T_5 = {_out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]} == 7'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{auto_ctrl_in_a_bits_mask[0]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{auto_ctrl_in_a_bits_mask[1]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{auto_ctrl_in_a_bits_mask[2]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{auto_ctrl_in_a_bits_mask[3]}}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {{8{auto_ctrl_in_a_bits_mask[7]}}, {8{auto_ctrl_in_a_bits_mask[6]}}, {8{auto_ctrl_in_a_bits_mask[5]}}, {8{auto_ctrl_in_a_bits_mask[4]}}, _out_frontMask_T_11, _out_frontMask_T_10, _out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_back_front_q_io_deq_bits_mask[0]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_back_front_q_io_deq_bits_mask[1]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_back_front_q_io_deq_bits_mask[2]}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_back_front_q_io_deq_bits_mask[3]}}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {{8{_out_back_front_q_io_deq_bits_mask[7]}}, {8{_out_back_front_q_io_deq_bits_mask[6]}}, {8{_out_back_front_q_io_deq_bits_mask[5]}}, {8{_out_back_front_q_io_deq_bits_mask[4]}}, _out_backMask_T_11, _out_backMask_T_10, _out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_5 = {_out_frontMask_T_11, _out_frontMask_T_10, _out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_5 = {_out_backMask_T_11, _out_backMask_T_10, _out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_back_front_q_io_deq_bits_index[6], _out_back_front_q_io_deq_bits_index[3]}; // @[RegisterRouter.scala:87:24]
wire [1:0] _GEN_0 = {auto_ctrl_in_a_bits_address[9], auto_ctrl_in_a_bits_address[6]}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_1 = {_out_back_front_q_io_deq_bits_index[6], _out_back_front_q_io_deq_bits_index[3]}; // @[OneHot.scala:58:35]
assign out_backSel_2 = _GEN_1 == 2'h2; // @[OneHot.scala:58:35]
assign out_backSel_3 = &_GEN_1; // @[OneHot.scala:58:35]
wire _out_wifireMux_T_2 = auto_ctrl_in_a_valid & _out_back_front_q_io_enq_ready & ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24]
wire [3:0] _GEN_2 = {{|{~flushInValid | ~(&_out_wimask_T_5), auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]}}, {|{~flushInValid | ~(&out_frontMask), auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]}}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:10]
assign _out_wofireMux_T_2 = _out_back_front_q_io_deq_valid & auto_ctrl_in_d_ready & ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_3 = {{|{flushOutValid | ~(&_out_womask_T_5), _out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]}}, {|{flushOutValid | ~(&out_backMask), _out_back_front_q_io_deq_bits_index[8:7], _out_back_front_q_io_deq_bits_index[5:4], _out_back_front_q_io_deq_bits_index[2:0]}}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:10]
wire out_iready = in_bits_read | _GEN_2[{auto_ctrl_in_a_bits_address[9], auto_ctrl_in_a_bits_address[6]}]; // @[MuxLiteral.scala:49:10]
wire out_oready = _out_back_front_q_io_deq_bits_read | _GEN_3[out_oindex]; // @[MuxLiteral.scala:49:10]
wire in_ready = _out_back_front_q_io_enq_ready & out_iready; // @[RegisterRouter.scala:87:24]
wire out_valid = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_T_5}, {_out_T_5}, {1'h1}, {_out_T_5}}; // @[MuxLiteral.scala:49:10]
wire [2:0] ctrlnodeIn_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read}; // @[RegisterRouter.scala:87:24, :105:19]
wire _GEN_5 = ~io_flush_match & flushInValid; // @[Control.scala:45:33, :56:{11,27}]
wire _out_T_4 = {auto_ctrl_in_a_bits_address[11:10], auto_ctrl_in_a_bits_address[8:7], auto_ctrl_in_a_bits_address[5:3]} == 7'h0; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = _out_wifireMux_T_2 & _GEN_0 == 2'h2 & _out_T_4 & (&out_frontMask); // @[OneHot.scala:58:35]
wire out_f_wivalid_5 = _out_wifireMux_T_2 & (&_GEN_0) & _out_T_4 & (&_out_wimask_T_5); // @[OneHot.scala:58:35]
always @(posedge clock) begin // @[Control.scala:38:9]
if (reset) begin // @[Control.scala:38:9]
flushInValid <= 1'h0; // @[Control.scala:45:33]
flushOutValid <= 1'h0; // @[Control.scala:47:33]
end
else begin // @[Control.scala:38:9]
flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_GEN_5 | io_flush_req_ready) & flushInValid; // @[RegisterRouter.scala:87:24]
flushOutValid <= _GEN_5 | io_flush_resp | ~(_out_wofireMux_T_2 & out_backSel_3 & _out_T_5 & (&_out_womask_T_5) | _out_wofireMux_T_2 & out_backSel_2 & _out_T_5 & (&out_backMask)) & flushOutValid; // @[RegisterRouter.scala:87:24]
end
if (out_f_wivalid_5 & ~flushInValid) // @[RegisterRouter.scala:87:24]
flushInAddress <= {28'h0, auto_ctrl_in_a_bits_data[31:0], 4'h0}; // @[RegisterRouter.scala:87:24]
else if (out_f_wivalid_4 & ~flushInValid) // @[RegisterRouter.scala:87:24]
flushInAddress <= auto_ctrl_in_a_bits_data; // @[Control.scala:46:29]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_13( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [4:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [4:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [4:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [4:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [4:0] io_schedule_bits_a_bits_source = 5'h0; // @[MSHR.scala:84:7]
wire [4:0] io_schedule_bits_c_bits_source = 5'h0; // @[MSHR.scala:84:7]
wire [4:0] io_schedule_bits_d_bits_sink = 5'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [7:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 8'h40; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 8'h40; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 8'h40; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_85( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File CLINT.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.Annotated
object CLINTConsts
{
def msipOffset(hart: Int) = hart * msipBytes
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
def timeOffset = 0xbff8
def msipBytes = 4
def timecmpBytes = 8
def size = 0x10000
def timeWidth = 64
def ipiWidth = 32
def ints = 2
}
case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
{
def address = AddressSet(baseAddress, CLINTConsts.size-1)
}
case object CLINTKey extends Field[Option[CLINTParams]](None)
case class CLINTAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object CLINTAttachKey extends Field(CLINTAttachParams())
class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
import CLINTConsts._
// clint0 => at most 4095 devices
val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
override val alwaysExtended = true
}
val node: TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes)
val intnode : IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
val io = IO(new Bundle {
val rtcTick = Input(Bool())
})
val time = RegInit(0.U(timeWidth.W))
when (io.rtcTick) { time := time + 1.U }
val nTiles = intnode.out.size
val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) }
val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
val (intnode_out, _) = intnode.out.unzip
intnode_out.zipWithIndex.foreach { case (int, i) =>
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}
/* 0000 msip hart 0
* 0004 msip hart 1
* 4000 mtimecmp hart 0 lo
* 4004 mtimecmp hart 0 hi
* 4008 mtimecmp hart 1 lo
* 400c mtimecmp hart 1 hi
* bff8 mtime lo
* bffc mtime hi
*/
node.regmap(
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),
RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
)
}
}
/** Trait that will connect a CLINT to a subsystem */
trait CanHavePeripheryCLINT { this: BaseSubsystem =>
val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } }
val clintTick = clintDomainWrapper { InModuleBody {
val tick = IO(Input(Bool()))
clint.module.io.rtcTick := tick
tick
}}
(clint, clintDomainWrapper, clintTick)
}.unzip3
}
| module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25]
input tick, // @[CLINT.scala:115:20]
output clock, // @[ClockDomain.scala:21:19]
output reset // @[ClockDomain.scala:22:19]
);
wire _clint_auto_int_out_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_1; // @[CLINT.scala:112:48]
wire auto_clint_in_a_valid_0 = auto_clint_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_a_bits_opcode_0 = auto_clint_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_a_bits_param_0 = auto_clint_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_a_bits_size_0 = auto_clint_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [13:0] auto_clint_in_a_bits_source_0 = auto_clint_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_clint_in_a_bits_address_0 = auto_clint_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_clint_in_a_bits_mask_0 = auto_clint_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_clint_in_a_bits_data_0 = auto_clint_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_clint_in_a_bits_corrupt_0 = auto_clint_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_ready_0 = auto_clint_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [13:0] auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_1_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_1_0 = intInClockXingOut_sync_1; // @[ClockDomain.scala:14:9]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
CLINT clint ( // @[CLINT.scala:112:48]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_int_out_0 (_clint_auto_int_out_0),
.auto_int_out_1 (_clint_auto_int_out_1),
.auto_in_a_ready (auto_clint_in_a_ready_0),
.auto_in_a_valid (auto_clint_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_clint_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_clint_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_clint_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_clint_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_clint_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_clint_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_clint_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_clint_in_d_valid_0),
.auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode_0),
.auto_in_d_bits_size (auto_clint_in_d_bits_size_0),
.auto_in_d_bits_source (auto_clint_in_d_bits_source_0),
.auto_in_d_bits_data (auto_clint_in_d_bits_data_0),
.io_rtcTick (tick)
); // @[CLINT.scala:112:48]
IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (_clint_auto_int_out_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (intInClockXingIn_sync_0),
.auto_out_sync_1 (intInClockXingIn_sync_1)
); // @[Crossing.scala:29:31]
assign auto_clint_in_a_ready = auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_valid = auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_opcode = auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_size = auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_source = auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_data = auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_0 = auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_1 = auto_int_in_clock_xing_out_sync_1_0; // @[ClockDomain.scala:14:9]
assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9]
assign reset = clockNodeIn_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_114( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillableQueue_6( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [64:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_fflags_valid, // @[util.scala:463:14]
input [4:0] io_enq_bits_fflags_bits, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [64:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_predicated, // @[util.scala:463:14]
output io_deq_bits_fflags_valid, // @[util.scala:463:14]
output [4:0] io_deq_bits_fflags_bits, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output [3:0] io_count // @[util.scala:463:14]
);
wire [71:0] _ram_ext_R0_data; // @[util.scala:503:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [64:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_fflags_valid_0 = io_enq_bits_fflags_valid; // @[util.scala:458:7]
wire [4:0] io_enq_bits_fflags_bits_0 = io_enq_bits_fflags_bits; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire io_enq_bits_predicated = 1'h0; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:504:34]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [39:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire [1:0] out_uop_dis_col_sel; // @[util.scala:545:19]
wire [11:0] out_uop_br_mask; // @[util.scala:545:19]
wire [3:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [5:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [3:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [6:0] out_uop_pdst; // @[util.scala:545:19]
wire [6:0] out_uop_prs1; // @[util.scala:545:19]
wire [6:0] out_uop_prs2; // @[util.scala:545:19]
wire [6:0] out_uop_prs3; // @[util.scala:545:19]
wire [4:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [64:0] out_data; // @[util.scala:545:19]
wire out_predicated; // @[util.scala:545:19]
wire out_fflags_valid; // @[util.scala:545:19]
wire [4:0] out_fflags_bits; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire _do_enq_T_6 = io_flush_0; // @[util.scala:458:7, :514:113]
wire _valids_0_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_1_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_2_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_3_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_4_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_5_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_6_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_7_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_8_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_9_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire [3:0] _io_count_T_5; // @[util.scala:556:22]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire io_deq_bits_fflags_valid_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_fflags_bits_0; // @[util.scala:458:7]
wire [64:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_predicated_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty; // @[util.scala:458:7]
wire [3:0] io_count_0; // @[util.scala:458:7]
assign out_data = _ram_ext_R0_data[64:0]; // @[util.scala:503:22, :545:19]
assign out_predicated = _ram_ext_R0_data[65]; // @[util.scala:503:22, :545:19]
assign out_fflags_valid = _ram_ext_R0_data[66]; // @[util.scala:503:22, :545:19]
assign out_fflags_bits = _ram_ext_R0_data[71:67]; // @[util.scala:503:22, :545:19]
reg valids_0; // @[util.scala:504:26]
reg valids_1; // @[util.scala:504:26]
reg valids_2; // @[util.scala:504:26]
reg valids_3; // @[util.scala:504:26]
reg valids_4; // @[util.scala:504:26]
reg valids_5; // @[util.scala:504:26]
reg valids_6; // @[util.scala:504:26]
reg valids_7; // @[util.scala:504:26]
reg valids_8; // @[util.scala:504:26]
reg valids_9; // @[util.scala:504:26]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_0_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_0_br_mask; // @[util.scala:505:22]
reg [3:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_0_pdst; // @[util.scala:505:22]
reg [6:0] uops_0_prs1; // @[util.scala:505:22]
reg [6:0] uops_0_prs2; // @[util.scala:505:22]
reg [6:0] uops_0_prs3; // @[util.scala:505:22]
reg [4:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_1_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_1_br_mask; // @[util.scala:505:22]
reg [3:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_1_pdst; // @[util.scala:505:22]
reg [6:0] uops_1_prs1; // @[util.scala:505:22]
reg [6:0] uops_1_prs2; // @[util.scala:505:22]
reg [6:0] uops_1_prs3; // @[util.scala:505:22]
reg [4:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_2_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_2_br_mask; // @[util.scala:505:22]
reg [3:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_2_pdst; // @[util.scala:505:22]
reg [6:0] uops_2_prs1; // @[util.scala:505:22]
reg [6:0] uops_2_prs2; // @[util.scala:505:22]
reg [6:0] uops_2_prs3; // @[util.scala:505:22]
reg [4:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_3_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_3_br_mask; // @[util.scala:505:22]
reg [3:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_3_pdst; // @[util.scala:505:22]
reg [6:0] uops_3_prs1; // @[util.scala:505:22]
reg [6:0] uops_3_prs2; // @[util.scala:505:22]
reg [6:0] uops_3_prs3; // @[util.scala:505:22]
reg [4:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_4_inst; // @[util.scala:505:22]
reg [31:0] uops_4_debug_inst; // @[util.scala:505:22]
reg uops_4_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_4_debug_pc; // @[util.scala:505:22]
reg uops_4_iq_type_0; // @[util.scala:505:22]
reg uops_4_iq_type_1; // @[util.scala:505:22]
reg uops_4_iq_type_2; // @[util.scala:505:22]
reg uops_4_iq_type_3; // @[util.scala:505:22]
reg uops_4_fu_code_0; // @[util.scala:505:22]
reg uops_4_fu_code_1; // @[util.scala:505:22]
reg uops_4_fu_code_2; // @[util.scala:505:22]
reg uops_4_fu_code_3; // @[util.scala:505:22]
reg uops_4_fu_code_4; // @[util.scala:505:22]
reg uops_4_fu_code_5; // @[util.scala:505:22]
reg uops_4_fu_code_6; // @[util.scala:505:22]
reg uops_4_fu_code_7; // @[util.scala:505:22]
reg uops_4_fu_code_8; // @[util.scala:505:22]
reg uops_4_fu_code_9; // @[util.scala:505:22]
reg uops_4_iw_issued; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_4_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_4_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_4_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_4_br_mask; // @[util.scala:505:22]
reg [3:0] uops_4_br_tag; // @[util.scala:505:22]
reg [3:0] uops_4_br_type; // @[util.scala:505:22]
reg uops_4_is_sfb; // @[util.scala:505:22]
reg uops_4_is_fence; // @[util.scala:505:22]
reg uops_4_is_fencei; // @[util.scala:505:22]
reg uops_4_is_sfence; // @[util.scala:505:22]
reg uops_4_is_amo; // @[util.scala:505:22]
reg uops_4_is_eret; // @[util.scala:505:22]
reg uops_4_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_4_is_rocc; // @[util.scala:505:22]
reg uops_4_is_mov; // @[util.scala:505:22]
reg [4:0] uops_4_ftq_idx; // @[util.scala:505:22]
reg uops_4_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_4_pc_lob; // @[util.scala:505:22]
reg uops_4_taken; // @[util.scala:505:22]
reg uops_4_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_4_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_4_pimm; // @[util.scala:505:22]
reg [19:0] uops_4_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_4_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_4_op2_sel; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_4_fp_ctrl_div; // @[util.scala:505:22]
reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_4_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_4_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_4_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_4_pdst; // @[util.scala:505:22]
reg [6:0] uops_4_prs1; // @[util.scala:505:22]
reg [6:0] uops_4_prs2; // @[util.scala:505:22]
reg [6:0] uops_4_prs3; // @[util.scala:505:22]
reg [4:0] uops_4_ppred; // @[util.scala:505:22]
reg uops_4_prs1_busy; // @[util.scala:505:22]
reg uops_4_prs2_busy; // @[util.scala:505:22]
reg uops_4_prs3_busy; // @[util.scala:505:22]
reg uops_4_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_4_stale_pdst; // @[util.scala:505:22]
reg uops_4_exception; // @[util.scala:505:22]
reg [63:0] uops_4_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_4_mem_size; // @[util.scala:505:22]
reg uops_4_mem_signed; // @[util.scala:505:22]
reg uops_4_uses_ldq; // @[util.scala:505:22]
reg uops_4_uses_stq; // @[util.scala:505:22]
reg uops_4_is_unique; // @[util.scala:505:22]
reg uops_4_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22]
reg uops_4_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_4_ldst; // @[util.scala:505:22]
reg [5:0] uops_4_lrs1; // @[util.scala:505:22]
reg [5:0] uops_4_lrs2; // @[util.scala:505:22]
reg [5:0] uops_4_lrs3; // @[util.scala:505:22]
reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22]
reg uops_4_frs3_en; // @[util.scala:505:22]
reg uops_4_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_4_fcn_op; // @[util.scala:505:22]
reg uops_4_fp_val; // @[util.scala:505:22]
reg [2:0] uops_4_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_4_fp_typ; // @[util.scala:505:22]
reg uops_4_xcpt_pf_if; // @[util.scala:505:22]
reg uops_4_xcpt_ae_if; // @[util.scala:505:22]
reg uops_4_xcpt_ma_if; // @[util.scala:505:22]
reg uops_4_bp_debug_if; // @[util.scala:505:22]
reg uops_4_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_5_inst; // @[util.scala:505:22]
reg [31:0] uops_5_debug_inst; // @[util.scala:505:22]
reg uops_5_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_5_debug_pc; // @[util.scala:505:22]
reg uops_5_iq_type_0; // @[util.scala:505:22]
reg uops_5_iq_type_1; // @[util.scala:505:22]
reg uops_5_iq_type_2; // @[util.scala:505:22]
reg uops_5_iq_type_3; // @[util.scala:505:22]
reg uops_5_fu_code_0; // @[util.scala:505:22]
reg uops_5_fu_code_1; // @[util.scala:505:22]
reg uops_5_fu_code_2; // @[util.scala:505:22]
reg uops_5_fu_code_3; // @[util.scala:505:22]
reg uops_5_fu_code_4; // @[util.scala:505:22]
reg uops_5_fu_code_5; // @[util.scala:505:22]
reg uops_5_fu_code_6; // @[util.scala:505:22]
reg uops_5_fu_code_7; // @[util.scala:505:22]
reg uops_5_fu_code_8; // @[util.scala:505:22]
reg uops_5_fu_code_9; // @[util.scala:505:22]
reg uops_5_iw_issued; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_5_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_5_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_5_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_5_br_mask; // @[util.scala:505:22]
reg [3:0] uops_5_br_tag; // @[util.scala:505:22]
reg [3:0] uops_5_br_type; // @[util.scala:505:22]
reg uops_5_is_sfb; // @[util.scala:505:22]
reg uops_5_is_fence; // @[util.scala:505:22]
reg uops_5_is_fencei; // @[util.scala:505:22]
reg uops_5_is_sfence; // @[util.scala:505:22]
reg uops_5_is_amo; // @[util.scala:505:22]
reg uops_5_is_eret; // @[util.scala:505:22]
reg uops_5_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_5_is_rocc; // @[util.scala:505:22]
reg uops_5_is_mov; // @[util.scala:505:22]
reg [4:0] uops_5_ftq_idx; // @[util.scala:505:22]
reg uops_5_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_5_pc_lob; // @[util.scala:505:22]
reg uops_5_taken; // @[util.scala:505:22]
reg uops_5_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_5_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_5_pimm; // @[util.scala:505:22]
reg [19:0] uops_5_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_5_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_5_op2_sel; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_5_fp_ctrl_div; // @[util.scala:505:22]
reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_5_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_5_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_5_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_5_pdst; // @[util.scala:505:22]
reg [6:0] uops_5_prs1; // @[util.scala:505:22]
reg [6:0] uops_5_prs2; // @[util.scala:505:22]
reg [6:0] uops_5_prs3; // @[util.scala:505:22]
reg [4:0] uops_5_ppred; // @[util.scala:505:22]
reg uops_5_prs1_busy; // @[util.scala:505:22]
reg uops_5_prs2_busy; // @[util.scala:505:22]
reg uops_5_prs3_busy; // @[util.scala:505:22]
reg uops_5_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_5_stale_pdst; // @[util.scala:505:22]
reg uops_5_exception; // @[util.scala:505:22]
reg [63:0] uops_5_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_5_mem_size; // @[util.scala:505:22]
reg uops_5_mem_signed; // @[util.scala:505:22]
reg uops_5_uses_ldq; // @[util.scala:505:22]
reg uops_5_uses_stq; // @[util.scala:505:22]
reg uops_5_is_unique; // @[util.scala:505:22]
reg uops_5_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22]
reg uops_5_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_5_ldst; // @[util.scala:505:22]
reg [5:0] uops_5_lrs1; // @[util.scala:505:22]
reg [5:0] uops_5_lrs2; // @[util.scala:505:22]
reg [5:0] uops_5_lrs3; // @[util.scala:505:22]
reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22]
reg uops_5_frs3_en; // @[util.scala:505:22]
reg uops_5_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_5_fcn_op; // @[util.scala:505:22]
reg uops_5_fp_val; // @[util.scala:505:22]
reg [2:0] uops_5_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_5_fp_typ; // @[util.scala:505:22]
reg uops_5_xcpt_pf_if; // @[util.scala:505:22]
reg uops_5_xcpt_ae_if; // @[util.scala:505:22]
reg uops_5_xcpt_ma_if; // @[util.scala:505:22]
reg uops_5_bp_debug_if; // @[util.scala:505:22]
reg uops_5_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_6_inst; // @[util.scala:505:22]
reg [31:0] uops_6_debug_inst; // @[util.scala:505:22]
reg uops_6_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_6_debug_pc; // @[util.scala:505:22]
reg uops_6_iq_type_0; // @[util.scala:505:22]
reg uops_6_iq_type_1; // @[util.scala:505:22]
reg uops_6_iq_type_2; // @[util.scala:505:22]
reg uops_6_iq_type_3; // @[util.scala:505:22]
reg uops_6_fu_code_0; // @[util.scala:505:22]
reg uops_6_fu_code_1; // @[util.scala:505:22]
reg uops_6_fu_code_2; // @[util.scala:505:22]
reg uops_6_fu_code_3; // @[util.scala:505:22]
reg uops_6_fu_code_4; // @[util.scala:505:22]
reg uops_6_fu_code_5; // @[util.scala:505:22]
reg uops_6_fu_code_6; // @[util.scala:505:22]
reg uops_6_fu_code_7; // @[util.scala:505:22]
reg uops_6_fu_code_8; // @[util.scala:505:22]
reg uops_6_fu_code_9; // @[util.scala:505:22]
reg uops_6_iw_issued; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_6_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_6_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_6_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_6_br_mask; // @[util.scala:505:22]
reg [3:0] uops_6_br_tag; // @[util.scala:505:22]
reg [3:0] uops_6_br_type; // @[util.scala:505:22]
reg uops_6_is_sfb; // @[util.scala:505:22]
reg uops_6_is_fence; // @[util.scala:505:22]
reg uops_6_is_fencei; // @[util.scala:505:22]
reg uops_6_is_sfence; // @[util.scala:505:22]
reg uops_6_is_amo; // @[util.scala:505:22]
reg uops_6_is_eret; // @[util.scala:505:22]
reg uops_6_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_6_is_rocc; // @[util.scala:505:22]
reg uops_6_is_mov; // @[util.scala:505:22]
reg [4:0] uops_6_ftq_idx; // @[util.scala:505:22]
reg uops_6_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_6_pc_lob; // @[util.scala:505:22]
reg uops_6_taken; // @[util.scala:505:22]
reg uops_6_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_6_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_6_pimm; // @[util.scala:505:22]
reg [19:0] uops_6_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_6_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_6_op2_sel; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_6_fp_ctrl_div; // @[util.scala:505:22]
reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_6_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_6_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_6_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_6_pdst; // @[util.scala:505:22]
reg [6:0] uops_6_prs1; // @[util.scala:505:22]
reg [6:0] uops_6_prs2; // @[util.scala:505:22]
reg [6:0] uops_6_prs3; // @[util.scala:505:22]
reg [4:0] uops_6_ppred; // @[util.scala:505:22]
reg uops_6_prs1_busy; // @[util.scala:505:22]
reg uops_6_prs2_busy; // @[util.scala:505:22]
reg uops_6_prs3_busy; // @[util.scala:505:22]
reg uops_6_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_6_stale_pdst; // @[util.scala:505:22]
reg uops_6_exception; // @[util.scala:505:22]
reg [63:0] uops_6_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_6_mem_size; // @[util.scala:505:22]
reg uops_6_mem_signed; // @[util.scala:505:22]
reg uops_6_uses_ldq; // @[util.scala:505:22]
reg uops_6_uses_stq; // @[util.scala:505:22]
reg uops_6_is_unique; // @[util.scala:505:22]
reg uops_6_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22]
reg uops_6_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_6_ldst; // @[util.scala:505:22]
reg [5:0] uops_6_lrs1; // @[util.scala:505:22]
reg [5:0] uops_6_lrs2; // @[util.scala:505:22]
reg [5:0] uops_6_lrs3; // @[util.scala:505:22]
reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22]
reg uops_6_frs3_en; // @[util.scala:505:22]
reg uops_6_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_6_fcn_op; // @[util.scala:505:22]
reg uops_6_fp_val; // @[util.scala:505:22]
reg [2:0] uops_6_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_6_fp_typ; // @[util.scala:505:22]
reg uops_6_xcpt_pf_if; // @[util.scala:505:22]
reg uops_6_xcpt_ae_if; // @[util.scala:505:22]
reg uops_6_xcpt_ma_if; // @[util.scala:505:22]
reg uops_6_bp_debug_if; // @[util.scala:505:22]
reg uops_6_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_7_inst; // @[util.scala:505:22]
reg [31:0] uops_7_debug_inst; // @[util.scala:505:22]
reg uops_7_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_7_debug_pc; // @[util.scala:505:22]
reg uops_7_iq_type_0; // @[util.scala:505:22]
reg uops_7_iq_type_1; // @[util.scala:505:22]
reg uops_7_iq_type_2; // @[util.scala:505:22]
reg uops_7_iq_type_3; // @[util.scala:505:22]
reg uops_7_fu_code_0; // @[util.scala:505:22]
reg uops_7_fu_code_1; // @[util.scala:505:22]
reg uops_7_fu_code_2; // @[util.scala:505:22]
reg uops_7_fu_code_3; // @[util.scala:505:22]
reg uops_7_fu_code_4; // @[util.scala:505:22]
reg uops_7_fu_code_5; // @[util.scala:505:22]
reg uops_7_fu_code_6; // @[util.scala:505:22]
reg uops_7_fu_code_7; // @[util.scala:505:22]
reg uops_7_fu_code_8; // @[util.scala:505:22]
reg uops_7_fu_code_9; // @[util.scala:505:22]
reg uops_7_iw_issued; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_7_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_7_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_7_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_7_br_mask; // @[util.scala:505:22]
reg [3:0] uops_7_br_tag; // @[util.scala:505:22]
reg [3:0] uops_7_br_type; // @[util.scala:505:22]
reg uops_7_is_sfb; // @[util.scala:505:22]
reg uops_7_is_fence; // @[util.scala:505:22]
reg uops_7_is_fencei; // @[util.scala:505:22]
reg uops_7_is_sfence; // @[util.scala:505:22]
reg uops_7_is_amo; // @[util.scala:505:22]
reg uops_7_is_eret; // @[util.scala:505:22]
reg uops_7_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_7_is_rocc; // @[util.scala:505:22]
reg uops_7_is_mov; // @[util.scala:505:22]
reg [4:0] uops_7_ftq_idx; // @[util.scala:505:22]
reg uops_7_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_7_pc_lob; // @[util.scala:505:22]
reg uops_7_taken; // @[util.scala:505:22]
reg uops_7_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_7_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_7_pimm; // @[util.scala:505:22]
reg [19:0] uops_7_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_7_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_7_op2_sel; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_7_fp_ctrl_div; // @[util.scala:505:22]
reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_7_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_7_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_7_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_7_pdst; // @[util.scala:505:22]
reg [6:0] uops_7_prs1; // @[util.scala:505:22]
reg [6:0] uops_7_prs2; // @[util.scala:505:22]
reg [6:0] uops_7_prs3; // @[util.scala:505:22]
reg [4:0] uops_7_ppred; // @[util.scala:505:22]
reg uops_7_prs1_busy; // @[util.scala:505:22]
reg uops_7_prs2_busy; // @[util.scala:505:22]
reg uops_7_prs3_busy; // @[util.scala:505:22]
reg uops_7_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_7_stale_pdst; // @[util.scala:505:22]
reg uops_7_exception; // @[util.scala:505:22]
reg [63:0] uops_7_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_7_mem_size; // @[util.scala:505:22]
reg uops_7_mem_signed; // @[util.scala:505:22]
reg uops_7_uses_ldq; // @[util.scala:505:22]
reg uops_7_uses_stq; // @[util.scala:505:22]
reg uops_7_is_unique; // @[util.scala:505:22]
reg uops_7_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22]
reg uops_7_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_7_ldst; // @[util.scala:505:22]
reg [5:0] uops_7_lrs1; // @[util.scala:505:22]
reg [5:0] uops_7_lrs2; // @[util.scala:505:22]
reg [5:0] uops_7_lrs3; // @[util.scala:505:22]
reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22]
reg uops_7_frs3_en; // @[util.scala:505:22]
reg uops_7_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_7_fcn_op; // @[util.scala:505:22]
reg uops_7_fp_val; // @[util.scala:505:22]
reg [2:0] uops_7_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_7_fp_typ; // @[util.scala:505:22]
reg uops_7_xcpt_pf_if; // @[util.scala:505:22]
reg uops_7_xcpt_ae_if; // @[util.scala:505:22]
reg uops_7_xcpt_ma_if; // @[util.scala:505:22]
reg uops_7_bp_debug_if; // @[util.scala:505:22]
reg uops_7_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_8_inst; // @[util.scala:505:22]
reg [31:0] uops_8_debug_inst; // @[util.scala:505:22]
reg uops_8_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_8_debug_pc; // @[util.scala:505:22]
reg uops_8_iq_type_0; // @[util.scala:505:22]
reg uops_8_iq_type_1; // @[util.scala:505:22]
reg uops_8_iq_type_2; // @[util.scala:505:22]
reg uops_8_iq_type_3; // @[util.scala:505:22]
reg uops_8_fu_code_0; // @[util.scala:505:22]
reg uops_8_fu_code_1; // @[util.scala:505:22]
reg uops_8_fu_code_2; // @[util.scala:505:22]
reg uops_8_fu_code_3; // @[util.scala:505:22]
reg uops_8_fu_code_4; // @[util.scala:505:22]
reg uops_8_fu_code_5; // @[util.scala:505:22]
reg uops_8_fu_code_6; // @[util.scala:505:22]
reg uops_8_fu_code_7; // @[util.scala:505:22]
reg uops_8_fu_code_8; // @[util.scala:505:22]
reg uops_8_fu_code_9; // @[util.scala:505:22]
reg uops_8_iw_issued; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_8_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_8_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_8_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_8_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_8_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_8_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_8_br_mask; // @[util.scala:505:22]
reg [3:0] uops_8_br_tag; // @[util.scala:505:22]
reg [3:0] uops_8_br_type; // @[util.scala:505:22]
reg uops_8_is_sfb; // @[util.scala:505:22]
reg uops_8_is_fence; // @[util.scala:505:22]
reg uops_8_is_fencei; // @[util.scala:505:22]
reg uops_8_is_sfence; // @[util.scala:505:22]
reg uops_8_is_amo; // @[util.scala:505:22]
reg uops_8_is_eret; // @[util.scala:505:22]
reg uops_8_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_8_is_rocc; // @[util.scala:505:22]
reg uops_8_is_mov; // @[util.scala:505:22]
reg [4:0] uops_8_ftq_idx; // @[util.scala:505:22]
reg uops_8_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_8_pc_lob; // @[util.scala:505:22]
reg uops_8_taken; // @[util.scala:505:22]
reg uops_8_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_8_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_8_pimm; // @[util.scala:505:22]
reg [19:0] uops_8_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_8_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_8_op2_sel; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_8_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_8_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_8_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_8_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_8_fp_ctrl_div; // @[util.scala:505:22]
reg uops_8_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_8_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_8_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_8_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_8_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_8_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_8_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_8_pdst; // @[util.scala:505:22]
reg [6:0] uops_8_prs1; // @[util.scala:505:22]
reg [6:0] uops_8_prs2; // @[util.scala:505:22]
reg [6:0] uops_8_prs3; // @[util.scala:505:22]
reg [4:0] uops_8_ppred; // @[util.scala:505:22]
reg uops_8_prs1_busy; // @[util.scala:505:22]
reg uops_8_prs2_busy; // @[util.scala:505:22]
reg uops_8_prs3_busy; // @[util.scala:505:22]
reg uops_8_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_8_stale_pdst; // @[util.scala:505:22]
reg uops_8_exception; // @[util.scala:505:22]
reg [63:0] uops_8_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_8_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_8_mem_size; // @[util.scala:505:22]
reg uops_8_mem_signed; // @[util.scala:505:22]
reg uops_8_uses_ldq; // @[util.scala:505:22]
reg uops_8_uses_stq; // @[util.scala:505:22]
reg uops_8_is_unique; // @[util.scala:505:22]
reg uops_8_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_8_csr_cmd; // @[util.scala:505:22]
reg uops_8_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_8_ldst; // @[util.scala:505:22]
reg [5:0] uops_8_lrs1; // @[util.scala:505:22]
reg [5:0] uops_8_lrs2; // @[util.scala:505:22]
reg [5:0] uops_8_lrs3; // @[util.scala:505:22]
reg [1:0] uops_8_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:505:22]
reg uops_8_frs3_en; // @[util.scala:505:22]
reg uops_8_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_8_fcn_op; // @[util.scala:505:22]
reg uops_8_fp_val; // @[util.scala:505:22]
reg [2:0] uops_8_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_8_fp_typ; // @[util.scala:505:22]
reg uops_8_xcpt_pf_if; // @[util.scala:505:22]
reg uops_8_xcpt_ae_if; // @[util.scala:505:22]
reg uops_8_xcpt_ma_if; // @[util.scala:505:22]
reg uops_8_bp_debug_if; // @[util.scala:505:22]
reg uops_8_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_8_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_8_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_9_inst; // @[util.scala:505:22]
reg [31:0] uops_9_debug_inst; // @[util.scala:505:22]
reg uops_9_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_9_debug_pc; // @[util.scala:505:22]
reg uops_9_iq_type_0; // @[util.scala:505:22]
reg uops_9_iq_type_1; // @[util.scala:505:22]
reg uops_9_iq_type_2; // @[util.scala:505:22]
reg uops_9_iq_type_3; // @[util.scala:505:22]
reg uops_9_fu_code_0; // @[util.scala:505:22]
reg uops_9_fu_code_1; // @[util.scala:505:22]
reg uops_9_fu_code_2; // @[util.scala:505:22]
reg uops_9_fu_code_3; // @[util.scala:505:22]
reg uops_9_fu_code_4; // @[util.scala:505:22]
reg uops_9_fu_code_5; // @[util.scala:505:22]
reg uops_9_fu_code_6; // @[util.scala:505:22]
reg uops_9_fu_code_7; // @[util.scala:505:22]
reg uops_9_fu_code_8; // @[util.scala:505:22]
reg uops_9_fu_code_9; // @[util.scala:505:22]
reg uops_9_iw_issued; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_9_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_9_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_9_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_9_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_9_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_9_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_9_br_mask; // @[util.scala:505:22]
reg [3:0] uops_9_br_tag; // @[util.scala:505:22]
reg [3:0] uops_9_br_type; // @[util.scala:505:22]
reg uops_9_is_sfb; // @[util.scala:505:22]
reg uops_9_is_fence; // @[util.scala:505:22]
reg uops_9_is_fencei; // @[util.scala:505:22]
reg uops_9_is_sfence; // @[util.scala:505:22]
reg uops_9_is_amo; // @[util.scala:505:22]
reg uops_9_is_eret; // @[util.scala:505:22]
reg uops_9_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_9_is_rocc; // @[util.scala:505:22]
reg uops_9_is_mov; // @[util.scala:505:22]
reg [4:0] uops_9_ftq_idx; // @[util.scala:505:22]
reg uops_9_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_9_pc_lob; // @[util.scala:505:22]
reg uops_9_taken; // @[util.scala:505:22]
reg uops_9_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_9_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_9_pimm; // @[util.scala:505:22]
reg [19:0] uops_9_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_9_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_9_op2_sel; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_9_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_9_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_9_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_9_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_9_fp_ctrl_div; // @[util.scala:505:22]
reg uops_9_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_9_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_9_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_9_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_9_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_9_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_9_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_9_pdst; // @[util.scala:505:22]
reg [6:0] uops_9_prs1; // @[util.scala:505:22]
reg [6:0] uops_9_prs2; // @[util.scala:505:22]
reg [6:0] uops_9_prs3; // @[util.scala:505:22]
reg [4:0] uops_9_ppred; // @[util.scala:505:22]
reg uops_9_prs1_busy; // @[util.scala:505:22]
reg uops_9_prs2_busy; // @[util.scala:505:22]
reg uops_9_prs3_busy; // @[util.scala:505:22]
reg uops_9_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_9_stale_pdst; // @[util.scala:505:22]
reg uops_9_exception; // @[util.scala:505:22]
reg [63:0] uops_9_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_9_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_9_mem_size; // @[util.scala:505:22]
reg uops_9_mem_signed; // @[util.scala:505:22]
reg uops_9_uses_ldq; // @[util.scala:505:22]
reg uops_9_uses_stq; // @[util.scala:505:22]
reg uops_9_is_unique; // @[util.scala:505:22]
reg uops_9_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_9_csr_cmd; // @[util.scala:505:22]
reg uops_9_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_9_ldst; // @[util.scala:505:22]
reg [5:0] uops_9_lrs1; // @[util.scala:505:22]
reg [5:0] uops_9_lrs2; // @[util.scala:505:22]
reg [5:0] uops_9_lrs3; // @[util.scala:505:22]
reg [1:0] uops_9_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:505:22]
reg uops_9_frs3_en; // @[util.scala:505:22]
reg uops_9_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_9_fcn_op; // @[util.scala:505:22]
reg uops_9_fp_val; // @[util.scala:505:22]
reg [2:0] uops_9_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_9_fp_typ; // @[util.scala:505:22]
reg uops_9_xcpt_pf_if; // @[util.scala:505:22]
reg uops_9_xcpt_ae_if; // @[util.scala:505:22]
reg uops_9_xcpt_ma_if; // @[util.scala:505:22]
reg uops_9_bp_debug_if; // @[util.scala:505:22]
reg uops_9_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_9_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_9_debug_tsrc; // @[util.scala:505:22]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire full = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire [11:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7]
wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}]
wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59]
wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42]
wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35]
wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}]
wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [15:0] _GEN = {{valids_0}, {valids_0}, {valids_0}, {valids_0}, {valids_0}, {valids_0}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_0 = _GEN[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_0; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire [11:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}]
wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59]
wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34]
wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}]
wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}]
wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59]
wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34]
wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}]
wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}]
wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59]
wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34]
wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}]
wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}]
wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59]
wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34]
wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}]
wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:126:{51,59}]
wire _valids_4_T_2 = _valids_4_T_1; // @[util.scala:61:61, :126:59]
wire _valids_4_T_3 = ~_valids_4_T_2; // @[util.scala:61:61, :520:34]
wire _valids_4_T_4 = valids_4 & _valids_4_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_4_T_6 = ~_valids_4_T_5; // @[util.scala:520:{83,94}]
wire _valids_4_T_7 = _valids_4_T_4 & _valids_4_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:126:{51,59}]
wire _valids_5_T_2 = _valids_5_T_1; // @[util.scala:61:61, :126:59]
wire _valids_5_T_3 = ~_valids_5_T_2; // @[util.scala:61:61, :520:34]
wire _valids_5_T_4 = valids_5 & _valids_5_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_5_T_6 = ~_valids_5_T_5; // @[util.scala:520:{83,94}]
wire _valids_5_T_7 = _valids_5_T_4 & _valids_5_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:126:{51,59}]
wire _valids_6_T_2 = _valids_6_T_1; // @[util.scala:61:61, :126:59]
wire _valids_6_T_3 = ~_valids_6_T_2; // @[util.scala:61:61, :520:34]
wire _valids_6_T_4 = valids_6 & _valids_6_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_6_T_6 = ~_valids_6_T_5; // @[util.scala:520:{83,94}]
wire _valids_6_T_7 = _valids_6_T_4 & _valids_6_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:126:{51,59}]
wire _valids_7_T_2 = _valids_7_T_1; // @[util.scala:61:61, :126:59]
wire _valids_7_T_3 = ~_valids_7_T_2; // @[util.scala:61:61, :520:34]
wire _valids_7_T_4 = valids_7 & _valids_7_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_7_T_6 = ~_valids_7_T_5; // @[util.scala:520:{83,94}]
wire _valids_7_T_7 = _valids_7_T_4 & _valids_7_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:126:{51,59}]
wire _valids_8_T_2 = _valids_8_T_1; // @[util.scala:61:61, :126:59]
wire _valids_8_T_3 = ~_valids_8_T_2; // @[util.scala:61:61, :520:34]
wire _valids_8_T_4 = valids_8 & _valids_8_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_8_T_6 = ~_valids_8_T_5; // @[util.scala:520:{83,94}]
wire _valids_8_T_7 = _valids_8_T_4 & _valids_8_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:126:{51,59}]
wire _valids_9_T_2 = _valids_9_T_1; // @[util.scala:61:61, :126:59]
wire _valids_9_T_3 = ~_valids_9_T_2; // @[util.scala:61:61, :520:34]
wire _valids_9_T_4 = valids_9 & _valids_9_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_9_T_6 = ~_valids_9_T_5; // @[util.scala:520:{83,94}]
wire _valids_9_T_7 = _valids_9_T_4 & _valids_9_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire wrap = enq_ptr_value == 4'h9; // @[Counter.scala:61:40, :73:24]
wire [11:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7]
wire [11:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7]
wire [4:0] _GEN_1 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_1 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = deq_ptr_value == 4'h9; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
assign io_deq_bits_predicated_0 = out_predicated; // @[util.scala:458:7, :545:19]
assign io_deq_bits_fflags_valid_0 = out_fflags_valid; // @[util.scala:458:7, :545:19]
assign io_deq_bits_fflags_bits_0 = out_fflags_bits; // @[util.scala:458:7, :545:19]
wire [15:0][31:0] _GEN_3 = {{uops_0_inst}, {uops_0_inst}, {uops_0_inst}, {uops_0_inst}, {uops_0_inst}, {uops_0_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_3[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_4 = {{uops_0_debug_inst}, {uops_0_debug_inst}, {uops_0_debug_inst}, {uops_0_debug_inst}, {uops_0_debug_inst}, {uops_0_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_5 = {{uops_0_is_rvc}, {uops_0_is_rvc}, {uops_0_is_rvc}, {uops_0_is_rvc}, {uops_0_is_rvc}, {uops_0_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][39:0] _GEN_6 = {{uops_0_debug_pc}, {uops_0_debug_pc}, {uops_0_debug_pc}, {uops_0_debug_pc}, {uops_0_debug_pc}, {uops_0_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_0_iq_type_0}, {uops_0_iq_type_0}, {uops_0_iq_type_0}, {uops_0_iq_type_0}, {uops_0_iq_type_0}, {uops_0_iq_type_0}, {uops_9_iq_type_0}, {uops_8_iq_type_0}, {uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_8 = {{uops_0_iq_type_1}, {uops_0_iq_type_1}, {uops_0_iq_type_1}, {uops_0_iq_type_1}, {uops_0_iq_type_1}, {uops_0_iq_type_1}, {uops_9_iq_type_1}, {uops_8_iq_type_1}, {uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_9 = {{uops_0_iq_type_2}, {uops_0_iq_type_2}, {uops_0_iq_type_2}, {uops_0_iq_type_2}, {uops_0_iq_type_2}, {uops_0_iq_type_2}, {uops_9_iq_type_2}, {uops_8_iq_type_2}, {uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_10 = {{uops_0_iq_type_3}, {uops_0_iq_type_3}, {uops_0_iq_type_3}, {uops_0_iq_type_3}, {uops_0_iq_type_3}, {uops_0_iq_type_3}, {uops_9_iq_type_3}, {uops_8_iq_type_3}, {uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_11 = {{uops_0_fu_code_0}, {uops_0_fu_code_0}, {uops_0_fu_code_0}, {uops_0_fu_code_0}, {uops_0_fu_code_0}, {uops_0_fu_code_0}, {uops_9_fu_code_0}, {uops_8_fu_code_0}, {uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_12 = {{uops_0_fu_code_1}, {uops_0_fu_code_1}, {uops_0_fu_code_1}, {uops_0_fu_code_1}, {uops_0_fu_code_1}, {uops_0_fu_code_1}, {uops_9_fu_code_1}, {uops_8_fu_code_1}, {uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_13 = {{uops_0_fu_code_2}, {uops_0_fu_code_2}, {uops_0_fu_code_2}, {uops_0_fu_code_2}, {uops_0_fu_code_2}, {uops_0_fu_code_2}, {uops_9_fu_code_2}, {uops_8_fu_code_2}, {uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_14 = {{uops_0_fu_code_3}, {uops_0_fu_code_3}, {uops_0_fu_code_3}, {uops_0_fu_code_3}, {uops_0_fu_code_3}, {uops_0_fu_code_3}, {uops_9_fu_code_3}, {uops_8_fu_code_3}, {uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_15 = {{uops_0_fu_code_4}, {uops_0_fu_code_4}, {uops_0_fu_code_4}, {uops_0_fu_code_4}, {uops_0_fu_code_4}, {uops_0_fu_code_4}, {uops_9_fu_code_4}, {uops_8_fu_code_4}, {uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_0_fu_code_5}, {uops_0_fu_code_5}, {uops_0_fu_code_5}, {uops_0_fu_code_5}, {uops_0_fu_code_5}, {uops_0_fu_code_5}, {uops_9_fu_code_5}, {uops_8_fu_code_5}, {uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_17 = {{uops_0_fu_code_6}, {uops_0_fu_code_6}, {uops_0_fu_code_6}, {uops_0_fu_code_6}, {uops_0_fu_code_6}, {uops_0_fu_code_6}, {uops_9_fu_code_6}, {uops_8_fu_code_6}, {uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_0_fu_code_7}, {uops_0_fu_code_7}, {uops_0_fu_code_7}, {uops_0_fu_code_7}, {uops_0_fu_code_7}, {uops_0_fu_code_7}, {uops_9_fu_code_7}, {uops_8_fu_code_7}, {uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_0_fu_code_8}, {uops_0_fu_code_8}, {uops_0_fu_code_8}, {uops_0_fu_code_8}, {uops_0_fu_code_8}, {uops_0_fu_code_8}, {uops_9_fu_code_8}, {uops_8_fu_code_8}, {uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_0_fu_code_9}, {uops_0_fu_code_9}, {uops_0_fu_code_9}, {uops_0_fu_code_9}, {uops_0_fu_code_9}, {uops_0_fu_code_9}, {uops_9_fu_code_9}, {uops_8_fu_code_9}, {uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_21 = {{uops_0_iw_issued}, {uops_0_iw_issued}, {uops_0_iw_issued}, {uops_0_iw_issued}, {uops_0_iw_issued}, {uops_0_iw_issued}, {uops_9_iw_issued}, {uops_8_iw_issued}, {uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_0_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}, {uops_9_iw_issued_partial_agen}, {uops_8_iw_issued_partial_agen}, {uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_0_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}, {uops_9_iw_issued_partial_dgen}, {uops_8_iw_issued_partial_dgen}, {uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_24 = {{uops_0_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}, {uops_9_iw_p1_speculative_child}, {uops_8_iw_p1_speculative_child}, {uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_25 = {{uops_0_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}, {uops_9_iw_p2_speculative_child}, {uops_8_iw_p2_speculative_child}, {uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_0_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}, {uops_9_iw_p1_bypass_hint}, {uops_8_iw_p1_bypass_hint}, {uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_0_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}, {uops_9_iw_p2_bypass_hint}, {uops_8_iw_p2_bypass_hint}, {uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_28 = {{uops_0_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}, {uops_9_iw_p3_bypass_hint}, {uops_8_iw_p3_bypass_hint}, {uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_29 = {{uops_0_dis_col_sel}, {uops_0_dis_col_sel}, {uops_0_dis_col_sel}, {uops_0_dis_col_sel}, {uops_0_dis_col_sel}, {uops_0_dis_col_sel}, {uops_9_dis_col_sel}, {uops_8_dis_col_sel}, {uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][11:0] _GEN_30 = {{uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_31 = {{uops_0_br_tag}, {uops_0_br_tag}, {uops_0_br_tag}, {uops_0_br_tag}, {uops_0_br_tag}, {uops_0_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_32 = {{uops_0_br_type}, {uops_0_br_type}, {uops_0_br_type}, {uops_0_br_type}, {uops_0_br_type}, {uops_0_br_type}, {uops_9_br_type}, {uops_8_br_type}, {uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_0_is_sfb}, {uops_0_is_sfb}, {uops_0_is_sfb}, {uops_0_is_sfb}, {uops_0_is_sfb}, {uops_0_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_34 = {{uops_0_is_fence}, {uops_0_is_fence}, {uops_0_is_fence}, {uops_0_is_fence}, {uops_0_is_fence}, {uops_0_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_35 = {{uops_0_is_fencei}, {uops_0_is_fencei}, {uops_0_is_fencei}, {uops_0_is_fencei}, {uops_0_is_fencei}, {uops_0_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_36 = {{uops_0_is_sfence}, {uops_0_is_sfence}, {uops_0_is_sfence}, {uops_0_is_sfence}, {uops_0_is_sfence}, {uops_0_is_sfence}, {uops_9_is_sfence}, {uops_8_is_sfence}, {uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_37 = {{uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_38 = {{uops_0_is_eret}, {uops_0_is_eret}, {uops_0_is_eret}, {uops_0_is_eret}, {uops_0_is_eret}, {uops_0_is_eret}, {uops_9_is_eret}, {uops_8_is_eret}, {uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_39 = {{uops_0_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_40 = {{uops_0_is_rocc}, {uops_0_is_rocc}, {uops_0_is_rocc}, {uops_0_is_rocc}, {uops_0_is_rocc}, {uops_0_is_rocc}, {uops_9_is_rocc}, {uops_8_is_rocc}, {uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_41 = {{uops_0_is_mov}, {uops_0_is_mov}, {uops_0_is_mov}, {uops_0_is_mov}, {uops_0_is_mov}, {uops_0_is_mov}, {uops_9_is_mov}, {uops_8_is_mov}, {uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_42 = {{uops_0_ftq_idx}, {uops_0_ftq_idx}, {uops_0_ftq_idx}, {uops_0_ftq_idx}, {uops_0_ftq_idx}, {uops_0_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_43 = {{uops_0_edge_inst}, {uops_0_edge_inst}, {uops_0_edge_inst}, {uops_0_edge_inst}, {uops_0_edge_inst}, {uops_0_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_44 = {{uops_0_pc_lob}, {uops_0_pc_lob}, {uops_0_pc_lob}, {uops_0_pc_lob}, {uops_0_pc_lob}, {uops_0_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_0_taken}, {uops_0_taken}, {uops_0_taken}, {uops_0_taken}, {uops_0_taken}, {uops_0_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_0_imm_rename}, {uops_0_imm_rename}, {uops_0_imm_rename}, {uops_0_imm_rename}, {uops_0_imm_rename}, {uops_0_imm_rename}, {uops_9_imm_rename}, {uops_8_imm_rename}, {uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_47 = {{uops_0_imm_sel}, {uops_0_imm_sel}, {uops_0_imm_sel}, {uops_0_imm_sel}, {uops_0_imm_sel}, {uops_0_imm_sel}, {uops_9_imm_sel}, {uops_8_imm_sel}, {uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_48 = {{uops_0_pimm}, {uops_0_pimm}, {uops_0_pimm}, {uops_0_pimm}, {uops_0_pimm}, {uops_0_pimm}, {uops_9_pimm}, {uops_8_pimm}, {uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_49 = {{uops_0_imm_packed}, {uops_0_imm_packed}, {uops_0_imm_packed}, {uops_0_imm_packed}, {uops_0_imm_packed}, {uops_0_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_50 = {{uops_0_op1_sel}, {uops_0_op1_sel}, {uops_0_op1_sel}, {uops_0_op1_sel}, {uops_0_op1_sel}, {uops_0_op1_sel}, {uops_9_op1_sel}, {uops_8_op1_sel}, {uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_51 = {{uops_0_op2_sel}, {uops_0_op2_sel}, {uops_0_op2_sel}, {uops_0_op2_sel}, {uops_0_op2_sel}, {uops_0_op2_sel}, {uops_9_op2_sel}, {uops_8_op2_sel}, {uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_0_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}, {uops_9_fp_ctrl_ldst}, {uops_8_fp_ctrl_ldst}, {uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_53 = {{uops_0_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}, {uops_9_fp_ctrl_wen}, {uops_8_fp_ctrl_wen}, {uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_54 = {{uops_0_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}, {uops_9_fp_ctrl_ren1}, {uops_8_fp_ctrl_ren1}, {uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_0_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}, {uops_9_fp_ctrl_ren2}, {uops_8_fp_ctrl_ren2}, {uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_0_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}, {uops_9_fp_ctrl_ren3}, {uops_8_fp_ctrl_ren3}, {uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_0_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}, {uops_9_fp_ctrl_swap12}, {uops_8_fp_ctrl_swap12}, {uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_0_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}, {uops_9_fp_ctrl_swap23}, {uops_8_fp_ctrl_swap23}, {uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_59 = {{uops_0_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}, {uops_9_fp_ctrl_typeTagIn}, {uops_8_fp_ctrl_typeTagIn}, {uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_60 = {{uops_0_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}, {uops_9_fp_ctrl_typeTagOut}, {uops_8_fp_ctrl_typeTagOut}, {uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_0_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}, {uops_9_fp_ctrl_fromint}, {uops_8_fp_ctrl_fromint}, {uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_0_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}, {uops_9_fp_ctrl_toint}, {uops_8_fp_ctrl_toint}, {uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_0_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}, {uops_9_fp_ctrl_fastpipe}, {uops_8_fp_ctrl_fastpipe}, {uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_0_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}, {uops_9_fp_ctrl_fma}, {uops_8_fp_ctrl_fma}, {uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_65 = {{uops_0_fp_ctrl_div}, {uops_0_fp_ctrl_div}, {uops_0_fp_ctrl_div}, {uops_0_fp_ctrl_div}, {uops_0_fp_ctrl_div}, {uops_0_fp_ctrl_div}, {uops_9_fp_ctrl_div}, {uops_8_fp_ctrl_div}, {uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_66 = {{uops_0_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}, {uops_9_fp_ctrl_sqrt}, {uops_8_fp_ctrl_sqrt}, {uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_67 = {{uops_0_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}, {uops_9_fp_ctrl_wflags}, {uops_8_fp_ctrl_wflags}, {uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_68 = {{uops_0_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}, {uops_9_fp_ctrl_vec}, {uops_8_fp_ctrl_vec}, {uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_69 = {{uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_70 = {{uops_0_ldq_idx}, {uops_0_ldq_idx}, {uops_0_ldq_idx}, {uops_0_ldq_idx}, {uops_0_ldq_idx}, {uops_0_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_71 = {{uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_0_rxq_idx}, {uops_0_rxq_idx}, {uops_0_rxq_idx}, {uops_0_rxq_idx}, {uops_0_rxq_idx}, {uops_0_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_73 = {{uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_74 = {{uops_0_prs1}, {uops_0_prs1}, {uops_0_prs1}, {uops_0_prs1}, {uops_0_prs1}, {uops_0_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_75 = {{uops_0_prs2}, {uops_0_prs2}, {uops_0_prs2}, {uops_0_prs2}, {uops_0_prs2}, {uops_0_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_76 = {{uops_0_prs3}, {uops_0_prs3}, {uops_0_prs3}, {uops_0_prs3}, {uops_0_prs3}, {uops_0_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_77 = {{uops_0_ppred}, {uops_0_ppred}, {uops_0_ppred}, {uops_0_ppred}, {uops_0_ppred}, {uops_0_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_0_prs1_busy}, {uops_0_prs1_busy}, {uops_0_prs1_busy}, {uops_0_prs1_busy}, {uops_0_prs1_busy}, {uops_0_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_0_prs2_busy}, {uops_0_prs2_busy}, {uops_0_prs2_busy}, {uops_0_prs2_busy}, {uops_0_prs2_busy}, {uops_0_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_0_prs3_busy}, {uops_0_prs3_busy}, {uops_0_prs3_busy}, {uops_0_prs3_busy}, {uops_0_prs3_busy}, {uops_0_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_81 = {{uops_0_ppred_busy}, {uops_0_ppred_busy}, {uops_0_ppred_busy}, {uops_0_ppred_busy}, {uops_0_ppred_busy}, {uops_0_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_82 = {{uops_0_stale_pdst}, {uops_0_stale_pdst}, {uops_0_stale_pdst}, {uops_0_stale_pdst}, {uops_0_stale_pdst}, {uops_0_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_83 = {{uops_0_exception}, {uops_0_exception}, {uops_0_exception}, {uops_0_exception}, {uops_0_exception}, {uops_0_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_84 = {{uops_0_exc_cause}, {uops_0_exc_cause}, {uops_0_exc_cause}, {uops_0_exc_cause}, {uops_0_exc_cause}, {uops_0_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_85 = {{uops_0_mem_cmd}, {uops_0_mem_cmd}, {uops_0_mem_cmd}, {uops_0_mem_cmd}, {uops_0_mem_cmd}, {uops_0_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_86 = {{uops_0_mem_size}, {uops_0_mem_size}, {uops_0_mem_size}, {uops_0_mem_size}, {uops_0_mem_size}, {uops_0_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_87 = {{uops_0_mem_signed}, {uops_0_mem_signed}, {uops_0_mem_signed}, {uops_0_mem_signed}, {uops_0_mem_signed}, {uops_0_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_88 = {{uops_0_uses_ldq}, {uops_0_uses_ldq}, {uops_0_uses_ldq}, {uops_0_uses_ldq}, {uops_0_uses_ldq}, {uops_0_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_89 = {{uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_90 = {{uops_0_is_unique}, {uops_0_is_unique}, {uops_0_is_unique}, {uops_0_is_unique}, {uops_0_is_unique}, {uops_0_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_91 = {{uops_0_flush_on_commit}, {uops_0_flush_on_commit}, {uops_0_flush_on_commit}, {uops_0_flush_on_commit}, {uops_0_flush_on_commit}, {uops_0_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_92 = {{uops_0_csr_cmd}, {uops_0_csr_cmd}, {uops_0_csr_cmd}, {uops_0_csr_cmd}, {uops_0_csr_cmd}, {uops_0_csr_cmd}, {uops_9_csr_cmd}, {uops_8_csr_cmd}, {uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_93 = {{uops_0_ldst_is_rs1}, {uops_0_ldst_is_rs1}, {uops_0_ldst_is_rs1}, {uops_0_ldst_is_rs1}, {uops_0_ldst_is_rs1}, {uops_0_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_94 = {{uops_0_ldst}, {uops_0_ldst}, {uops_0_ldst}, {uops_0_ldst}, {uops_0_ldst}, {uops_0_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_95 = {{uops_0_lrs1}, {uops_0_lrs1}, {uops_0_lrs1}, {uops_0_lrs1}, {uops_0_lrs1}, {uops_0_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_96 = {{uops_0_lrs2}, {uops_0_lrs2}, {uops_0_lrs2}, {uops_0_lrs2}, {uops_0_lrs2}, {uops_0_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_97 = {{uops_0_lrs3}, {uops_0_lrs3}, {uops_0_lrs3}, {uops_0_lrs3}, {uops_0_lrs3}, {uops_0_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_98 = {{uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_99 = {{uops_0_lrs1_rtype}, {uops_0_lrs1_rtype}, {uops_0_lrs1_rtype}, {uops_0_lrs1_rtype}, {uops_0_lrs1_rtype}, {uops_0_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_100 = {{uops_0_lrs2_rtype}, {uops_0_lrs2_rtype}, {uops_0_lrs2_rtype}, {uops_0_lrs2_rtype}, {uops_0_lrs2_rtype}, {uops_0_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_101 = {{uops_0_frs3_en}, {uops_0_frs3_en}, {uops_0_frs3_en}, {uops_0_frs3_en}, {uops_0_frs3_en}, {uops_0_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_102 = {{uops_0_fcn_dw}, {uops_0_fcn_dw}, {uops_0_fcn_dw}, {uops_0_fcn_dw}, {uops_0_fcn_dw}, {uops_0_fcn_dw}, {uops_9_fcn_dw}, {uops_8_fcn_dw}, {uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_103 = {{uops_0_fcn_op}, {uops_0_fcn_op}, {uops_0_fcn_op}, {uops_0_fcn_op}, {uops_0_fcn_op}, {uops_0_fcn_op}, {uops_9_fcn_op}, {uops_8_fcn_op}, {uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_104 = {{uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_105 = {{uops_0_fp_rm}, {uops_0_fp_rm}, {uops_0_fp_rm}, {uops_0_fp_rm}, {uops_0_fp_rm}, {uops_0_fp_rm}, {uops_9_fp_rm}, {uops_8_fp_rm}, {uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_106 = {{uops_0_fp_typ}, {uops_0_fp_typ}, {uops_0_fp_typ}, {uops_0_fp_typ}, {uops_0_fp_typ}, {uops_0_fp_typ}, {uops_9_fp_typ}, {uops_8_fp_typ}, {uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_107 = {{uops_0_xcpt_pf_if}, {uops_0_xcpt_pf_if}, {uops_0_xcpt_pf_if}, {uops_0_xcpt_pf_if}, {uops_0_xcpt_pf_if}, {uops_0_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_108 = {{uops_0_xcpt_ae_if}, {uops_0_xcpt_ae_if}, {uops_0_xcpt_ae_if}, {uops_0_xcpt_ae_if}, {uops_0_xcpt_ae_if}, {uops_0_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_109 = {{uops_0_xcpt_ma_if}, {uops_0_xcpt_ma_if}, {uops_0_xcpt_ma_if}, {uops_0_xcpt_ma_if}, {uops_0_xcpt_ma_if}, {uops_0_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_110 = {{uops_0_bp_debug_if}, {uops_0_bp_debug_if}, {uops_0_bp_debug_if}, {uops_0_bp_debug_if}, {uops_0_bp_debug_if}, {uops_0_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_111 = {{uops_0_bp_xcpt_if}, {uops_0_bp_xcpt_if}, {uops_0_bp_xcpt_if}, {uops_0_bp_xcpt_if}, {uops_0_bp_xcpt_if}, {uops_0_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_112 = {{uops_0_debug_fsrc}, {uops_0_debug_fsrc}, {uops_0_debug_fsrc}, {uops_0_debug_fsrc}, {uops_0_debug_fsrc}, {uops_0_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_113 = {{uops_0_debug_tsrc}, {uops_0_debug_tsrc}, {uops_0_debug_tsrc}, {uops_0_debug_tsrc}, {uops_0_debug_tsrc}, {uops_0_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_0; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [4:0] _ptr_diff_T = _GEN_1 - _GEN_2; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:551:34]
wire [3:0] _io_count_T = maybe_full ? 4'hA : 4'h0; // @[util.scala:509:29, :557:12]
wire _io_count_T_1 = deq_ptr_value > enq_ptr_value; // @[Counter.scala:61:40]
wire [4:0] _io_count_T_2 = {1'h0, ptr_diff} + 5'hA; // @[util.scala:551:34, :560:26]
wire [3:0] _io_count_T_3 = _io_count_T_2[3:0]; // @[util.scala:560:26]
wire [3:0] _io_count_T_4 = _io_count_T_1 ? _io_count_T_3 : ptr_diff; // @[util.scala:551:34, :559:{12,27}, :560:26]
assign _io_count_T_5 = ptr_match ? _io_count_T : _io_count_T_4; // @[util.scala:511:35, :556:22, :557:12, :559:12]
assign io_count_0 = _io_count_T_5; // @[util.scala:458:7, :556:22]
wire _GEN_114 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_115 = do_enq & _GEN_114; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_116 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_117 = do_enq & _GEN_116; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_118 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_119 = do_enq & _GEN_118; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_120 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_121 = do_enq & _GEN_120; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_122 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_123 = do_enq & _GEN_122; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_124 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_125 = do_enq & _GEN_124; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_126 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_127 = do_enq & _GEN_126; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_128 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_129 = do_enq & _GEN_128; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_130 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_131 = do_enq & _GEN_130; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_132 = do_enq & wrap; // @[Counter.scala:73:24]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
valids_4 <= 1'h0; // @[util.scala:504:26]
valids_5 <= 1'h0; // @[util.scala:504:26]
valids_6 <= 1'h0; // @[util.scala:504:26]
valids_7 <= 1'h0; // @[util.scala:504:26]
valids_8 <= 1'h0; // @[util.scala:504:26]
valids_9 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_115 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_117 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_119 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_123 | _valids_4_T_7); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_125 | _valids_5_T_7); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_127 | _valids_6_T_7); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_131 | _valids_8_T_7); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & wrap_1) & (_GEN_132 | _valids_9_T_7); // @[Counter.scala:73:24]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= wrap ? 4'h0 : _value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= wrap_1 ? 4'h0 : _value_T_3; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_115) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_114) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_117) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_116) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_119) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_118) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_120) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_123) begin // @[util.scala:520:18, :526:19, :528:35]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_122) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_4) // @[util.scala:504:26]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_125) begin // @[util.scala:520:18, :526:19, :528:35]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_124) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_5) // @[util.scala:504:26]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_127) begin // @[util.scala:520:18, :526:19, :528:35]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_126) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_6) // @[util.scala:504:26]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_128) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_7) // @[util.scala:504:26]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_131) begin // @[util.scala:520:18, :526:19, :528:35]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_8_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_8_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_8_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_8_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_8_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_8_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_8_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_8_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_8_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_8_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_8_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_8_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_8_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_8_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_8_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_8_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_8_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_8_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_130) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_8) // @[util.scala:504:26]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_132) begin // @[util.scala:520:18, :526:19, :528:35]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_9_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_9_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_9_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_9_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_9_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_9_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_9_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_9_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_9_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_9_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_9_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_9_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_9_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_9_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_9_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_9_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_9_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_9_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & wrap) // @[Counter.scala:73:24]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_9) // @[util.scala:504:26]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_10x72 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data ({io_enq_bits_fflags_bits_0, io_enq_bits_fflags_valid_0, 1'h0, io_enq_bits_data_0}) // @[util.scala:458:7, :503:22]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_predicated = io_deq_bits_predicated_0; // @[util.scala:458:7]
assign io_deq_bits_fflags_valid = io_deq_bits_fflags_valid_0; // @[util.scala:458:7]
assign io_deq_bits_fflags_bits = io_deq_bits_fflags_bits_0; // @[util.scala:458:7]
assign io_count = io_count_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_6( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_262 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_63( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_109( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_103( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLFIFOFixer_1( // @[FIFOFixer.scala:50:9]
input clock, // @[FIFOFixer.scala:50:9]
input reset, // @[FIFOFixer.scala:50:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire [29:0] _a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _stalls_a_sel_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_6 = 1'h1; // @[FIFOFixer.scala:85:59]
wire [128:0] _allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [28:0] auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29]
wire [7:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source; // @[Parameters.scala:52:29]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [28:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
wire _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [29:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_id_T_2 = _a_id_T_1 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_id_T_3 = _a_id_T_2; // @[Parameters.scala:137:46]
wire _a_id_T_4 = _a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_id_T_10 = _a_id_T_4; // @[Mux.scala:30:73]
wire [28:0] _a_id_T_5 = anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [29:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_id_T_7 = _a_id_T_6 & 30'h10000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_id_T_8 = _a_id_T_7; // @[Parameters.scala:137:46]
wire _a_id_T_9 = _a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] _a_id_T_11 = {_a_id_T_9, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _a_id_T_12 = {1'h0, _a_id_T_10} | _a_id_T_11; // @[Mux.scala:30:73]
wire [1:0] a_id = _a_id_T_12; // @[Mux.scala:30:73]
wire a_noDomain = a_id == 2'h0; // @[Mux.scala:30:73]
wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T; // @[Decoupled.scala:51:35]
assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T_4; // @[Decoupled.scala:51:35]
assign _stalls_id_T_4 = _T_5; // @[Decoupled.scala:51:35]
wire [12:0] _a_first_beats1_decode_T = 13'h3F << anonIn_a_bits_size; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [12:0] _d_first_beats1_decode_T = 13'h3F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg flight_0; // @[FIFOFixer.scala:79:27]
reg flight_1; // @[FIFOFixer.scala:79:27]
reg flight_2; // @[FIFOFixer.scala:79:27]
reg flight_3; // @[FIFOFixer.scala:79:27]
reg flight_4; // @[FIFOFixer.scala:79:27]
reg flight_5; // @[FIFOFixer.scala:79:27]
reg flight_6; // @[FIFOFixer.scala:79:27]
reg flight_7; // @[FIFOFixer.scala:79:27]
reg flight_8; // @[FIFOFixer.scala:79:27]
reg flight_9; // @[FIFOFixer.scala:79:27]
reg flight_10; // @[FIFOFixer.scala:79:27]
reg flight_11; // @[FIFOFixer.scala:79:27]
reg flight_12; // @[FIFOFixer.scala:79:27]
reg flight_13; // @[FIFOFixer.scala:79:27]
reg flight_14; // @[FIFOFixer.scala:79:27]
reg flight_15; // @[FIFOFixer.scala:79:27]
reg flight_16; // @[FIFOFixer.scala:79:27]
reg flight_17; // @[FIFOFixer.scala:79:27]
reg flight_18; // @[FIFOFixer.scala:79:27]
reg flight_19; // @[FIFOFixer.scala:79:27]
reg flight_20; // @[FIFOFixer.scala:79:27]
reg flight_21; // @[FIFOFixer.scala:79:27]
reg flight_22; // @[FIFOFixer.scala:79:27]
reg flight_23; // @[FIFOFixer.scala:79:27]
reg flight_24; // @[FIFOFixer.scala:79:27]
reg flight_25; // @[FIFOFixer.scala:79:27]
reg flight_26; // @[FIFOFixer.scala:79:27]
reg flight_27; // @[FIFOFixer.scala:79:27]
reg flight_28; // @[FIFOFixer.scala:79:27]
reg flight_29; // @[FIFOFixer.scala:79:27]
reg flight_30; // @[FIFOFixer.scala:79:27]
reg flight_31; // @[FIFOFixer.scala:79:27]
reg flight_32; // @[FIFOFixer.scala:79:27]
reg flight_33; // @[FIFOFixer.scala:79:27]
reg flight_34; // @[FIFOFixer.scala:79:27]
reg flight_35; // @[FIFOFixer.scala:79:27]
reg flight_36; // @[FIFOFixer.scala:79:27]
reg flight_37; // @[FIFOFixer.scala:79:27]
reg flight_38; // @[FIFOFixer.scala:79:27]
reg flight_39; // @[FIFOFixer.scala:79:27]
reg flight_40; // @[FIFOFixer.scala:79:27]
reg flight_41; // @[FIFOFixer.scala:79:27]
reg flight_42; // @[FIFOFixer.scala:79:27]
reg flight_43; // @[FIFOFixer.scala:79:27]
reg flight_44; // @[FIFOFixer.scala:79:27]
reg flight_45; // @[FIFOFixer.scala:79:27]
reg flight_46; // @[FIFOFixer.scala:79:27]
reg flight_47; // @[FIFOFixer.scala:79:27]
reg flight_48; // @[FIFOFixer.scala:79:27]
reg flight_49; // @[FIFOFixer.scala:79:27]
reg flight_50; // @[FIFOFixer.scala:79:27]
reg flight_51; // @[FIFOFixer.scala:79:27]
reg flight_52; // @[FIFOFixer.scala:79:27]
reg flight_53; // @[FIFOFixer.scala:79:27]
reg flight_54; // @[FIFOFixer.scala:79:27]
reg flight_55; // @[FIFOFixer.scala:79:27]
reg flight_56; // @[FIFOFixer.scala:79:27]
reg flight_57; // @[FIFOFixer.scala:79:27]
reg flight_58; // @[FIFOFixer.scala:79:27]
reg flight_59; // @[FIFOFixer.scala:79:27]
reg flight_60; // @[FIFOFixer.scala:79:27]
reg flight_61; // @[FIFOFixer.scala:79:27]
reg flight_62; // @[FIFOFixer.scala:79:27]
reg flight_63; // @[FIFOFixer.scala:79:27]
reg flight_64; // @[FIFOFixer.scala:79:27]
reg flight_65; // @[FIFOFixer.scala:79:27]
reg flight_66; // @[FIFOFixer.scala:79:27]
reg flight_67; // @[FIFOFixer.scala:79:27]
reg flight_68; // @[FIFOFixer.scala:79:27]
reg flight_69; // @[FIFOFixer.scala:79:27]
reg flight_70; // @[FIFOFixer.scala:79:27]
reg flight_71; // @[FIFOFixer.scala:79:27]
reg flight_72; // @[FIFOFixer.scala:79:27]
reg flight_73; // @[FIFOFixer.scala:79:27]
reg flight_74; // @[FIFOFixer.scala:79:27]
reg flight_75; // @[FIFOFixer.scala:79:27]
reg flight_76; // @[FIFOFixer.scala:79:27]
reg flight_77; // @[FIFOFixer.scala:79:27]
reg flight_78; // @[FIFOFixer.scala:79:27]
reg flight_79; // @[FIFOFixer.scala:79:27]
reg flight_80; // @[FIFOFixer.scala:79:27]
reg flight_81; // @[FIFOFixer.scala:79:27]
reg flight_82; // @[FIFOFixer.scala:79:27]
reg flight_83; // @[FIFOFixer.scala:79:27]
reg flight_84; // @[FIFOFixer.scala:79:27]
reg flight_85; // @[FIFOFixer.scala:79:27]
reg flight_86; // @[FIFOFixer.scala:79:27]
reg flight_87; // @[FIFOFixer.scala:79:27]
reg flight_88; // @[FIFOFixer.scala:79:27]
reg flight_89; // @[FIFOFixer.scala:79:27]
reg flight_90; // @[FIFOFixer.scala:79:27]
reg flight_91; // @[FIFOFixer.scala:79:27]
reg flight_92; // @[FIFOFixer.scala:79:27]
reg flight_93; // @[FIFOFixer.scala:79:27]
reg flight_94; // @[FIFOFixer.scala:79:27]
reg flight_95; // @[FIFOFixer.scala:79:27]
reg flight_96; // @[FIFOFixer.scala:79:27]
reg flight_97; // @[FIFOFixer.scala:79:27]
reg flight_98; // @[FIFOFixer.scala:79:27]
reg flight_99; // @[FIFOFixer.scala:79:27]
reg flight_100; // @[FIFOFixer.scala:79:27]
reg flight_101; // @[FIFOFixer.scala:79:27]
reg flight_102; // @[FIFOFixer.scala:79:27]
reg flight_103; // @[FIFOFixer.scala:79:27]
reg flight_104; // @[FIFOFixer.scala:79:27]
reg flight_105; // @[FIFOFixer.scala:79:27]
reg flight_106; // @[FIFOFixer.scala:79:27]
reg flight_107; // @[FIFOFixer.scala:79:27]
reg flight_108; // @[FIFOFixer.scala:79:27]
reg flight_109; // @[FIFOFixer.scala:79:27]
reg flight_110; // @[FIFOFixer.scala:79:27]
reg flight_111; // @[FIFOFixer.scala:79:27]
reg flight_112; // @[FIFOFixer.scala:79:27]
reg flight_113; // @[FIFOFixer.scala:79:27]
reg flight_114; // @[FIFOFixer.scala:79:27]
reg flight_115; // @[FIFOFixer.scala:79:27]
reg flight_116; // @[FIFOFixer.scala:79:27]
reg flight_117; // @[FIFOFixer.scala:79:27]
reg flight_118; // @[FIFOFixer.scala:79:27]
reg flight_119; // @[FIFOFixer.scala:79:27]
reg flight_120; // @[FIFOFixer.scala:79:27]
reg flight_121; // @[FIFOFixer.scala:79:27]
reg flight_122; // @[FIFOFixer.scala:79:27]
reg flight_123; // @[FIFOFixer.scala:79:27]
reg flight_124; // @[FIFOFixer.scala:79:27]
reg flight_125; // @[FIFOFixer.scala:79:27]
reg flight_126; // @[FIFOFixer.scala:79:27]
reg flight_127; // @[FIFOFixer.scala:79:27]
reg flight_128; // @[FIFOFixer.scala:79:27]
wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _stalls_a_sel_T = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10]
wire [4:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10]
wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35]
wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}]
reg [1:0] stalls_id; // @[FIFOFixer.scala:85:30]
wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_1 = flight_16 | flight_17; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_2 = _stalls_T_1 | flight_18; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_3 = _stalls_T_2 | flight_19; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_4 = _stalls_T_3 | flight_20; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_5 = _stalls_T_4 | flight_21; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_6 = _stalls_T_5 | flight_22; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_7 = _stalls_T_6 | flight_23; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_9 = stalls_id != a_id; // @[Mux.scala:30:73]
wire _stalls_T_10 = a_noDomain | _stalls_T_9; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_0 = _stalls_T_8 & _stalls_T_10; // @[FIFOFixer.scala:88:{26,50,65}]
wire _stall_T = stalls_0; // @[FIFOFixer.scala:88:50, :91:45]
wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel_1 = _stalls_a_sel_T_8; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1; // @[Decoupled.scala:51:35]
wire _stalls_id_T_7 = _stalls_id_T_5; // @[FIFOFixer.scala:85:{47,56}]
reg [1:0] stalls_id_1; // @[FIFOFixer.scala:85:30]
wire _stalls_T_11 = stalls_a_sel_1 & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_12 = flight_24 | flight_25; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_13 = _stalls_T_12 | flight_26; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_14 = _stalls_T_13 | flight_27; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_15 = _stalls_T_14 | flight_28; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_16 = _stalls_T_15 | flight_29; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_17 = _stalls_T_16 | flight_30; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_18 = _stalls_T_17 | flight_31; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_20 = stalls_id_1 != a_id; // @[Mux.scala:30:73]
wire _stalls_T_21 = a_noDomain | _stalls_T_20; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_1 = _stalls_T_19 & _stalls_T_21; // @[FIFOFixer.scala:88:{26,50,65}]
wire stall = _stall_T | stalls_1; // @[FIFOFixer.scala:88:50, :91:45]
wire _anonOut_a_valid_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50]
wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T; // @[FIFOFixer.scala:95:{47,50}]
assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1; // @[FIFOFixer.scala:95:{33,47}]
assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire _anonIn_a_ready_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50, :96:50]
wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T; // @[FIFOFixer.scala:96:{47,50}]
assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1; // @[FIFOFixer.scala:96:{33,47}]
assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [128:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [128:0] SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [128:0] SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [255:0] _SourceIdSet_T = 256'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [255:0] _SourceIdClear_T = 256'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [128:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35]
wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[FIFOFixer.scala:50:9]
if (reset) begin // @[FIFOFixer.scala:50:9]
a_first_counter <= 3'h0; // @[Edges.scala:229:27]
d_first_counter <= 3'h0; // @[Edges.scala:229:27]
flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27]
SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[FIFOFixer.scala:50:9]
if (_a_first_T) // @[Decoupled.scala:51:35]
a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (_d_first_T) // @[Decoupled.scala:51:35]
d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21]
flight_0 <= ~(_T_3 & anonIn_d_bits_source == 8'h0) & (_T_1 & anonIn_a_bits_source == 8'h0 | flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_1 <= ~(_T_3 & anonIn_d_bits_source == 8'h1) & (_T_1 & anonIn_a_bits_source == 8'h1 | flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_2 <= ~(_T_3 & anonIn_d_bits_source == 8'h2) & (_T_1 & anonIn_a_bits_source == 8'h2 | flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_3 <= ~(_T_3 & anonIn_d_bits_source == 8'h3) & (_T_1 & anonIn_a_bits_source == 8'h3 | flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_4 <= ~(_T_3 & anonIn_d_bits_source == 8'h4) & (_T_1 & anonIn_a_bits_source == 8'h4 | flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_5 <= ~(_T_3 & anonIn_d_bits_source == 8'h5) & (_T_1 & anonIn_a_bits_source == 8'h5 | flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_6 <= ~(_T_3 & anonIn_d_bits_source == 8'h6) & (_T_1 & anonIn_a_bits_source == 8'h6 | flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_7 <= ~(_T_3 & anonIn_d_bits_source == 8'h7) & (_T_1 & anonIn_a_bits_source == 8'h7 | flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_8 <= ~(_T_3 & anonIn_d_bits_source == 8'h8) & (_T_1 & anonIn_a_bits_source == 8'h8 | flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_9 <= ~(_T_3 & anonIn_d_bits_source == 8'h9) & (_T_1 & anonIn_a_bits_source == 8'h9 | flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_10 <= ~(_T_3 & anonIn_d_bits_source == 8'hA) & (_T_1 & anonIn_a_bits_source == 8'hA | flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_11 <= ~(_T_3 & anonIn_d_bits_source == 8'hB) & (_T_1 & anonIn_a_bits_source == 8'hB | flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_12 <= ~(_T_3 & anonIn_d_bits_source == 8'hC) & (_T_1 & anonIn_a_bits_source == 8'hC | flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_13 <= ~(_T_3 & anonIn_d_bits_source == 8'hD) & (_T_1 & anonIn_a_bits_source == 8'hD | flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_14 <= ~(_T_3 & anonIn_d_bits_source == 8'hE) & (_T_1 & anonIn_a_bits_source == 8'hE | flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_15 <= ~(_T_3 & anonIn_d_bits_source == 8'hF) & (_T_1 & anonIn_a_bits_source == 8'hF | flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_16 <= ~(_T_3 & anonIn_d_bits_source == 8'h10) & (_T_1 & anonIn_a_bits_source == 8'h10 | flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_17 <= ~(_T_3 & anonIn_d_bits_source == 8'h11) & (_T_1 & anonIn_a_bits_source == 8'h11 | flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_18 <= ~(_T_3 & anonIn_d_bits_source == 8'h12) & (_T_1 & anonIn_a_bits_source == 8'h12 | flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_19 <= ~(_T_3 & anonIn_d_bits_source == 8'h13) & (_T_1 & anonIn_a_bits_source == 8'h13 | flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_20 <= ~(_T_3 & anonIn_d_bits_source == 8'h14) & (_T_1 & anonIn_a_bits_source == 8'h14 | flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_21 <= ~(_T_3 & anonIn_d_bits_source == 8'h15) & (_T_1 & anonIn_a_bits_source == 8'h15 | flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_22 <= ~(_T_3 & anonIn_d_bits_source == 8'h16) & (_T_1 & anonIn_a_bits_source == 8'h16 | flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_23 <= ~(_T_3 & anonIn_d_bits_source == 8'h17) & (_T_1 & anonIn_a_bits_source == 8'h17 | flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_24 <= ~(_T_3 & anonIn_d_bits_source == 8'h18) & (_T_1 & anonIn_a_bits_source == 8'h18 | flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_25 <= ~(_T_3 & anonIn_d_bits_source == 8'h19) & (_T_1 & anonIn_a_bits_source == 8'h19 | flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_26 <= ~(_T_3 & anonIn_d_bits_source == 8'h1A) & (_T_1 & anonIn_a_bits_source == 8'h1A | flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_27 <= ~(_T_3 & anonIn_d_bits_source == 8'h1B) & (_T_1 & anonIn_a_bits_source == 8'h1B | flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_28 <= ~(_T_3 & anonIn_d_bits_source == 8'h1C) & (_T_1 & anonIn_a_bits_source == 8'h1C | flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_29 <= ~(_T_3 & anonIn_d_bits_source == 8'h1D) & (_T_1 & anonIn_a_bits_source == 8'h1D | flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_30 <= ~(_T_3 & anonIn_d_bits_source == 8'h1E) & (_T_1 & anonIn_a_bits_source == 8'h1E | flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_31 <= ~(_T_3 & anonIn_d_bits_source == 8'h1F) & (_T_1 & anonIn_a_bits_source == 8'h1F | flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_32 <= ~(_T_3 & anonIn_d_bits_source == 8'h20) & (_T_1 & anonIn_a_bits_source == 8'h20 | flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_33 <= ~(_T_3 & anonIn_d_bits_source == 8'h21) & (_T_1 & anonIn_a_bits_source == 8'h21 | flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_34 <= ~(_T_3 & anonIn_d_bits_source == 8'h22) & (_T_1 & anonIn_a_bits_source == 8'h22 | flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_35 <= ~(_T_3 & anonIn_d_bits_source == 8'h23) & (_T_1 & anonIn_a_bits_source == 8'h23 | flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_36 <= ~(_T_3 & anonIn_d_bits_source == 8'h24) & (_T_1 & anonIn_a_bits_source == 8'h24 | flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_37 <= ~(_T_3 & anonIn_d_bits_source == 8'h25) & (_T_1 & anonIn_a_bits_source == 8'h25 | flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_38 <= ~(_T_3 & anonIn_d_bits_source == 8'h26) & (_T_1 & anonIn_a_bits_source == 8'h26 | flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_39 <= ~(_T_3 & anonIn_d_bits_source == 8'h27) & (_T_1 & anonIn_a_bits_source == 8'h27 | flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_40 <= ~(_T_3 & anonIn_d_bits_source == 8'h28) & (_T_1 & anonIn_a_bits_source == 8'h28 | flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_41 <= ~(_T_3 & anonIn_d_bits_source == 8'h29) & (_T_1 & anonIn_a_bits_source == 8'h29 | flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_42 <= ~(_T_3 & anonIn_d_bits_source == 8'h2A) & (_T_1 & anonIn_a_bits_source == 8'h2A | flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_43 <= ~(_T_3 & anonIn_d_bits_source == 8'h2B) & (_T_1 & anonIn_a_bits_source == 8'h2B | flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_44 <= ~(_T_3 & anonIn_d_bits_source == 8'h2C) & (_T_1 & anonIn_a_bits_source == 8'h2C | flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_45 <= ~(_T_3 & anonIn_d_bits_source == 8'h2D) & (_T_1 & anonIn_a_bits_source == 8'h2D | flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_46 <= ~(_T_3 & anonIn_d_bits_source == 8'h2E) & (_T_1 & anonIn_a_bits_source == 8'h2E | flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_47 <= ~(_T_3 & anonIn_d_bits_source == 8'h2F) & (_T_1 & anonIn_a_bits_source == 8'h2F | flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_48 <= ~(_T_3 & anonIn_d_bits_source == 8'h30) & (_T_1 & anonIn_a_bits_source == 8'h30 | flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_49 <= ~(_T_3 & anonIn_d_bits_source == 8'h31) & (_T_1 & anonIn_a_bits_source == 8'h31 | flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_50 <= ~(_T_3 & anonIn_d_bits_source == 8'h32) & (_T_1 & anonIn_a_bits_source == 8'h32 | flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_51 <= ~(_T_3 & anonIn_d_bits_source == 8'h33) & (_T_1 & anonIn_a_bits_source == 8'h33 | flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_52 <= ~(_T_3 & anonIn_d_bits_source == 8'h34) & (_T_1 & anonIn_a_bits_source == 8'h34 | flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_53 <= ~(_T_3 & anonIn_d_bits_source == 8'h35) & (_T_1 & anonIn_a_bits_source == 8'h35 | flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_54 <= ~(_T_3 & anonIn_d_bits_source == 8'h36) & (_T_1 & anonIn_a_bits_source == 8'h36 | flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_55 <= ~(_T_3 & anonIn_d_bits_source == 8'h37) & (_T_1 & anonIn_a_bits_source == 8'h37 | flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_56 <= ~(_T_3 & anonIn_d_bits_source == 8'h38) & (_T_1 & anonIn_a_bits_source == 8'h38 | flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_57 <= ~(_T_3 & anonIn_d_bits_source == 8'h39) & (_T_1 & anonIn_a_bits_source == 8'h39 | flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_58 <= ~(_T_3 & anonIn_d_bits_source == 8'h3A) & (_T_1 & anonIn_a_bits_source == 8'h3A | flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_59 <= ~(_T_3 & anonIn_d_bits_source == 8'h3B) & (_T_1 & anonIn_a_bits_source == 8'h3B | flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_60 <= ~(_T_3 & anonIn_d_bits_source == 8'h3C) & (_T_1 & anonIn_a_bits_source == 8'h3C | flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_61 <= ~(_T_3 & anonIn_d_bits_source == 8'h3D) & (_T_1 & anonIn_a_bits_source == 8'h3D | flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_62 <= ~(_T_3 & anonIn_d_bits_source == 8'h3E) & (_T_1 & anonIn_a_bits_source == 8'h3E | flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_63 <= ~(_T_3 & anonIn_d_bits_source == 8'h3F) & (_T_1 & anonIn_a_bits_source == 8'h3F | flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_64 <= ~(_T_3 & anonIn_d_bits_source == 8'h40) & (_T_1 & anonIn_a_bits_source == 8'h40 | flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_65 <= ~(_T_3 & anonIn_d_bits_source == 8'h41) & (_T_1 & anonIn_a_bits_source == 8'h41 | flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_66 <= ~(_T_3 & anonIn_d_bits_source == 8'h42) & (_T_1 & anonIn_a_bits_source == 8'h42 | flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_67 <= ~(_T_3 & anonIn_d_bits_source == 8'h43) & (_T_1 & anonIn_a_bits_source == 8'h43 | flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_68 <= ~(_T_3 & anonIn_d_bits_source == 8'h44) & (_T_1 & anonIn_a_bits_source == 8'h44 | flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_69 <= ~(_T_3 & anonIn_d_bits_source == 8'h45) & (_T_1 & anonIn_a_bits_source == 8'h45 | flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_70 <= ~(_T_3 & anonIn_d_bits_source == 8'h46) & (_T_1 & anonIn_a_bits_source == 8'h46 | flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_71 <= ~(_T_3 & anonIn_d_bits_source == 8'h47) & (_T_1 & anonIn_a_bits_source == 8'h47 | flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_72 <= ~(_T_3 & anonIn_d_bits_source == 8'h48) & (_T_1 & anonIn_a_bits_source == 8'h48 | flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_73 <= ~(_T_3 & anonIn_d_bits_source == 8'h49) & (_T_1 & anonIn_a_bits_source == 8'h49 | flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_74 <= ~(_T_3 & anonIn_d_bits_source == 8'h4A) & (_T_1 & anonIn_a_bits_source == 8'h4A | flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_75 <= ~(_T_3 & anonIn_d_bits_source == 8'h4B) & (_T_1 & anonIn_a_bits_source == 8'h4B | flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_76 <= ~(_T_3 & anonIn_d_bits_source == 8'h4C) & (_T_1 & anonIn_a_bits_source == 8'h4C | flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_77 <= ~(_T_3 & anonIn_d_bits_source == 8'h4D) & (_T_1 & anonIn_a_bits_source == 8'h4D | flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_78 <= ~(_T_3 & anonIn_d_bits_source == 8'h4E) & (_T_1 & anonIn_a_bits_source == 8'h4E | flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_79 <= ~(_T_3 & anonIn_d_bits_source == 8'h4F) & (_T_1 & anonIn_a_bits_source == 8'h4F | flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_80 <= ~(_T_3 & anonIn_d_bits_source == 8'h50) & (_T_1 & anonIn_a_bits_source == 8'h50 | flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_81 <= ~(_T_3 & anonIn_d_bits_source == 8'h51) & (_T_1 & anonIn_a_bits_source == 8'h51 | flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_82 <= ~(_T_3 & anonIn_d_bits_source == 8'h52) & (_T_1 & anonIn_a_bits_source == 8'h52 | flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_83 <= ~(_T_3 & anonIn_d_bits_source == 8'h53) & (_T_1 & anonIn_a_bits_source == 8'h53 | flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_84 <= ~(_T_3 & anonIn_d_bits_source == 8'h54) & (_T_1 & anonIn_a_bits_source == 8'h54 | flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_85 <= ~(_T_3 & anonIn_d_bits_source == 8'h55) & (_T_1 & anonIn_a_bits_source == 8'h55 | flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_86 <= ~(_T_3 & anonIn_d_bits_source == 8'h56) & (_T_1 & anonIn_a_bits_source == 8'h56 | flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_87 <= ~(_T_3 & anonIn_d_bits_source == 8'h57) & (_T_1 & anonIn_a_bits_source == 8'h57 | flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_88 <= ~(_T_3 & anonIn_d_bits_source == 8'h58) & (_T_1 & anonIn_a_bits_source == 8'h58 | flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_89 <= ~(_T_3 & anonIn_d_bits_source == 8'h59) & (_T_1 & anonIn_a_bits_source == 8'h59 | flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_90 <= ~(_T_3 & anonIn_d_bits_source == 8'h5A) & (_T_1 & anonIn_a_bits_source == 8'h5A | flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_91 <= ~(_T_3 & anonIn_d_bits_source == 8'h5B) & (_T_1 & anonIn_a_bits_source == 8'h5B | flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_92 <= ~(_T_3 & anonIn_d_bits_source == 8'h5C) & (_T_1 & anonIn_a_bits_source == 8'h5C | flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_93 <= ~(_T_3 & anonIn_d_bits_source == 8'h5D) & (_T_1 & anonIn_a_bits_source == 8'h5D | flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_94 <= ~(_T_3 & anonIn_d_bits_source == 8'h5E) & (_T_1 & anonIn_a_bits_source == 8'h5E | flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_95 <= ~(_T_3 & anonIn_d_bits_source == 8'h5F) & (_T_1 & anonIn_a_bits_source == 8'h5F | flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_96 <= ~(_T_3 & anonIn_d_bits_source == 8'h60) & (_T_1 & anonIn_a_bits_source == 8'h60 | flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_97 <= ~(_T_3 & anonIn_d_bits_source == 8'h61) & (_T_1 & anonIn_a_bits_source == 8'h61 | flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_98 <= ~(_T_3 & anonIn_d_bits_source == 8'h62) & (_T_1 & anonIn_a_bits_source == 8'h62 | flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_99 <= ~(_T_3 & anonIn_d_bits_source == 8'h63) & (_T_1 & anonIn_a_bits_source == 8'h63 | flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_100 <= ~(_T_3 & anonIn_d_bits_source == 8'h64) & (_T_1 & anonIn_a_bits_source == 8'h64 | flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_101 <= ~(_T_3 & anonIn_d_bits_source == 8'h65) & (_T_1 & anonIn_a_bits_source == 8'h65 | flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_102 <= ~(_T_3 & anonIn_d_bits_source == 8'h66) & (_T_1 & anonIn_a_bits_source == 8'h66 | flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_103 <= ~(_T_3 & anonIn_d_bits_source == 8'h67) & (_T_1 & anonIn_a_bits_source == 8'h67 | flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_104 <= ~(_T_3 & anonIn_d_bits_source == 8'h68) & (_T_1 & anonIn_a_bits_source == 8'h68 | flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_105 <= ~(_T_3 & anonIn_d_bits_source == 8'h69) & (_T_1 & anonIn_a_bits_source == 8'h69 | flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_106 <= ~(_T_3 & anonIn_d_bits_source == 8'h6A) & (_T_1 & anonIn_a_bits_source == 8'h6A | flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_107 <= ~(_T_3 & anonIn_d_bits_source == 8'h6B) & (_T_1 & anonIn_a_bits_source == 8'h6B | flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_108 <= ~(_T_3 & anonIn_d_bits_source == 8'h6C) & (_T_1 & anonIn_a_bits_source == 8'h6C | flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_109 <= ~(_T_3 & anonIn_d_bits_source == 8'h6D) & (_T_1 & anonIn_a_bits_source == 8'h6D | flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_110 <= ~(_T_3 & anonIn_d_bits_source == 8'h6E) & (_T_1 & anonIn_a_bits_source == 8'h6E | flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_111 <= ~(_T_3 & anonIn_d_bits_source == 8'h6F) & (_T_1 & anonIn_a_bits_source == 8'h6F | flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_112 <= ~(_T_3 & anonIn_d_bits_source == 8'h70) & (_T_1 & anonIn_a_bits_source == 8'h70 | flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_113 <= ~(_T_3 & anonIn_d_bits_source == 8'h71) & (_T_1 & anonIn_a_bits_source == 8'h71 | flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_114 <= ~(_T_3 & anonIn_d_bits_source == 8'h72) & (_T_1 & anonIn_a_bits_source == 8'h72 | flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_115 <= ~(_T_3 & anonIn_d_bits_source == 8'h73) & (_T_1 & anonIn_a_bits_source == 8'h73 | flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_116 <= ~(_T_3 & anonIn_d_bits_source == 8'h74) & (_T_1 & anonIn_a_bits_source == 8'h74 | flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_117 <= ~(_T_3 & anonIn_d_bits_source == 8'h75) & (_T_1 & anonIn_a_bits_source == 8'h75 | flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_118 <= ~(_T_3 & anonIn_d_bits_source == 8'h76) & (_T_1 & anonIn_a_bits_source == 8'h76 | flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_119 <= ~(_T_3 & anonIn_d_bits_source == 8'h77) & (_T_1 & anonIn_a_bits_source == 8'h77 | flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_120 <= ~(_T_3 & anonIn_d_bits_source == 8'h78) & (_T_1 & anonIn_a_bits_source == 8'h78 | flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_121 <= ~(_T_3 & anonIn_d_bits_source == 8'h79) & (_T_1 & anonIn_a_bits_source == 8'h79 | flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_122 <= ~(_T_3 & anonIn_d_bits_source == 8'h7A) & (_T_1 & anonIn_a_bits_source == 8'h7A | flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_123 <= ~(_T_3 & anonIn_d_bits_source == 8'h7B) & (_T_1 & anonIn_a_bits_source == 8'h7B | flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_124 <= ~(_T_3 & anonIn_d_bits_source == 8'h7C) & (_T_1 & anonIn_a_bits_source == 8'h7C | flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_125 <= ~(_T_3 & anonIn_d_bits_source == 8'h7D) & (_T_1 & anonIn_a_bits_source == 8'h7D | flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_126 <= ~(_T_3 & anonIn_d_bits_source == 8'h7E) & (_T_1 & anonIn_a_bits_source == 8'h7E | flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_127 <= ~(_T_3 & anonIn_d_bits_source == 8'h7F) & (_T_1 & anonIn_a_bits_source == 8'h7F | flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_128 <= ~(_T_3 & anonIn_d_bits_source == 8'h80) & (_T_1 & anonIn_a_bits_source == 8'h80 | flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
end
if (_stalls_id_T_3) // @[FIFOFixer.scala:85:56]
stalls_id <= a_id; // @[Mux.scala:30:73]
if (_stalls_id_T_7) // @[FIFOFixer.scala:85:56]
stalls_id_1 <= a_id; // @[Mux.scala:30:73]
always @(posedge)
TLMonitor_5 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_24( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_982 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_982; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_982; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_1055 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1055; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1055; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1055; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_908 = _T_982 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_923 = _T_1055 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1026 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1026 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1008 = _T_1055 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1008 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1008 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1008 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_399( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_40( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_clear = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [7:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module RecFNToRecFN_7( // @[RecFNToRecFN.scala:44:5]
input [64:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out, // @[RecFNToRecFN.scala:48:16]
output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h0; // @[RecFNToRecFN.scala:44:5]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_3 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Periphery.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
case object DMI extends DebugExportProtocol
case object JTAG extends DebugExportProtocol
case object CJTAG extends DebugExportProtocol
case object APB extends DebugExportProtocol
/** Options for possible debug interfaces */
case class DebugAttachParams(
protocols: Set[DebugExportProtocol] = Set(DMI),
externalDisable: Boolean = false,
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = CBUS
) {
def dmi = protocols.contains(DMI)
def jtag = protocols.contains(JTAG)
def cjtag = protocols.contains(CJTAG)
def apb = protocols.contains(APB)
}
case object ExportDebug extends Field(DebugAttachParams())
class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) {
val clock = Clock()
val reset = Reset()
}
class DebugIO(implicit val p: Parameters) extends Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO()))
val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO)
val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32))))
//------------------------------
val ndreset = Output(Bool())
val dmactive = Output(Bool())
val dmactiveAck = Input(Bool())
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool()))
}
class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO {
}
class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle {
val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool())))
val hartIsInReset = Input(Vec(nComponents, Bool()))
}
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), or exports and hooks up APB,
* based on a global parameter.
*/
trait HasPeripheryDebug { this: BaseSubsystem =>
private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
val domain = ClockSinkNode(Seq(ClockSinkParameters()))
domain := tlbus.fixedClockNode
domain
}
lazy val debugOpt = p(DebugModuleKey).map { params =>
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}
tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") {
_ := TLWidthWidget(1) := sb2tl.node
}
}
tlDM
}
val debugNode = debugOpt.map(_.intnode)
val psd = InModuleBody {
val psd = IO(new PSDIO)
psd
}
val resetctrl = InModuleBody {
debugOpt.map { debug =>
debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset
debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock
val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size))
debug.module.io.hartIsInReset := resetctrl.hartIsInReset
resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
resetctrl
}
}
// noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
val debug = InModuleBody { noPrefix(debugOpt.map { debugmod =>
val debug = IO(new DebugIO)
require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
"You cannot have both DMI and JTAG interface in HasPeripheryDebug")
require(!(debug.clockeddmi.isDefined && debug.apb.isDefined),
"You cannot have both DMI and APB interface in HasPeripheryDebug")
require(!(debug.systemjtag.isDefined && debug.apb.isDefined),
"You cannot have both APB and JTAG interface in HasPeripheryDebug")
debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg }
(debug.apb
zip apbDebugNodeOpt
zip debugmod.module.io.apb_clock
zip debugmod.module.io.apb_reset).foreach {
case (((io, apb), c ), r) =>
apb.out(0)._1 <> io
c:= io.clock
r:= io.reset
}
debugmod.module.io.debug_reset := debug.reset
debugmod.module.io.debug_clock := debug.clock
debug.ndreset := debugmod.module.io.ctrl.ndreset
debug.dmactive := debugmod.module.io.ctrl.dmactive
debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck
debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}}
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B }
debug
})}
val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) }
def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled
dtm.io.jtag_clock := sj.jtag.TCK
dtm.io.jtag_reset := sj.reset
dtm.io.jtag_mfr_id := sj.mfr_id
dtm.io.jtag_part_number := sj.part_number
dtm.io.jtag_version := sj.version
dtm.rf_reset := sj.reset
debugOpt.map { outerdebug =>
outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi
outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK
outerdebug.module.io.dmi.get.dmiReset := sj.reset
}
dtm
}
}
/** BlackBox to export DMI interface */
class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Bool())
val debug = new DMIIO
val exit = Output(UInt(32.W))
})
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio.dmi <> io.debug
dutio.dmiClock := tbclk
dutio.dmiReset := tbreset
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimDTM.v")
addResource("/csrc/SimDTM.cc")
}
/** BlackBox to export JTAG interface */
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Input(Bool())
val init_done = Input(Bool())
val exit = Output(UInt(32.W))
})
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio.TCK := io.jtag.TCK
dutio.TMS := io.jtag.TMS
dutio.TDI := io.jtag.TDI
io.jtag.TDO := dutio.TDO
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimJTAG.v")
addResource("/csrc/SimJTAG.cc")
addResource("/csrc/remote_bitbang.h")
addResource("/csrc/remote_bitbang.cc")
}
object Debug {
def connectDebug(
debugOpt: Option[DebugIO],
resetctrlOpt: Option[ResetCtrlIO],
psdio: PSDIO,
c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode()))
(implicit p: Parameters): Unit = {
connectDebugClockAndReset(debugOpt, c)
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }}
debugOpt.map { debug =>
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r.asAsyncReset
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
sj.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
debug.apb.foreach { apb =>
require(false, "No support for connectDebug for an APB debug connection.")
}
psdio.psd.foreach { _ <> psd }
debug.disableDebug.foreach { x => x := false.B }
}
}
def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
debugOpt.foreach { debug =>
val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) |
debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) |
debug.apb.map(_.reset.asBool).getOrElse(false.B)
connectDebugClockHelper(debug, dmi_reset, c, sync)
}
}
def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
val debug_reset = Wire(Bool())
withClockAndReset(c, dmi_reset) {
val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset
debug_reset := debug_reset_syncd
}
// Need to clock DM during debug_reset because of synchronous reset, so keep
// the clock alive for one cycle after debug_reset asserts to action this behavior.
// The unit should also be clocked when dmactive is high.
withClockAndReset(c, debug_reset.asAsyncReset) {
val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive
val clock_en = RegNext(next=dmactiveAck, init=true.B)
val gated_clock =
if (!p(DebugModuleKey).get.clockGate) c
else ClockGate(c, clock_en, "debug_clock_gate")
debug.clock := gated_clock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset)
debug.dmactiveAck := dmactiveAck
}
}
def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = {
psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } )
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }}
debugOpt.map { debug =>
debug.clock := true.B.asClock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset)
debug.systemjtag.foreach { sj =>
sj.jtag.TCK := true.B.asClock
sj.jtag.TMS := true.B
sj.jtag.TDI := true.B
sj.jtag.TRSTn.foreach { r => r := true.B }
sj.reset := true.B.asAsyncReset
sj.mfr_id := 0.U
sj.part_number := 0.U
sj.version := 0.U
}
debug.clockeddmi.foreach { d =>
d.dmi.req.valid := false.B
d.dmi.req.bits.addr := 0.U
d.dmi.req.bits.data := 0.U
d.dmi.req.bits.op := 0.U
d.dmi.resp.ready := true.B
d.dmiClock := false.B.asClock
d.dmiReset := true.B.asAsyncReset
}
debug.apb.foreach { apb =>
apb.clock := false.B.asClock
apb.reset := true.B.asAsyncReset
apb.pready := false.B
apb.pslverr := false.B
apb.prdata := 0.U
apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser))
apb.psel := false.B
apb.penable := false.B
}
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
debug.disableDebug.foreach { x => x := false.B }
debug.dmactiveAck := false.B
debug.ndreset
}.getOrElse(false.B)
}
}
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File IOCell.scala:
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}
import chisel3.reflect.DataMirror
import chisel3.experimental.{Analog, BaseModule}
// The following four IO cell bundle types are bare-minimum functional connections
// for modeling 4 different IO cell scenarios. The intention is that the user
// would create wrapper modules that extend these interfaces with additional
// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
// but we want to avoid a dependency on an external libraries.
/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
* pad: off-chip (external) connection
* core: internal connection
*/
class AnalogIOCellBundle extends Bundle {
val pad = Analog(1.W) // Pad/bump signal (off-chip)
val core = Analog(1.W) // core signal (on-chip)
}
/** The base IO bundle for a signal with runtime-controllable direction
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalGPIOCellBundle extends Bundle {
val pad = Analog(1.W)
val i = Output(Bool())
val ie = Input(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital output signal
* pad: off-chip (external) connection
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalOutIOCellBundle extends Bundle {
val pad = Output(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital input signal
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
*/
class DigitalInIOCellBundle extends Bundle {
val pad = Input(Bool())
val i = Output(Bool())
val ie = Input(Bool())
}
trait IOCell extends BaseModule {
var iocell_name: Option[String] = None
/** Set IOCell name
* @param s Proposed name for the IOCell
*
* @return An inherited IOCell with given the proposed name
*/
def suggestName(s: String): this.type = {
iocell_name = Some(s)
super.suggestName(s)
}
}
trait AnalogIOCell extends IOCell {
val io: AnalogIOCellBundle
}
trait DigitalGPIOCell extends IOCell {
val io: DigitalGPIOCellBundle
}
trait DigitalInIOCell extends IOCell {
val io: DigitalInIOCellBundle
}
trait DigitalOutIOCell extends IOCell {
val io: DigitalOutIOCellBundle
}
// The following Generic IO cell black boxes have verilog models that mimic a very simple
// implementation of an IO cell. For building a real chip, it is important to implement
// and use similar classes which wrap the foundry-specific IO cells.
abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
val impl: String
val moduleName = this.getClass.getSimpleName
setInline(s"$moduleName.v", impl);
}
class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
val io = IO(new AnalogIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericAnalogIOCell(
inout pad,
inout core
);
assign core = 1'bz;
assign pad = core;
endmodule"""
}
class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
val io = IO(new DigitalGPIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
val io = IO(new DigitalInIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalInIOCell(
input pad,
output i,
input ie
);
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
val io = IO(new DigitalOutIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalOutIOCell(
output pad,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
endmodule"""
}
trait IOCellTypeParams {
def analog(): AnalogIOCell
def gpio(): DigitalGPIOCell
def input(): DigitalInIOCell
def output(): DigitalOutIOCell
}
case class GenericIOCellParams() extends IOCellTypeParams {
def analog() = Module(new GenericAnalogIOCell)
def gpio() = Module(new GenericDigitalGPIOCell)
def input() = Module(new GenericDigitalInIOCell)
def output() = Module(new GenericDigitalOutIOCell)
}
object IOCell {
/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
* signal and return the new IO and a Seq containing all generated IO cells.
* @param coreSignal The signal onto which to add IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @param abstractResetAsAsync When set, will coerce abstract resets to
* AsyncReset, and otherwise to Bool (sync reset)
* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
*/
def generateIOFromSignal[T <: Data](
coreSignal: T,
name: String,
typeParams: IOCellTypeParams = GenericIOCellParams(),
abstractResetAsAsync: Boolean = false
): (T, Seq[IOCell]) = {
val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
(padSignal, iocells)
}
/** Connect two identical signals together by adding IO cells between them and return a Seq
* containing all generated IO cells.
* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
* @param padSignal The pad-side (external) signal onto which to connect IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @return A Seq of all generated IO cell instances
*/
val toSyncReset: (Reset) => Bool = _.asBool
val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
def generateFromSignal[T <: Data, R <: Reset](
coreSignal: T,
padSignal: T,
name: Option[String] = None,
typeParams: IOCellTypeParams = GenericIOCellParams(),
concretizeResetFn: (Reset) => R = toSyncReset
): Seq[IOCell] = {
def genCell[T <: Data](
castToBool: (T) => Bool,
castFromBool: (Bool) => T
)(coreSignal: T,
padSignal: T
): Seq[IOCell] = {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocell = typeParams.input()
name.foreach(n => {
iocell.suggestName(n)
})
coreSignal := castFromBool(iocell.io.i)
iocell.io.ie := true.B
iocell.io.pad := castToBool(padSignal)
Seq(iocell)
}
case ActualDirection.Output => {
val iocell = typeParams.output()
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := castToBool(coreSignal)
iocell.io.oe := true.B
padSignal := castFromBool(iocell.io.pad)
Seq(iocell)
}
case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
}
}
def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
(coreSignal, padSignal) match {
case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) {
Seq()
} else {
require(
coreSignal.getWidth == 1,
"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
)
val iocell = typeParams.analog()
name.foreach(n => iocell.suggestName(n))
iocell.io.core <> coreSignal
padSignal <> iocell.io.pad
Seq(iocell)
}
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => coreSignal := 0.U
case _ => {}
}
Seq()
} else {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.input()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.pad := sig
iocell.io.ie := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
coreSignal := Cat(iocells.map(_.io.i).reverse)
iocells
}
case ActualDirection.Output => {
val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.output()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := sig
iocell.io.oe := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
padSignal := Cat(iocells.map(_.io.pad).reverse)
iocells
}
case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
total ++ ios
}
}
case (coreSignal: Record, padSignal: Record) => {
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
total ++ ios
}
}
case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
}
}
}
File ChipTop.scala:
package chipyard
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
* named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock,
* is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey
* drive clock and reset generation
*/
class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
with HasIOBinders {
// The system module specified by BuildSystem
lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children
// of ChipTop (ex: ClockGroup) do not receive clock or reset.
// However. anonymous children of ChipTop should not need an implicit Clock or Reset
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { }
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File ClockGate.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import org.chipsalliance.cde.config.{Field, Parameters}
import java.nio.file.{Files, Paths}
case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
case object ClockGateModelFile extends Field[Option[String]](None)
abstract class ClockGate extends BlackBox
with HasBlackBoxResource with HasBlackBoxPath {
val io = IO(new Bundle{
val in = Input(Clock())
val test_en = Input(Bool())
val en = Input(Bool())
val out = Output(Clock())
})
def addVerilogResource(vsrc: String): Unit = {
if (Files.exists(Paths.get(vsrc)))
addPath(vsrc)
else
addResource(vsrc)
}
}
object ClockGate {
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: Option[String] = None)(implicit p: Parameters): Clock = {
val cg = Module(p(ClockGateImpl)())
name.foreach(cg.suggestName(_))
p(ClockGateModelFile).map(cg.addVerilogResource(_))
cg.io.in := in
cg.io.test_en := false.B
cg.io.en := en
cg.io.out
}
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: String)(implicit p: Parameters): Clock =
apply(in, en, Some(name))
}
// behavioral model of Integrated Clock Gating cell
class EICG_wrapper extends ClockGate
File IOBinders.scala:
package chipyard.iobinders
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress, RegionType}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.soc.{CanHavePeripheryChipIdPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag}
object IOBinderTypes {
type IOBinderTuple = (Seq[Port[_]], Seq[IOCell])
type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]
}
import IOBinderTypes._
// System for instantiating binders based
// on the scala type of the Target (_not_ its IO). This avoids needing to
// duplicate harnesses (essentially test harnesses) for each target.
// IOBinders is map between string representations of traits to the desired
// IO connection behavior for tops matching that trait. We use strings to enable
// composition and overriding of IOBinders, much like how normal Keys in the config
// system are used/ At elaboration, the testharness traverses this set of functions,
// and functions which match the type of the DigitalTop are evaluated.
// You can add your own binder by adding a new (key, fn) pair, typically by using
// the OverrideIOBinder or ComposeIOBinder macros
case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
)
abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
val lazySystem: LazyModule
private val iobinders = p(IOBinders)
// Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
// context of a LazyRawModuleImp
private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) })
private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) })
private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
// A publicly accessible list of IO cells (useful for a floorplanning tool, for example)
val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports
val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
def ports = portMap.getWrappedValue.values.flatten.toSeq
InModuleBody {
println("IOCells generated by IOBinders:")
for ((k, v) <- iocellMap) {
if (!v.isEmpty) {
val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" IOBinder for $k generated:")
for ((t, c) <- cells) { println(s" $c X $t") }
}
}
println()
val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" Total generated ${iocells.size} IOCells:")
for ((t, c) <- totals) { println(s" $c X $t") }
}
}
// Note: The parameters instance is accessible only through LazyModule
// or LazyModuleImpLike. The self-type requirement in traits like
// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
// As a result, IOBinders only work on Modules which inherit LazyModule or
// or LazyModuleImpLike
object GetSystemParameters {
def apply(s: Any): Parameters = {
s match {
case s: LazyModule => s.p
case s: LazyModuleImpLike => s.p
case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
}
}
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => {
val upMap = up(IOBinders)
upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
}
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody {
t match {
case system: T => fn(system)
case _ => (Nil, Nil)
}
}}): IOBinderFunction)
)
class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => {
val empty = new ModuleValue[IOBinderTuple] {
def getWrappedValue: IOBinderTuple = (Nil, Nil)
}
if (isLazy) {
t match {
case system: T => fn(system)
case _ => empty
}
} else {
empty
}
}): IOBinderFunction)
)
// The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait.
// The "Compose" binders do not override previously defined IOBinders on the same trait
// The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration
// The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody
class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn)
class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn)
class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn)
class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn)
case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
}).unzip
(ports2d.flatten, cells2d.flatten)
}
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
GPIOPinsPort(() => io_gpio, i)
}
(ports, Nil)
}
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
I2CPort(() => i2c)
}
(ports, Nil)
}
})
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
(ports, cells2d.flatten)
}
})
// DOC include end: WithUARTIOCells
class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
(system: HasPeripherySPI) => {
// attach resource to 1st SPI
if (system.tlSpiNodes.size > 0) ResourceBinding {
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
SPIPort(() => io_spi)
})
(ports, Nil)
}
}
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
pin.i := iocell.io.i
iocell.io.pad <> ana
iocell
}
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
})
class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ExtIntPort(() => port)), cells)
} else {
system.interrupts := DontCare // why do I have to drive this 0-wide wire???
(Nil, Nil)
}
}
})
// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
class JTAGChipIO extends Bundle {
val TCK = Input(Clock())
val TMS = Input(Bool())
val TDI = Input(Bool())
val TDO = Output(Bool())
}
// WARNING: Don't disable syncReset unless you are trying to
// get around bugs in RTL simulators
class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := tlbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } }
system.debug.map { d =>
// Tie off extTrigger
d.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
// Tie off disableDebug
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
}
Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
(DMIPort(() => port), cells)
}
val jtagTuple = debug.systemjtag.map { j =>
val jtag_wire = Wire(new JTAGChipIO)
j.jtag.TCK := jtag_wire.TCK
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
(JTAGPort(() => port), cells)
}
require(!debug.apb.isDefined)
val allTuples = (dmiTuple ++ jtagTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
}).getOrElse((Nil, Nil))
}}}
}
})
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithChipIdIOCells extends OverrideIOBinder({
(system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ChipIdPort(() => port)), cells)
}).getOrElse(Nil, Nil)
})
class WithSerialTLPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val port = IO(chiselTypeOf(s.getWrappedValue))
port <> s.getWrappedValue
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
}).toSeq
(ports, Nil)
}
}
})
class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MMIOPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
}).toSeq
(ports, Nil)
}
}
})
class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
m <> port.bits
port.clock := clockBundle.clock
AXI4InPort(() => port, p(ExtIn).get)
}).toSeq
(ports, Nil)
}
}
})
class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryBlockDevice) => {
val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev =>
val p = GetSystemParameters(system)
val bdParams = p(BlockDeviceKey).get
val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
port <> bdev
BlockDevicePort(() => port, bdParams)
}).toSeq
(ports, Nil)
}
})
class WithNICIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryIceNIC) => {
val ports: Seq[NICPort] = system.icenicOpt.map({ n =>
val p = GetSystemParameters(system)
val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
port <> n
NICPort(() => port, p(NICKey).get)
}).toSeq
(ports, Nil)
}
})
class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
(system: TraceGenSystemModuleImp) => {
val success: Bool = IO(Output(Bool())).suggestName("success")
success := system.success
(Seq(SuccessPort(() => success)), Nil)
}
})
class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveTraceIO) => InModuleBody {
val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
val p = GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.totalTiles.values
val viewpointBus = system.asInstanceOf[HasConfigurableTLNetworkTopology].viewpointBus
val mems = viewpointBus.unifyManagers.filter { m =>
val regionTypes = Seq(RegionType.CACHED, RegionType.TRACKED, RegionType.UNCACHED, RegionType.IDEMPOTENT)
val ignoreAddresses = Seq(
0x10000 // bootrom is handled specially
)
regionTypes.contains(m.regionType) && !ignoreAddresses.contains(m.address.map(_.base).min)
}.map { m =>
val base = m.address.map(_.base).min
val size = m.address.map(_.max).max - base + 1
(base, size)
}
val useSimDTM = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
has_dtm = useSimDTM,
mems = mems,
// Connect using the legacy API for firesim only
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
)
TracePort(() => trace, cfg)
}
(ports.toSeq, Nil)
}
})
class WithCustomBootPin extends OverrideIOBinder({
(system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(CustomBootPort(() => port)), cells)
}).getOrElse((Nil, Nil))
})
class WithUARTTSIPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val uart_tsi = IO(new UARTTSIIO(p.uartParams))
uart_tsi <> p
(Seq(UARTTSIPort(() => uart_tsi)), Nil)
}).getOrElse((Nil, Nil))
})
class WithTLMemPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
(Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
}
})
class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
})
class WithNMITiedOff extends ComposeIOBinder({
(system: HasHierarchicalElementsRootContextModuleImp) => {
system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
}
(Nil, Nil)
}
})
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})
File ClockBinders.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
// Unsetting enable will prevent the divider/selector from actually modifying the clock,
// while preserving the address map. Unsetting enable should only be done for RTL
// simulators (Verilator) which do not model reset properly
class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
(Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
require(clockGroupAggNode.out.size == 1)
val (bundle, edge) = clockGroupAggNode.out(0)
val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz
val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
b.clock := clock_io
b.reset := reset_io
ClockPort(() => clock_io, freq)
}.toSeq
((clock_ios :+ ResetPort(() => reset_io)), Nil)
}
}
})
// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
bundle.member.data.foreach { b =>
b.clock := clock_io
b.reset := reset_io
}
}
(Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>
val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
(Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
}.getOrElse((Nil, Nil))
}
})
| module ChipTop( // @[ChipTop.scala:33:44]
output axi4_mmio_0_clock, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_aw_ready, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_aw_valid, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_aw_bits_id, // @[IOBinders.scala:416:22]
output [30:0] axi4_mmio_0_bits_aw_bits_addr, // @[IOBinders.scala:416:22]
output [7:0] axi4_mmio_0_bits_aw_bits_len, // @[IOBinders.scala:416:22]
output [2:0] axi4_mmio_0_bits_aw_bits_size, // @[IOBinders.scala:416:22]
output [1:0] axi4_mmio_0_bits_aw_bits_burst, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_aw_bits_lock, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_aw_bits_cache, // @[IOBinders.scala:416:22]
output [2:0] axi4_mmio_0_bits_aw_bits_prot, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_aw_bits_qos, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_w_ready, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_w_valid, // @[IOBinders.scala:416:22]
output [63:0] axi4_mmio_0_bits_w_bits_data, // @[IOBinders.scala:416:22]
output [7:0] axi4_mmio_0_bits_w_bits_strb, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_w_bits_last, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_b_ready, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_b_valid, // @[IOBinders.scala:416:22]
input [3:0] axi4_mmio_0_bits_b_bits_id, // @[IOBinders.scala:416:22]
input [1:0] axi4_mmio_0_bits_b_bits_resp, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_ar_ready, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_ar_valid, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_ar_bits_id, // @[IOBinders.scala:416:22]
output [30:0] axi4_mmio_0_bits_ar_bits_addr, // @[IOBinders.scala:416:22]
output [7:0] axi4_mmio_0_bits_ar_bits_len, // @[IOBinders.scala:416:22]
output [2:0] axi4_mmio_0_bits_ar_bits_size, // @[IOBinders.scala:416:22]
output [1:0] axi4_mmio_0_bits_ar_bits_burst, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_ar_bits_lock, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_ar_bits_cache, // @[IOBinders.scala:416:22]
output [2:0] axi4_mmio_0_bits_ar_bits_prot, // @[IOBinders.scala:416:22]
output [3:0] axi4_mmio_0_bits_ar_bits_qos, // @[IOBinders.scala:416:22]
output axi4_mmio_0_bits_r_ready, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_r_valid, // @[IOBinders.scala:416:22]
input [3:0] axi4_mmio_0_bits_r_bits_id, // @[IOBinders.scala:416:22]
input [63:0] axi4_mmio_0_bits_r_bits_data, // @[IOBinders.scala:416:22]
input [1:0] axi4_mmio_0_bits_r_bits_resp, // @[IOBinders.scala:416:22]
input axi4_mmio_0_bits_r_bits_last, // @[IOBinders.scala:416:22]
output uart_0_txd, // @[IOCell.scala:196:23]
input uart_0_rxd, // @[IOCell.scala:196:23]
output axi4_fbus_0_clock, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_aw_ready, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_aw_valid, // @[IOBinders.scala:436:22]
input [7:0] axi4_fbus_0_bits_aw_bits_id, // @[IOBinders.scala:436:22]
input [31:0] axi4_fbus_0_bits_aw_bits_addr, // @[IOBinders.scala:436:22]
input [7:0] axi4_fbus_0_bits_aw_bits_len, // @[IOBinders.scala:436:22]
input [2:0] axi4_fbus_0_bits_aw_bits_size, // @[IOBinders.scala:436:22]
input [1:0] axi4_fbus_0_bits_aw_bits_burst, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_aw_bits_lock, // @[IOBinders.scala:436:22]
input [3:0] axi4_fbus_0_bits_aw_bits_cache, // @[IOBinders.scala:436:22]
input [2:0] axi4_fbus_0_bits_aw_bits_prot, // @[IOBinders.scala:436:22]
input [3:0] axi4_fbus_0_bits_aw_bits_qos, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_w_ready, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_w_valid, // @[IOBinders.scala:436:22]
input [63:0] axi4_fbus_0_bits_w_bits_data, // @[IOBinders.scala:436:22]
input [7:0] axi4_fbus_0_bits_w_bits_strb, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_w_bits_last, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_b_ready, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_b_valid, // @[IOBinders.scala:436:22]
output [7:0] axi4_fbus_0_bits_b_bits_id, // @[IOBinders.scala:436:22]
output [1:0] axi4_fbus_0_bits_b_bits_resp, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_ar_ready, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_ar_valid, // @[IOBinders.scala:436:22]
input [7:0] axi4_fbus_0_bits_ar_bits_id, // @[IOBinders.scala:436:22]
input [31:0] axi4_fbus_0_bits_ar_bits_addr, // @[IOBinders.scala:436:22]
input [7:0] axi4_fbus_0_bits_ar_bits_len, // @[IOBinders.scala:436:22]
input [2:0] axi4_fbus_0_bits_ar_bits_size, // @[IOBinders.scala:436:22]
input [1:0] axi4_fbus_0_bits_ar_bits_burst, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_ar_bits_lock, // @[IOBinders.scala:436:22]
input [3:0] axi4_fbus_0_bits_ar_bits_cache, // @[IOBinders.scala:436:22]
input [2:0] axi4_fbus_0_bits_ar_bits_prot, // @[IOBinders.scala:436:22]
input [3:0] axi4_fbus_0_bits_ar_bits_qos, // @[IOBinders.scala:436:22]
input axi4_fbus_0_bits_r_ready, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_r_valid, // @[IOBinders.scala:436:22]
output [7:0] axi4_fbus_0_bits_r_bits_id, // @[IOBinders.scala:436:22]
output [63:0] axi4_fbus_0_bits_r_bits_data, // @[IOBinders.scala:436:22]
output [1:0] axi4_fbus_0_bits_r_bits_resp, // @[IOBinders.scala:436:22]
output axi4_fbus_0_bits_r_bits_last, // @[IOBinders.scala:436:22]
input custom_boot, // @[IOCell.scala:196:23]
input jtag_TCK, // @[IOCell.scala:196:23]
input jtag_TMS, // @[IOCell.scala:196:23]
input jtag_TDI, // @[IOCell.scala:196:23]
output jtag_TDO, // @[IOCell.scala:196:23]
input reset_io, // @[ClockBinders.scala:87:24]
input clock_uncore, // @[ClockBinders.scala:95:26]
output clock_tap, // @[IOCell.scala:196:23]
output serial_tl_0_in_ready, // @[IOCell.scala:196:23]
input serial_tl_0_in_valid, // @[IOCell.scala:196:23]
input [31:0] serial_tl_0_in_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_out_ready, // @[IOCell.scala:196:23]
output serial_tl_0_out_valid, // @[IOCell.scala:196:23]
output [31:0] serial_tl_0_out_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_clock_in // @[IOCell.scala:196:23]
);
wire _iocell_serial_tl_0_in_valid_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_31_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_30_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_29_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_28_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_27_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_26_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_25_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_24_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_23_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_22_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_21_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_20_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_19_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_18_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_17_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_16_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_15_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_14_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_13_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_12_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_11_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_10_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_9_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_8_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_7_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_6_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_5_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_4_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_3_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_2_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_1_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_ready_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_bits_phit_31_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_30_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_29_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_28_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_27_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_26_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_25_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_24_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_23_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_22_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_21_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_20_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_19_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_18_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_17_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_16_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_15_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_14_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_13_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_12_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_11_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_10_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_9_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_8_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_7_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_6_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_5_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_4_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_3_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_2_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_1_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_pad; // @[IOCell.scala:177:24]
wire _gated_clock_debug_clock_gate_out; // @[ClockGate.scala:36:20]
wire _system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _iocell_custom_boot_i; // @[IOCell.scala:176:23]
wire _iocell_uart_0_rxd_i; // @[IOCell.scala:176:23]
wire _system_debug_dmactive; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_in_ready; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_out_valid; // @[ChipTop.scala:27:35]
wire [31:0] _system_serial_tl_0_out_bits_phit; // @[ChipTop.scala:27:35]
wire _system_uart_0_txd; // @[ChipTop.scala:27:35]
wire axi4_mmio_0_bits_aw_ready_0 = axi4_mmio_0_bits_aw_ready; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_w_ready_0 = axi4_mmio_0_bits_w_ready; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_b_valid_0 = axi4_mmio_0_bits_b_valid; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_b_bits_id_0 = axi4_mmio_0_bits_b_bits_id; // @[ChipTop.scala:33:44]
wire [1:0] axi4_mmio_0_bits_b_bits_resp_0 = axi4_mmio_0_bits_b_bits_resp; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_ar_ready_0 = axi4_mmio_0_bits_ar_ready; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_r_valid_0 = axi4_mmio_0_bits_r_valid; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_r_bits_id_0 = axi4_mmio_0_bits_r_bits_id; // @[ChipTop.scala:33:44]
wire [63:0] axi4_mmio_0_bits_r_bits_data_0 = axi4_mmio_0_bits_r_bits_data; // @[ChipTop.scala:33:44]
wire [1:0] axi4_mmio_0_bits_r_bits_resp_0 = axi4_mmio_0_bits_r_bits_resp; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_r_bits_last_0 = axi4_mmio_0_bits_r_bits_last; // @[ChipTop.scala:33:44]
wire uart_0_rxd_0 = uart_0_rxd; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_aw_valid_0 = axi4_fbus_0_bits_aw_valid; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_aw_bits_id_0 = axi4_fbus_0_bits_aw_bits_id; // @[ChipTop.scala:33:44]
wire [31:0] axi4_fbus_0_bits_aw_bits_addr_0 = axi4_fbus_0_bits_aw_bits_addr; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_aw_bits_len_0 = axi4_fbus_0_bits_aw_bits_len; // @[ChipTop.scala:33:44]
wire [2:0] axi4_fbus_0_bits_aw_bits_size_0 = axi4_fbus_0_bits_aw_bits_size; // @[ChipTop.scala:33:44]
wire [1:0] axi4_fbus_0_bits_aw_bits_burst_0 = axi4_fbus_0_bits_aw_bits_burst; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_aw_bits_lock_0 = axi4_fbus_0_bits_aw_bits_lock; // @[ChipTop.scala:33:44]
wire [3:0] axi4_fbus_0_bits_aw_bits_cache_0 = axi4_fbus_0_bits_aw_bits_cache; // @[ChipTop.scala:33:44]
wire [2:0] axi4_fbus_0_bits_aw_bits_prot_0 = axi4_fbus_0_bits_aw_bits_prot; // @[ChipTop.scala:33:44]
wire [3:0] axi4_fbus_0_bits_aw_bits_qos_0 = axi4_fbus_0_bits_aw_bits_qos; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_w_valid_0 = axi4_fbus_0_bits_w_valid; // @[ChipTop.scala:33:44]
wire [63:0] axi4_fbus_0_bits_w_bits_data_0 = axi4_fbus_0_bits_w_bits_data; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_w_bits_strb_0 = axi4_fbus_0_bits_w_bits_strb; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_w_bits_last_0 = axi4_fbus_0_bits_w_bits_last; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_b_ready_0 = axi4_fbus_0_bits_b_ready; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_ar_valid_0 = axi4_fbus_0_bits_ar_valid; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_ar_bits_id_0 = axi4_fbus_0_bits_ar_bits_id; // @[ChipTop.scala:33:44]
wire [31:0] axi4_fbus_0_bits_ar_bits_addr_0 = axi4_fbus_0_bits_ar_bits_addr; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_ar_bits_len_0 = axi4_fbus_0_bits_ar_bits_len; // @[ChipTop.scala:33:44]
wire [2:0] axi4_fbus_0_bits_ar_bits_size_0 = axi4_fbus_0_bits_ar_bits_size; // @[ChipTop.scala:33:44]
wire [1:0] axi4_fbus_0_bits_ar_bits_burst_0 = axi4_fbus_0_bits_ar_bits_burst; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_ar_bits_lock_0 = axi4_fbus_0_bits_ar_bits_lock; // @[ChipTop.scala:33:44]
wire [3:0] axi4_fbus_0_bits_ar_bits_cache_0 = axi4_fbus_0_bits_ar_bits_cache; // @[ChipTop.scala:33:44]
wire [2:0] axi4_fbus_0_bits_ar_bits_prot_0 = axi4_fbus_0_bits_ar_bits_prot; // @[ChipTop.scala:33:44]
wire [3:0] axi4_fbus_0_bits_ar_bits_qos_0 = axi4_fbus_0_bits_ar_bits_qos; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_r_ready_0 = axi4_fbus_0_bits_r_ready; // @[ChipTop.scala:33:44]
wire jtag_TCK_0 = jtag_TCK; // @[ChipTop.scala:33:44]
wire jtag_TMS_0 = jtag_TMS; // @[ChipTop.scala:33:44]
wire jtag_TDI_0 = jtag_TDI; // @[ChipTop.scala:33:44]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[ChipTop.scala:33:44]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[ChipTop.scala:33:44]
wire clockGroupAggNodeOut_member_allClocks_uncore_clock = clock_uncore; // @[MixedNode.scala:542:17]
wire clockGroupAggNodeOut_member_allClocks_uncore_reset = reset_io; // @[MixedNode.scala:542:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroupAggNodeIn_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupAggNodeIn_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:542:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:542:17]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _clock_tap_T; // @[IOCell.scala:248:61]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_1_clock; // @[MixedNode.scala:551:17]
wire _iocell_jtag_TCK_io_pad_T = jtag_TCK_0; // @[IOCell.scala:248:44]
wire [31:0] _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire _iocell_serial_tl_0_clock_in_io_pad_T = serial_tl_0_clock_in_0; // @[IOCell.scala:248:44]
wire [3:0] axi4_mmio_0_bits_aw_bits_id_0; // @[ChipTop.scala:33:44]
wire [30:0] axi4_mmio_0_bits_aw_bits_addr_0; // @[ChipTop.scala:33:44]
wire [7:0] axi4_mmio_0_bits_aw_bits_len_0; // @[ChipTop.scala:33:44]
wire [2:0] axi4_mmio_0_bits_aw_bits_size_0; // @[ChipTop.scala:33:44]
wire [1:0] axi4_mmio_0_bits_aw_bits_burst_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_aw_bits_lock_0; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_aw_bits_cache_0; // @[ChipTop.scala:33:44]
wire [2:0] axi4_mmio_0_bits_aw_bits_prot_0; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_aw_bits_qos_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_aw_valid_0; // @[ChipTop.scala:33:44]
wire [63:0] axi4_mmio_0_bits_w_bits_data_0; // @[ChipTop.scala:33:44]
wire [7:0] axi4_mmio_0_bits_w_bits_strb_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_w_bits_last_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_w_valid_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_b_ready_0; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_ar_bits_id_0; // @[ChipTop.scala:33:44]
wire [30:0] axi4_mmio_0_bits_ar_bits_addr_0; // @[ChipTop.scala:33:44]
wire [7:0] axi4_mmio_0_bits_ar_bits_len_0; // @[ChipTop.scala:33:44]
wire [2:0] axi4_mmio_0_bits_ar_bits_size_0; // @[ChipTop.scala:33:44]
wire [1:0] axi4_mmio_0_bits_ar_bits_burst_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_ar_bits_lock_0; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_ar_bits_cache_0; // @[ChipTop.scala:33:44]
wire [2:0] axi4_mmio_0_bits_ar_bits_prot_0; // @[ChipTop.scala:33:44]
wire [3:0] axi4_mmio_0_bits_ar_bits_qos_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_ar_valid_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_bits_r_ready_0; // @[ChipTop.scala:33:44]
wire axi4_mmio_0_clock_0; // @[ChipTop.scala:33:44]
wire uart_0_txd_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_aw_ready_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_w_ready_0; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_b_bits_id_0; // @[ChipTop.scala:33:44]
wire [1:0] axi4_fbus_0_bits_b_bits_resp_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_b_valid_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_ar_ready_0; // @[ChipTop.scala:33:44]
wire [7:0] axi4_fbus_0_bits_r_bits_id_0; // @[ChipTop.scala:33:44]
wire [63:0] axi4_fbus_0_bits_r_bits_data_0; // @[ChipTop.scala:33:44]
wire [1:0] axi4_fbus_0_bits_r_bits_resp_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_r_bits_last_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_bits_r_valid_0; // @[ChipTop.scala:33:44]
wire axi4_fbus_0_clock_0; // @[ChipTop.scala:33:44]
wire jtag_TDO_0; // @[ChipTop.scala:33:44]
wire _clock_tap_output; // @[ChipTop.scala:33:44]
wire serial_tl_0_in_ready_0; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_valid_0; // @[ChipTop.scala:33:44]
assign axi4_mmio_0_clock_0 = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
assign axi4_fbus_0_clock_0 = clockSinkNodeIn_1_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_1_reset; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_2_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_2_reset; // @[MixedNode.scala:551:17]
wire _system_resetctrl_hartIsInReset_0_T = clockSinkNodeIn_2_reset; // @[MixedNode.scala:551:17]
wire _system_debug_systemjtag_reset_T = clockSinkNodeIn_2_reset; // @[MixedNode.scala:551:17]
wire _dmi_reset_T; // @[Periphery.scala:281:38]
wire _dmi_reset_T_1 = _dmi_reset_T; // @[Periphery.scala:280:82, :281:38]
wire dmi_reset = _dmi_reset_T_1; // @[Periphery.scala:280:82, :281:65]
wire debug_reset_syncd; // @[Periphery.scala:290:40]
wire debug_reset; // @[Periphery.scala:288:27]
wire _debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset_syncd = ~_debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset = debug_reset_syncd; // @[Periphery.scala:288:27, :290:40]
wire dmactiveAck; // @[ShiftReg.scala:48:24]
reg clock_en; // @[Periphery.scala:298:29]
wire _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire jtag_wire_TCK; // @[IOBinders.scala:339:31]
wire jtag_wire_TMS; // @[IOBinders.scala:339:31]
wire jtag_wire_TDI; // @[IOBinders.scala:339:31]
wire jtag_wire_TDO; // @[IOBinders.scala:339:31]
assign jtag_wire_TCK = _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire _iocell_jtag_TCK_io_pad_T_1 = _iocell_jtag_TCK_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:44]
wire _iocell_clock_tap_io_o_T_1 = _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:{44,51}]
assign _clock_tap_output = _clock_tap_T; // @[IOCell.scala:248:61]
wire _iocell_serial_tl_0_clock_in_io_pad_T_1 = _iocell_serial_tl_0_clock_in_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_1_pad, _iocell_serial_tl_0_out_bits_phit_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_3_pad, _iocell_serial_tl_0_out_bits_phit_2_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_5_pad, _iocell_serial_tl_0_out_bits_phit_4_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_7_pad, _iocell_serial_tl_0_out_bits_phit_6_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_hi = {serial_tl_0_out_bits_phit_lo_lo_hi_hi, serial_tl_0_out_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_9_pad, _iocell_serial_tl_0_out_bits_phit_8_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_11_pad, _iocell_serial_tl_0_out_bits_phit_10_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_lo = {serial_tl_0_out_bits_phit_lo_hi_lo_hi, serial_tl_0_out_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_13_pad, _iocell_serial_tl_0_out_bits_phit_12_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_15_pad, _iocell_serial_tl_0_out_bits_phit_14_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_hi = {serial_tl_0_out_bits_phit_lo_hi_hi_hi, serial_tl_0_out_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_hi = {serial_tl_0_out_bits_phit_lo_hi_hi, serial_tl_0_out_bits_phit_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_lo = {serial_tl_0_out_bits_phit_lo_hi, serial_tl_0_out_bits_phit_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_17_pad, _iocell_serial_tl_0_out_bits_phit_16_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_19_pad, _iocell_serial_tl_0_out_bits_phit_18_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_lo = {serial_tl_0_out_bits_phit_hi_lo_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_21_pad, _iocell_serial_tl_0_out_bits_phit_20_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_23_pad, _iocell_serial_tl_0_out_bits_phit_22_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_hi = {serial_tl_0_out_bits_phit_hi_lo_hi_hi, serial_tl_0_out_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_lo = {serial_tl_0_out_bits_phit_hi_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_25_pad, _iocell_serial_tl_0_out_bits_phit_24_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_27_pad, _iocell_serial_tl_0_out_bits_phit_26_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_lo = {serial_tl_0_out_bits_phit_hi_hi_lo_hi, serial_tl_0_out_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_29_pad, _iocell_serial_tl_0_out_bits_phit_28_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_31_pad, _iocell_serial_tl_0_out_bits_phit_30_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_hi = {serial_tl_0_out_bits_phit_hi_hi, serial_tl_0_out_bits_phit_hi_lo}; // @[IOCell.scala:312:31]
assign _serial_tl_0_out_bits_phit_T = {serial_tl_0_out_bits_phit_hi, serial_tl_0_out_bits_phit_lo}; // @[IOCell.scala:312:31]
assign serial_tl_0_out_bits_phit_0 = _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_1_i, _iocell_serial_tl_0_in_bits_phit_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_3_i, _iocell_serial_tl_0_in_bits_phit_2_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_5_i, _iocell_serial_tl_0_in_bits_phit_4_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_7_i, _iocell_serial_tl_0_in_bits_phit_6_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_hi = {system_serial_tl_0_in_bits_phit_lo_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_9_i, _iocell_serial_tl_0_in_bits_phit_8_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_11_i, _iocell_serial_tl_0_in_bits_phit_10_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_lo = {system_serial_tl_0_in_bits_phit_lo_hi_lo_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_13_i, _iocell_serial_tl_0_in_bits_phit_12_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_15_i, _iocell_serial_tl_0_in_bits_phit_14_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_lo = {system_serial_tl_0_in_bits_phit_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_17_i, _iocell_serial_tl_0_in_bits_phit_16_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_19_i, _iocell_serial_tl_0_in_bits_phit_18_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_lo = {system_serial_tl_0_in_bits_phit_hi_lo_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_21_i, _iocell_serial_tl_0_in_bits_phit_20_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_23_i, _iocell_serial_tl_0_in_bits_phit_22_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_hi = {system_serial_tl_0_in_bits_phit_hi_lo_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_lo = {system_serial_tl_0_in_bits_phit_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_25_i, _iocell_serial_tl_0_in_bits_phit_24_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_27_i, _iocell_serial_tl_0_in_bits_phit_26_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_lo = {system_serial_tl_0_in_bits_phit_hi_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_29_i, _iocell_serial_tl_0_in_bits_phit_28_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_31_i, _iocell_serial_tl_0_in_bits_phit_30_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_hi = {system_serial_tl_0_in_bits_phit_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo}; // @[IOCell.scala:295:32]
wire [31:0] _system_serial_tl_0_in_bits_phit_T = {system_serial_tl_0_in_bits_phit_hi, system_serial_tl_0_in_bits_phit_lo}; // @[IOCell.scala:295:32]
always @(posedge clockSinkNodeIn_2_clock or posedge debug_reset) begin // @[Periphery.scala:288:27]
if (debug_reset) // @[Periphery.scala:288:27]
clock_en <= 1'h1; // @[Periphery.scala:298:29]
else // @[MixedNode.scala:551:17]
clock_en <= dmactiveAck; // @[ShiftReg.scala:48:24]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Frontend.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.tile.{CoreBundle, BaseTile}
import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut}
import freechips.rocketchip.util.{ClockGate, ShiftQueue, property}
import freechips.rocketchip.util.UIntToAugmentedUInt
class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(vaddrBitsExtended.W)
val speculative = Bool()
}
class FrontendExceptions extends Bundle {
val pf = new Bundle {
val inst = Bool()
}
val gf = new Bundle {
val inst = Bool()
}
val ae = new Bundle {
val inst = Bool()
}
}
class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
val btb = new BTBResp
val pc = UInt(vaddrBitsExtended.W) // ID stage PC
val data = UInt((fetchWidth * coreInstBits).W)
val mask = Bits(fetchWidth.W)
val xcpt = new FrontendExceptions
val replay = Bool()
}
class FrontendPerfEvents extends Bundle {
val acquire = Bool()
val tlbMiss = Bool()
}
class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val might_request = Output(Bool())
val clock_enabled = Input(Bool())
val req = Valid(new FrontendReq)
val sfence = Valid(new SFenceReq)
val resp = Flipped(Decoupled(new FrontendResp))
val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W)))
val gpa_is_pte = Input(Bool())
val btb_update = Valid(new BTBUpdate)
val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate)
val flush_icache = Output(Bool())
val npc = Input(UInt(vaddrBitsExtended.W))
val perf = Input(new FrontendPerfEvents())
val progress = Output(Bool())
}
class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(icacheParams, tileId))
val masterNode = icache.masterNode
val slaveNode = icache.slaveNode
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W)))
}
class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) {
val cpu = Flipped(new FrontendIO())
val ptw = new TLBPTWIO()
val errors = new ICacheErrors
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasRocketCoreParameters
with HasL1ICacheParameters {
val io = IO(new FrontendBundle(outer))
val io_reset_vector = outer.resetVectorSinkNode.bundle
implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0)
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cpu.might_request
io.cpu.clock_enabled := clock_en
assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "icache_clock_gate")
icache.clock := gated_clock
icache.io.clock_enabled := clock_en
withClock (gated_clock) { // entering gated-clock domain
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages)))
val s1_valid = Reg(Bool())
val s2_valid = RegInit(false.B)
val s0_fq_has_space =
!fq.io.mask(fq.io.mask.getWidth-3) ||
(!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) ||
(!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid))
val s0_valid = io.cpu.req.valid || s0_fq_has_space
s1_valid := s0_valid
val s1_pc = Reg(UInt(vaddrBitsExtended.W))
val s1_speculative = Reg(Bool())
val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector))
val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
val s2_btb_resp_bits = Reg(new BTBResp)
val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
val s2_tlb_resp = Reg(tlb.io.resp.cloneType)
val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst
val s2_speculative = RegInit(false.B)
val s2_partial_insn_valid = RegInit(false.B)
val s2_partial_insn = Reg(UInt(coreInstBits.W))
val wrong_path = RegInit(false.B)
val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U)
val ntpc = s1_base_pc + fetchBytes.U
val predicted_npc = WireDefault(ntpc)
val predicted_taken = WireDefault(false.B)
val s2_replay = Wire(Bool())
s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B)
val npc = Mux(s2_replay, s2_pc, predicted_npc)
s1_pc := io.cpu.npc
// consider RVC fetches across blocks to be non-speculative if the first
// part was non-speculative
val s0_speculative =
if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken
else true.B
s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative))
val s2_redirect = WireDefault(io.cpu.req.valid)
s2_valid := false.B
when (!s2_replay) {
s2_valid := !s2_redirect
s2_pc := s1_pc
s2_speculative := s1_speculative
s2_tlb_resp := tlb.io.resp
}
val recent_progress_counter_init = 3.U
val recent_progress_counter = RegInit(recent_progress_counter_init)
val recent_progress = recent_progress_counter > 0.U
when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U }
when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init }
val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid && !s2_replay
tlb.io.req.bits.cmd := M_XRD // Frontend only reads
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := false.B
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U
tlb.io.req.bits.prv := io.ptw.status.prv
tlb.io.req.bits.v := io.ptw.status.v
tlb.io.sfence := io.cpu.sfence
tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill
icache.io.req.valid := s0_valid
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill
icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt
icache.io.s2_cacheable := s2_tlb_resp.cacheable
icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch
fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill))
fq.io.enq.bits.pc := s2_pc
io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc))
fq.io.enq.bits.data := icache.io.resp.bits.data
fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss)
fq.io.enq.bits.btb := s2_btb_resp_bits
fq.io.enq.bits.btb.taken := s2_btb_taken
fq.io.enq.bits.xcpt := s2_tlb_resp
assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))
when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B }
if (usingBTB) {
val btb = Module(new BTB)
btb.io.flush := false.B
btb.io.req.valid := false.B
btb.io.req.bits.addr := s1_pc
btb.io.btb_update := io.cpu.btb_update
btb.io.bht_update := io.cpu.bht_update
btb.io.ras_update.valid := false.B
btb.io.ras_update.bits := DontCare
btb.io.bht_advance.valid := false.B
btb.io.bht_advance.bits := DontCare
when (!s2_replay) {
btb.io.req.valid := !s2_redirect
s2_btb_resp_valid := btb.io.resp.valid
s2_btb_resp_bits := btb.io.resp.bits
}
when (btb.io.resp.valid && btb.io.resp.bits.taken) {
predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
predicted_taken := true.B
}
val force_taken = io.ptw.customCSRs.bpmStatic
when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B }
when (force_taken) { btb.io.bht_update.valid := false.B }
val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U)
val taken_idx = Wire(UInt())
val after_idx = Wire(UInt())
val useRAS = WireDefault(false.B)
val updateBTB = WireDefault(false.B)
// If !prevTaken, ras_update / bht_update is always invalid.
taken_idx := DontCare
after_idx := DontCare
def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U
val prevRVI = prevValid && !insnIsRVC(prevBits)
val valid = fq.io.enq.bits.mask(idx) && !prevRVI
val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
val rvc = insnIsRVC(bits)
val rviBits = Cat(bits, prevBits)
val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0)
val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0)
val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0)
val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
val rviCall = (rviJALR || rviJump) && rviBits(7)
val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL
val rvcJump = bits === Instructions.C_J || rvcJAL
val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt)
val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U
val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U
val rvcCall = rvcJAL || rvcJALR
val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
val predict_taken = s2_btb_resp_bits.bht.taken || force_taken
val taken =
prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) ||
valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken)
val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
val predictJump = prevRVI && rviJump || valid && rvcJump
val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch)
when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) {
// The BTB has predicted that the middle of an RVI instruction is
// a branch! Flush the BTB and the pipeline.
btb.io.flush := true.B
fq.io.enq.bits.replay := true.B
wrong_path := true.B
ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path")
}
when (!prevTaken) {
taken_idx := idx.U
after_idx := (idx + 1).U
btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret,
Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call,
Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch,
CFIType.jump)))
when (!s2_btb_taken) {
when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) {
wrong_path := true.B
}
when (s2_valid && predictReturn) {
useRAS := true.B
}
when (s2_valid && (predictBranch || predictJump)) {
val pc = s2_base_pc | (idx*coreInstBytes).U
val npc =
if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
predicted_npc := npc.asUInt
}
}
when (prevRVI && rviBranch || valid && rvcBranch) {
btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path
btb.io.bht_advance.bits := s2_btb_resp_bits
}
when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) {
updateBTB := true.B
}
}
if (idx == fetchWidth-1) {
when (fq.io.enq.fire) {
s2_partial_insn_valid := false.B
when (valid && !prevTaken && !rvc) {
s2_partial_insn_valid := true.B
s2_partial_insn := bits | 0x3.U
}
}
prevTaken || taken
} else {
scanInsns(idx + 1, valid, bits, prevTaken || taken)
}
}
when (!io.cpu.btb_update.valid) {
val fetch_bubble_likely = !fq.io.mask(1)
btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB
btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U
btb.io.btb_update.bits.isValid := true.B
btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType
btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes))
btb.io.btb_update.bits.pc := s2_base_pc
}
btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
when (useRAS) {
predicted_npc := btb.io.ras_head.bits
}
when (fq.io.enq.fire && (s2_btb_taken || taken)) {
s2_partial_insn_valid := false.B
}
when (!s2_btb_taken) {
when (taken) {
fq.io.enq.bits.btb.bridx := taken_idx
fq.io.enq.bits.btb.taken := true.B
fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U
when (fq.io.enq.fire) { s2_redirect := true.B }
}
}
assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))
when (s2_redirect) { s2_partial_insn_valid := false.B }
when (io.cpu.req.valid) { wrong_path := false.B }
}
io.cpu.resp <> fq.io.deq
// supply guest physical address to commit stage
val gpa_valid = Reg(Bool())
val gpa = Reg(UInt(vaddrBitsExtended.W))
val gpa_is_pte = Reg(Bool())
when (fq.io.enq.fire && s2_tlb_resp.gf.inst) {
when (!gpa_valid) {
gpa := s2_tlb_resp.gpa
gpa_is_pte := s2_tlb_resp.gpa_is_pte
}
gpa_valid := true.B
}
when (io.cpu.req.valid) {
gpa_valid := false.B
}
io.cpu.gpa.valid := gpa_valid
io.cpu.gpa.bits := gpa
io.cpu.gpa_is_pte := gpa_is_pte
// performance events
io.cpu.perf.acquire := icache.io.perf.acquire
io.cpu.perf.tlbMiss := io.ptw.req.fire
io.errors := icache.io.errors
// gate the clock
clock_en_reg := !rocketParams.clockGate.B ||
io.cpu.might_request || // chicken bit
icache.io.keep_clock_enabled || // I$ miss or ITIM access
s1_valid || s2_valid || // some fetch in flight
!tlb.io.req.ready || // handling TLB miss
!fq.io.mask(fq.io.mask.getWidth-1) // queue not full
} // leaving gated-clock domain
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U)
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId))
tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode
connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode }
frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode }
frontend.resetVectorSinkNode := resetVectorNexusNode
nPTWPorts += 1
// This should be a None in the case of not having an ITIM address, when we
// don't actually use the device that is instantiated in the frontend.
private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None
}
trait HasICacheFrontendModule extends CanHavePTWModule {
val outer: HasICacheFrontend
ptwPorts += outer.frontend.module.io.ptw
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File RocketCore.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.withClock
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ArrayBuffer
case class RocketCoreParams(
xLen: Int = 64,
pgLevels: Int = 3, // sv39 default
bootFreqHz: BigInt = 0,
useVM: Boolean = true,
useUser: Boolean = false,
useSupervisor: Boolean = false,
useHypervisor: Boolean = false,
useDebug: Boolean = true,
useAtomics: Boolean = true,
useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true,
useRVE: Boolean = false,
useConditionalZero: Boolean = false,
useZba: Boolean = false,
useZbb: Boolean = false,
useZbs: Boolean = false,
nLocalInterrupts: Int = 0,
useNMI: Boolean = false,
nBreakpoints: Int = 1,
useBPWatch: Boolean = false,
mcontextWidth: Int = 0,
scontextWidth: Int = 0,
nPMPs: Int = 8,
nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true,
haveCFlush: Boolean = false,
misaWritable: Boolean = true,
nL2TLBEntries: Int = 0,
nL2TLBWays: Int = 1,
nPTECacheEntries: Int = 8,
mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
branchPredictionModeCSR: Boolean = false,
clockGate: Boolean = false,
mvendorid: Int = 0, // 0 means non-commercial implementation
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
vector: Option[RocketCoreVectorParams] = None
) extends CoreParams {
val lgPauseCycles = 5
val haveFSDirty = false
val pmpGranularity: Int = if (useHypervisor) 4096 else 4
val fetchWidth: Int = if (useCompressed) 2 else 1
// fetchWidth doubled, but coreInstBytes halved, for RVC:
val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1)
val retireWidth: Int = 1
val instBits: Int = if (useCompressed) 16 else 32
val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace
override val useVector = vector.isDefined
override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)
override def vLen = vector.map(_.vLen).getOrElse(0)
override def eLen = vector.map(_.eLen).getOrElse(0)
override def vfLen = vector.map(_.vfLen).getOrElse(0)
override def vfh = vector.map(_.vfh).getOrElse(false)
override def vExts = vector.map(_.vExts).getOrElse(Nil)
override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs
}
trait HasRocketCoreParameters extends HasCoreParameters {
lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams]
val fastLoadWord = rocketParams.fastLoadWord
val fastLoadByte = rocketParams.fastLoadByte
val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this
require(!fastLoadByte || fastLoadWord)
require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty")
}
class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters {
override def bpmCSR = {
rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0))))
}
private def haveDCache = tileParams.dcache.get.scratch.isEmpty
override def chickenCSR = {
val mask = BigInt(
tileParams.dcache.get.clockGate.toInt << 0 |
rocketParams.clockGate.toInt << 1 |
rocketParams.clockGate.toInt << 2 |
1 << 3 | // disableSpeculativeICacheRefill
haveDCache.toInt << 9 | // suppressCorruptOnGrantData
tileParams.icache.get.prefetch.toInt << 17
)
Some(CustomCSR(chickenCSRId, mask, Some(mask)))
}
def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B)
def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1))
def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
// mimpid encodes a release version in the form of a BCD-encoded datestamp.
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
}
class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) {
val buserror = Option.when(hasBeu)(Bool())
}
trait HasRocketCoreIO extends HasRocketCoreParameters {
implicit val p: Parameters
def nTotalRoCCCSRs: Int
val io = IO(new CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined))
val imem = new FrontendIO
val dmem = new HellaCacheIO
val ptw = Flipped(new DatapathPTWIO())
val fpu = Flipped(new FPUCoreIO())
val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
val trace = Output(new TraceBundle)
val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None
})
}
class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
with HasRocketCoreParameters
with HasRocketCoreIO {
def nTotalRoCCCSRs = tile.roccCSRs.flatten.size
import ALU._
val clock_en_reg = RegInit(true.B)
val long_latency_stall = Reg(Bool())
val id_reg_pause = Reg(Bool())
val imem_might_request_reg = Reg(Bool())
val clock_en = WireDefault(true.B)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "rocket_clock_gate")
class RocketImpl { // entering gated-clock domain
// performance counters
def pipelineIDToWB[T <: Data](x: T): T =
RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid)
val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
("exception", () => false.B),
("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
("system", () => id_ctrl.csr =/= CSR.N),
("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
("branch", () => id_ctrl.branch),
("jal", () => id_ctrl.jal),
("jalr", () => id_ctrl.jalr))
++ (if (!usingMulDiv) Seq() else Seq(
("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV),
("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV)))
++ (if (!usingFPU) Seq() else Seq(
("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
("long-latency interlock", () => id_sboard_hazard),
("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
("I$ blocked", () => icache_blocked),
("D$ blocked", () => id_ctrl.mem && dcache_blocked),
("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
("flush", () => wb_reg_flush_pipe),
("replay", () => replay_wb))
++ (if (!usingMulDiv) Seq() else Seq(
("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
++ (if (!usingFPU) Seq() else Seq(
("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.imem.perf.acquire),
("D$ miss", () => io.dmem.perf.acquire),
("D$ release", () => io.dmem.perf.release),
("ITLB miss", () => io.imem.perf.tlbMiss),
("DTLB miss", () => io.dmem.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
val decode_table = {
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++:
(if (xLen == 32) new I32Decode else new I64Decode) +:
(usingVM.option(new SVMDecode)) ++:
(usingSupervisor.option(new SDecode)) ++:
(usingHypervisor.option(new HypervisorDecode)) ++:
((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++:
(usingDebug.option(new DebugDecode)) ++:
(usingNMI.option(new NMIDecode)) ++:
(usingConditionalZero.option(new ConditionalZeroDecode)) ++:
Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++:
coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++:
rocketParams.haveCease.option(new CeaseDecode) ++:
usingVector.option(new VCFGDecode) ++:
(if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++:
(if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++:
coreParams.useZbs.option(new ZbsDecode) ++:
Seq(new IDecode)
} flatMap(_.table)
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)
val wb_ctrl = Reg(new IntCtrlSigs)
val ex_reg_xcpt_interrupt = Reg(Bool())
val ex_reg_valid = Reg(Bool())
val ex_reg_rvc = Reg(Bool())
val ex_reg_btb_resp = Reg(new BTBResp)
val ex_reg_xcpt = Reg(Bool())
val ex_reg_flush_pipe = Reg(Bool())
val ex_reg_load_use = Reg(Bool())
val ex_reg_cause = Reg(UInt())
val ex_reg_replay = Reg(Bool())
val ex_reg_pc = Reg(UInt())
val ex_reg_mem_size = Reg(UInt())
val ex_reg_hls = Reg(Bool())
val ex_reg_inst = Reg(Bits())
val ex_reg_raw_inst = Reg(UInt())
val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val ex_reg_set_vconfig = Reg(Bool())
val mem_reg_xcpt_interrupt = Reg(Bool())
val mem_reg_valid = Reg(Bool())
val mem_reg_rvc = Reg(Bool())
val mem_reg_btb_resp = Reg(new BTBResp)
val mem_reg_xcpt = Reg(Bool())
val mem_reg_replay = Reg(Bool())
val mem_reg_flush_pipe = Reg(Bool())
val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool())
val mem_reg_load = Reg(Bool())
val mem_reg_store = Reg(Bool())
val mem_reg_set_vconfig = Reg(Bool())
val mem_reg_sfence = Reg(Bool())
val mem_reg_pc = Reg(UInt())
val mem_reg_inst = Reg(Bits())
val mem_reg_mem_size = Reg(UInt())
val mem_reg_hls_or_dv = Reg(Bool())
val mem_reg_raw_inst = Reg(UInt())
val mem_reg_wdata = Reg(Bits())
val mem_reg_rs2 = Reg(Bits())
val mem_br_taken = Reg(Bool())
val take_pc_mem = Wire(Bool())
val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val wb_reg_valid = Reg(Bool())
val wb_reg_xcpt = Reg(Bool())
val wb_reg_replay = Reg(Bool())
val wb_reg_flush_pipe = Reg(Bool())
val wb_reg_cause = Reg(UInt())
val wb_reg_set_vconfig = Reg(Bool())
val wb_reg_sfence = Reg(Bool())
val wb_reg_pc = Reg(UInt())
val wb_reg_mem_size = Reg(UInt())
val wb_reg_hls_or_dv = Reg(Bool())
val wb_reg_hfence_v = Reg(Bool())
val wb_reg_hfence_g = Reg(Bool())
val wb_reg_inst = Reg(Bits())
val wb_reg_raw_inst = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_rs2 = Reg(Bits())
val take_pc_wb = Wire(Bool())
val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val take_pc_mem_wb = take_pc_wb || take_pc_mem
val take_pc = take_pc_mem_wb
// decode stage
val ibuf = Module(new IBuf)
val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
val id_inst = id_expanded_inst.map(_.bits)
ibuf.io.imem <> io.imem.resp
ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)
require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point")
require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor")
val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table)
val lgNXRegs = if (coreParams.useRVE) 4 else 5
val regAddrMask = (1 << lgNXRegs) - 1
def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0))
val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3)
val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2)
val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1)
val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd)
val id_load_use = Wire(Bool())
val id_reg_fence = RegInit(false.B)
val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
val rf = new RegFile(regAddrMask, xLen)
val id_rs = id_raddr.map(rf.read _)
val ctrl_killd = Wire(Bool())
val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt
val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined))
val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)
val id_system_insn = id_ctrl.csr === CSR.I
val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U
val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr))
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B
id_ctrl.vec := false.B
if (usingVector) {
val v_decode = rocketParams.vector.get.decoder(p)
v_decode.io.inst := id_inst(0)
v_decode.io.vconfig := csr.io.vector.get.vconfig
when (v_decode.io.legal) {
id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
id_ctrl.fp := v_decode.io.fp
id_ctrl.rocc := false.B
id_ctrl.branch := false.B
id_ctrl.jal := false.B
id_ctrl.jalr := false.B
id_ctrl.rxs2 := v_decode.io.read_rs2
id_ctrl.rxs1 := v_decode.io.read_rs1
id_ctrl.mem := false.B
id_ctrl.rfs1 := v_decode.io.read_frs1
id_ctrl.rfs2 := false.B
id_ctrl.rfs3 := false.B
id_ctrl.wfd := v_decode.io.write_frd
id_ctrl.mul := false.B
id_ctrl.div := false.B
id_ctrl.wxd := v_decode.io.write_rd
id_ctrl.csr := CSR.N
id_ctrl.fence_i := false.B
id_ctrl.fence := false.B
id_ctrl.amo := false.B
id_ctrl.dp := false.B
id_ctrl.vec := true.B
}
}
val id_illegal_insn = !id_ctrl.legal ||
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
(id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
id_raddr2_illegal && id_ctrl.rxs2 ||
id_raddr1_illegal && id_ctrl.rxs1 ||
id_waddr_illegal && id_ctrl.wxd ||
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
!ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal)
val id_virtual_insn = id_ctrl.legal &&
((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) ||
(!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal))
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
val id_amo_aq = id_inst(0)(26)
val id_amo_rl = id_inst(0)(25)
val id_fence_pred = id_inst(0)(27,24)
val id_fence_succ = id_inst(0)(23,20)
val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq
val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
when (!id_mem_busy) { id_reg_fence := false.B }
val id_rocc_busy = usingRoCC.B &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren
val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B)
val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||
id_vec_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status
bpu.io.bp := csr.io.bp
bpu.io.pc := ibuf.io.pc
bpu.io.ea := mem_reg_wdata
bpu.io.mcontext := csr.io.mcontext
bpu.io.scontext := csr.io.scontext
val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
val (id_xcpt, id_cause) = checkExceptions(List(
(csr.io.interrupt, csr.io.interrupt_cause),
(bpu.io.debug_if, CSR.debugTriggerCause.U),
(bpu.io.xcpt_if, Causes.breakpoint.U),
(id_xcpt0.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt0.ae.inst, Causes.fetch_access.U),
(id_xcpt1.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt1.ae.inst, Causes.fetch_access.U),
(id_virtual_insn, Causes.virtual_instruction.U),
(id_illegal_insn, Causes.illegal_instruction.U)))
val idCoverCauses = List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.fetch_access, "FETCH_ACCESS"),
(Causes.illegal_instruction, "ILLEGAL_INSTRUCTION")
) ++ (if (usingVM) List(
(Causes.fetch_page_fault, "FETCH_PAGE_FAULT")
) else Nil)
coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
val dcache_bypass_data =
if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
else wb_reg_wdata
// detect bypass opportunities
val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U
val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U
val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U
val bypass_sources = IndexedSeq(
(true.B, 0.U, 0.U), // treat reading x0 as a bypass
(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W)))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13)
val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq(
A1_RS1 -> ex_rs(0).asSInt,
A1_PC -> ex_reg_pc.asSInt,
A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S)
))
val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt
val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq(
A2_RS2 -> ex_rs(1).asSInt,
A2_IMM -> ex_imm,
A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S),
) ++ (if (coreParams.useZbs) Seq(
A2_RS2OH -> ex_op2_oh,
A2_IMMOH -> ex_op2_oh,
) else Nil))
val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(
ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),
!ex_reg_inst(31) -> ex_reg_inst(30,20))))
val ex_avl = Mux(ex_ctrl.rxs1,
Mux(ex_reg_inst(19,15) === 0.U,
Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
ex_rs(0)
),
ex_reg_inst(19,15))
val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B)
val ex_new_vconfig = Wire(new VConfig)
ex_new_vconfig.vtype := ex_new_vtype
ex_new_vconfig.vl := ex_new_vl
(Some(ex_new_vl), Some(ex_new_vconfig))
} else { (None, None) }
val alu = Module(new ALU)
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.asUInt
alu.io.in1 := ex_op1.asUInt
// multiplier and divider
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
div.io.req.valid := ex_reg_valid && ex_ctrl.div
div.io.req.bits.dw := ex_ctrl.alu_dw
div.io.req.bits.fn := ex_ctrl.alu_fn
div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := ex_waddr
val mul = pipelinedMul.option {
val m = Module(new PipelinedMultiplier(xLen, 2))
m.io.req.valid := ex_reg_valid && ex_ctrl.mul
m.io.req.bits := div.io.req.bits
m
}
ex_reg_valid := !ctrl_killd
ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
ex_reg_xcpt := !ctrl_killd && id_xcpt
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
when (!ctrl_killd) {
ex_ctrl := id_ctrl
ex_reg_rvc := ibuf.io.inst(0).bits.rvc
ex_ctrl.csr := id_csr
when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B }
when (id_fence_next) { id_reg_fence := true.B }
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := FN_ADD
ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
ex_ctrl.sel_alu2 := A2_ZERO
when (id_xcpt1.asUInt.orR) { // badaddr := PC+2
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_SIZE
ex_reg_rvc := true.B
}
when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_ZERO
}
}
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_load_use := id_load_use
ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX)
ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))
when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) {
ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U)
}
when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) {
ex_ctrl.mem_cmd := M_HFENCEV
}
if (tile.dcache.flushOnFenceI) {
when (id_ctrl.fence_i) {
ex_reg_mem_size := 0.U
}
}
for (i <- 0 until id_raddr.size) {
val do_bypass = id_bypass_src(i).reduce(_||_)
val bypass_src = PriorityEncoder(id_bypass_src(i))
ex_reg_rs_bypass(i) := do_bypass
ex_reg_rs_lsb(i) := bypass_src
when (id_ren(i) && !do_bypass) {
ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)
}
}
when (id_illegal_insn || id_virtual_insn) {
val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))
ex_reg_rs_bypass(0) := false.B
ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
}
}
when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
ex_reg_cause := id_cause
ex_reg_inst := id_inst(0)
ex_reg_raw_inst := id_raw_inst(0)
ex_reg_pc := ibuf.io.pc
ex_reg_btb_resp := ibuf.io.btb_resp
ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) }
ex_reg_set_vconfig := id_set_vconfig && !id_xcpt
}
// replay inst in ex stage?
val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt
val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid
val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||
ex_ctrl.div && !div.io.req.ready ||
ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B)
val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use
val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use))
val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid
// detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U
val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG)
val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause)))
val exCoverCauses = idCoverCauses
coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses)
// memory stage
val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
val mem_br_target = mem_reg_pc.asSInt +
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
Mux(mem_reg_rvc, 2.S, 4.S)))
val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt
val mem_wrong_npc =
Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,
Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B))
val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken)
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence)
mem_reg_valid := !ctrl_killx
mem_reg_replay := !take_pc_mem_wb && replay_ex
mem_reg_xcpt := !ctrl_killx && ex_xcpt
mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt
// on pipeline flushes, cause mem_npc to hold the sequential npc, which
// will drive the W-stage npc mux
when (mem_reg_valid && mem_reg_flush_pipe) {
mem_reg_sfence := false.B
}.elsewhen (ex_pc_valid) {
mem_ctrl := ex_ctrl
mem_reg_rvc := ex_reg_rvc
mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
mem_reg_sfence := ex_sfence
mem_reg_btb_resp := ex_reg_btb_resp
mem_reg_flush_pipe := ex_reg_flush_pipe
mem_reg_slow_bypass := ex_slow_bypass
mem_reg_wphit := ex_reg_wphit
mem_reg_set_vconfig := ex_reg_set_vconfig
mem_reg_cause := ex_cause
mem_reg_inst := ex_reg_inst
mem_reg_raw_inst := ex_reg_raw_inst
mem_reg_mem_size := ex_reg_mem_size
mem_reg_hls_or_dv := io.dmem.req.bits.dv
mem_reg_pc := ex_reg_pc
// IDecode ensured they are 1H
mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out)
mem_br_taken := alu.io.cmp_out
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size)
mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data
}
if (usingVector) { when (ex_reg_set_vconfig) {
mem_reg_rs2 := ex_new_vconfig.get.asUInt
} }
when (ex_ctrl.jalr && csr.io.status.debug) {
// flush I$ on D-mode JALR to effect uncached fetch without D$ flush
mem_ctrl.fence_i := true.B
mem_reg_flush_pipe := true.B
}
}
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
(mem_debug_breakpoint, CSR.debugTriggerCause.U),
(mem_breakpoint, Causes.breakpoint.U)))
val (mem_xcpt, mem_cause) = checkExceptions(List(
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
(mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U),
(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
val memCoverCauses = (exCoverCauses ++ List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.misaligned_fetch, "MISALIGNED_FETCH")
)).distinct
coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses)
val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B)
val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B)
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
div.io.kill := killm_common && RegNext(div.io.req.fire)
val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem
// writeback stage
wb_reg_valid := !ctrl_killm
wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B)
wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe
when (mem_pc_valid) {
wb_ctrl := mem_ctrl
wb_reg_sfence := mem_reg_sfence
wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) {
wb_reg_rs2 := mem_reg_rs2
}
wb_reg_cause := mem_cause
wb_reg_inst := mem_reg_inst
wb_reg_raw_inst := mem_reg_raw_inst
wb_reg_mem_size := mem_reg_mem_size
wb_reg_hls_or_dv := mem_reg_hls_or_dv
wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV
wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG
wb_reg_pc := mem_reg_pc
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }
wb_reg_set_vconfig := mem_reg_set_vconfig
}
val (wb_xcpt, wb_cause) = checkExceptions(List(
(wb_reg_xcpt, wb_reg_cause),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U)
))
val wbCoverCauses = List(
(Causes.misaligned_store, "MISALIGNED_STORE"),
(Causes.misaligned_load, "MISALIGNED_LOAD"),
(Causes.store_access, "STORE_ACCESS"),
(Causes.load_access, "LOAD_ACCESS")
) ++ (if(usingVM) List(
(Causes.store_page_fault, "STORE_PAGE_FAULT"),
(Causes.load_page_fault, "LOAD_PAGE_FAULT")
) else Nil) ++ (if (usingHypervisor) List(
(Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"),
(Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"),
) else Nil)
coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses)
val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt
val wb_wxd = wb_reg_valid && wb_ctrl.wxd
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec
val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall
val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B)
val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec
take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool
val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
class LLWB extends Bundle {
val data = UInt(xLen.W)
val tag = UInt(5.W)
}
val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec
ll_arb.io.in.foreach(_.valid := false.B)
ll_arb.io.in.foreach(_.bits := DontCare)
val ll_wdata = WireInit(ll_arb.io.out.bits.data)
val ll_waddr = WireInit(ll_arb.io.out.bits.tag)
val ll_wen = WireInit(ll_arb.io.out.fire)
ll_arb.io.out.ready := !wb_wxd
div.io.resp.ready := ll_arb.io.in(0).ready
ll_arb.io.in(0).valid := div.io.resp.valid
ll_arb.io.in(0).bits.data := div.io.resp.bits.data
ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag
if (usingRoCC) {
io.rocc.resp.ready := ll_arb.io.in(1).ready
ll_arb.io.in(1).valid := io.rocc.resp.valid
ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data
ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd
} else {
// tie off RoCC
io.rocc.resp.ready := false.B
io.rocc.mem.req.ready := false.B
}
io.vector.map { v =>
v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready)
ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp
ll_arb.io.in(2).bits.data := v.resp.bits.data
ll_arb.io.in(2).bits.tag := v.resp.bits.rd
}
// Dont care mem since not all RoCC need accessing memory
io.rocc.mem := DontCare
when (dmem_resp_replay && dmem_resp_xpu) {
ll_arb.io.out.ready := false.B
ll_waddr := dmem_resp_waddr
ll_wen := true.B
}
val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt
val wb_wen = wb_valid && wb_ctrl.wxd
val rf_wen = wb_wen || ll_wen
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
Mux(ll_wen, ll_wdata,
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata),
wb_reg_wdata))))
when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
// hook up control/status regfile
csr.io.ungated_clock := clock
csr.io.decode(0).inst := id_inst(0)
csr.io.exception := wb_xcpt
csr.io.cause := wb_cause
csr.io.retire := wb_valid
csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst)
csr.io.interrupts := io.interrupts
csr.io.hartid := io.hartid
io.fpu.fcsr_rm := csr.io.fcsr_rm
val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W))
val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B)
csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid
csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid))
io.fpu.time := csr.io.time(31,0)
io.fpu.hartid := io.hartid
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
val tval_dmem_addr = !wb_reg_xcpt
val tval_any_addr = tval_dmem_addr ||
wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U)
val tval_inst = wb_reg_cause === Causes.illegal_instruction.U
val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)
csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
val (htval, mhtinst_read_pseudo) = {
val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U
val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)
assert(!htval_valid_imem || io.imem.gpa.valid)
val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR
val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)
val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
// read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation
val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)
(htval, mhtinst_read_pseudo)
}
csr.io.vector.foreach { v =>
v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid
v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig)
v.set_vs_dirty := wb_valid && wb_ctrl.vec
v.set_vstart.valid := wb_valid && wb_reg_set_vconfig
v.set_vstart.bits := 0.U
}
io.vector.foreach { v =>
when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) {
csr.io.pc := v.wb.pc
csr.io.retire := v.wb.retire
csr.io.inst(0) := v.wb.inst
when (v.wb.xcpt && !wb_reg_xcpt) {
wb_xcpt := true.B
wb_cause := v.wb.cause
csr.io.tval := v.wb.tval
}
}
v.wb.store_pending := io.dmem.store_pending
v.wb.vxrm := csr.io.vector.get.vxrm
v.wb.frm := csr.io.fcsr_rm
csr.io.vector.get.set_vxsat := v.set_vxsat
when (v.set_vconfig.valid) {
csr.io.vector.get.set_vconfig.valid := true.B
csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits
}
when (v.set_vstart.valid) {
csr.io.vector.get.set_vstart.valid := true.B
csr.io.vector.get.set_vstart.bits := v.set_vstart.bits
}
}
csr.io.htval := htval
csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo
io.ptw.ptbr := csr.io.ptbr
io.ptw.hgatp := csr.io.hgatp
io.ptw.vsatp := csr.io.vsatp
(io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
io.ptw.status := csr.io.status
io.ptw.hstatus := csr.io.hstatus
io.ptw.gstatus := csr.io.gstatus
io.ptw.pmp := csr.io.pmp
csr.io.rw.addr := wb_reg_inst(31,20)
csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)
csr.io.rw.wdata := wb_reg_wdata
io.rocc.csrs <> csr.io.roccCSRs
io.trace.time := csr.io.time
io.trace.insns := csr.io.trace
if (rocketParams.debugROB.isDefined) {
val sz = rocketParams.debugROB.get.size
if (sz < 1) { // use unsynthesizable ROB
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception)
val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)
val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
io.vector.foreach { v => when (v.wb.retire) {
should_wb := v.wb.rob_should_wb
has_wb := false.B
wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))
}}
DebugROB.pushTrace(clock, reset,
io.hartid, csr_trace_with_wdata,
should_wb, has_wb, wb_addr)
io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
} else { // synthesizable ROB (no FPRs)
require(!usingVector, "Synthesizable ROB does not support vector implementations")
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val debug_rob = Module(new HardDebugROB(sz, 32))
debug_rob.io.i_insn := csr_trace_with_wdata
debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
!csr.io.trace(0).exception
debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
debug_rob.io.wb_val := ll_wen
debug_rob.io.wb_tag := rf_waddr
debug_rob.io.wb_data := rf_wdata
io.trace.insns(0) := debug_rob.io.o_insn
}
} else {
io.trace.insns := csr.io.trace
}
for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {
iobpw.valid(0) := wphit
iobpw.action := bp.control.action
// tie off bpwatch valids
iobpw.rvalid.foreach(_ := false.B)
iobpw.wvalid.foreach(_ := false.B)
iobpw.ivalid.foreach(_ := false.B)
}
val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1),
(id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2),
(id_ctrl.wxd && id_waddr =/= 0.U, id_waddr))
val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),
(io.fpu.dec.ren2, id_raddr2),
(io.fpu.dec.ren3, id_raddr3),
(io.fpu.dec.wen, id_waddr))
val sboard = new Scoreboard(32, true)
sboard.clear(ll_wen, ll_waddr)
def id_sboard_clear_bypass(r: UInt) = {
// ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check
if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r
else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r
}
val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
val mem_mem_cmd_bh =
if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass
else true.B
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem
val id_vconfig_hazard = id_ctrl.vec && (
(ex_reg_valid && ex_reg_set_vconfig) ||
(mem_reg_valid && mem_reg_set_vconfig) ||
(wb_reg_valid && wb_reg_set_vconfig))
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)
val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
val id_stall_fpu = if (usingFPU) {
val fp_sboard = new Scoreboard(32)
fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B)
fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
checkHazards(fp_hazard_targets, fp_sboard.read _)
} else false.B
val dcache_blocked = {
// speculate that a blocked D$ will unblock the cycle after a Grant
val blocked = Reg(Bool())
blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack)
blocked && !io.dmem.perf.grant
}
val rocc_blocked = Reg(Bool())
rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked)
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_vconfig_hazard ||
csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) ||
id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy ||
id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay
!clock_en ||
id_do_fence ||
csr.io.csr_stall ||
id_reg_pause ||
io.traceStall
ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
io.imem.req.valid := take_pc
io.imem.req.bits.speculative := !take_pc_wb
io.imem.req.bits.pc :=
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)) // flush or branch misprediction
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
io.imem.might_request := {
imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B)
imem_might_request_reg
}
io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common)
io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
io.imem.sfence.bits.rs1 := wb_reg_mem_size(0)
io.imem.sfence.bits.rs2 := wb_reg_mem_size(1)
io.imem.sfence.bits.addr := wb_reg_wdata
io.imem.sfence.bits.asid := wb_reg_rs2
io.imem.sfence.bits.hv := wb_reg_hfence_v
io.imem.sfence.bits.hg := wb_reg_hfence_g
io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)
io.imem.btb_update.bits.isValid := mem_cfi
io.imem.btb_update.bits.cfiType :=
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret,
Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump,
CFIType.branch)))
io.imem.btb_update.bits.target := io.imem.req.bits.pc
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc)
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U)
io.imem.btb_update.bits.prediction := mem_reg_btb_resp
io.imem.btb_update.bits.taken := DontCare
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
io.imem.bht_update.bits.taken := mem_br_taken
io.imem.bht_update.bits.mispredict := mem_wrong_npc
io.imem.bht_update.bits.branch := mem_ctrl.branch
io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht
// Connect RAS in Frontend
io.imem.ras_update := DontCare
io.fpu.valid := !ctrl_killd && id_ctrl.fp
io.fpu.killx := ctrl_killx
io.fpu.killm := killm_common
io.fpu.inst := id_inst(0)
io.fpu.fromint_data := ex_rs(0)
io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data)
io.fpu.ll_resp_type := io.dmem.resp.bits.size
io.fpu.ll_resp_tag := dmem_resp_waddr
io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate
io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U)
io.vector.map { v =>
when (!(dmem_resp_valid && dmem_resp_fpu)) {
io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp
io.fpu.ll_resp_data := v.resp.bits.data
io.fpu.ll_resp_type := v.resp.bits.size
io.fpu.ll_resp_tag := v.resp.bits.rd
}
}
io.vector.foreach { v =>
v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx
v.ex.inst := ex_reg_inst
v.ex.vconfig := csr.io.vector.get.vconfig
v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart)
v.ex.rs1 := ex_rs(0)
v.ex.rs2 := ex_rs(1)
v.ex.pc := ex_reg_pc
v.mem.frs1 := io.fpu.store_data
v.killm := killm_common
v.status := csr.io.status
}
io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem
val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)
require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth)
io.dmem.req.bits.tag := ex_dcache_tag
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.size := ex_reg_mem_size
io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))
io.dmem.req.bits.phys := false.B
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)
io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv
io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)
io.dmem.req.bits.no_alloc := DontCare
io.dmem.req.bits.no_xcpt := DontCare
io.dmem.req.bits.data := DontCare
io.dmem.req.bits.mask := DontCare
io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2))
io.dmem.s1_data.mask := DontCare
io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem
io.dmem.s2_kill := false.B
// don't let D$ go to sleep if we're probably going to use it soon
io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
io.rocc.cmd.bits.status := csr.io.status
io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction())
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false.B }
io.cease := csr.io.status.cease && !clock_en_reg
io.wfi := csr.io.status.wfi
if (rocketParams.clockGate) {
long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause
clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid)
clock_en_reg :=
ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight
io.ptw.customCSRs.disableCoreClockGate || // chicken bit
!div.io.req.ready || // mul/div in flight
usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight
io.dmem.replay_next || // long-latency load replaying
(!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending
assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en)
}
// evaluate performance counters
val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
coreMonitorBundle.hartid := io.hartid
coreMonitorBundle.timer := csr.io.time(31,0)
coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen)
coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard
coreMonitorBundle.wrenf := false.B
coreMonitorBundle.wrdst := wb_waddr
coreMonitorBundle.wrdata := rf_wdata
coreMonitorBundle.rd0src := wb_reg_inst(19,15)
coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0)))
coreMonitorBundle.rd1src := wb_reg_inst(24,20)
coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1)))
coreMonitorBundle.inst := csr.io.trace(0).insn
coreMonitorBundle.excpt := csr.io.trace(0).exception
coreMonitorBundle.priv_mode := csr.io.trace(0).priv
if (enableCommitLog) {
val t = csr.io.trace(0)
val rd = wb_waddr
val wfd = wb_ctrl.wfd
val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard
when (t.valid && !t.exception) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U)
}
.elsewhen (wxd && rd =/= 0.U && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= 0.U && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
when (ll_wen && rf_waddr =/= 0.U) {
printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
}
}
else {
when (csr.io.trace(0).valid) {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
coreMonitorBundle.pc,
Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),
Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),
coreMonitorBundle.wrenx,
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),
coreMonitorBundle.inst, coreMonitorBundle.inst)
}
}
// CoreMonitorBundle for late latency writes
val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen))
xrfWriteBundle.clock := clock
xrfWriteBundle.reset := reset
xrfWriteBundle.hartid := io.hartid
xrfWriteBundle.timer := csr.io.time(31,0)
xrfWriteBundle.valid := false.B
xrfWriteBundle.pc := 0.U
xrfWriteBundle.wrdst := rf_waddr
xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr))
xrfWriteBundle.wrenf := false.B
xrfWriteBundle.wrdata := rf_wdata
xrfWriteBundle.rd0src := 0.U
xrfWriteBundle.rd0val := 0.U
xrfWriteBundle.rd1src := 0.U
xrfWriteBundle.rd1val := 0.U
xrfWriteBundle.inst := 0.U
xrfWriteBundle.excpt := false.B
xrfWriteBundle.priv_mode := csr.io.trace(0).priv
if (rocketParams.haveSimTimeout) PlusArg.timeout(
name = "max_core_cycles",
docstring = "Kill the emulation after INT rdtime cycles. Off if 0."
)(csr.io.time)
} // leaving gated-clock domain
val rocketImpl = withClock (gated_clock) { new RocketImpl }
def checkExceptions(x: Seq[(Bool, UInt)]) =
(WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x)))
def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = {
for ((coverCause, label) <- coverCausesLabels) {
property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}")
}
}
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val b = vaddrBitsExtended-1
val a = (a0 >> b).asSInt
val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))
Cat(msb, ea(b-1, 0))
}
class Scoreboard(n: Int, zero: Boolean = false)
{
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
def read(addr: UInt): Bool = r(addr)
def readBypassed(addr: UInt): Bool = _next(addr)
private val _r = RegInit(0.U(n.W))
private val r = if (zero) (_r >> 1 << 1) else _r
private var _next = r
private var ens = false.B
private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U)
private def update(en: Bool, update: UInt) = {
_next = update
ens = ens || en
when (ens) { _r := _next }
}
}
}
class RegFile(n: Int, w: Int, zero: Boolean = false) {
val rf = Mem(n, UInt(w.W))
private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
private val reads = ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> Wire(UInt())
reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr))
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr =/= 0.U) {
access(addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
object ImmGen {
def apply(sel: UInt, inst: UInt) = {
val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)
val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)
val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt)
val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,
Mux(sel === IMM_UJ, inst(20).asSInt,
Mux(sel === IMM_SB, inst(7).asSInt, sign)))
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))
val b4_1 = Mux(sel === IMM_U, 0.U,
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), 0.U)))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File RVC.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class ExpandedInstruction extends Bundle {
val bits = UInt(32.W)
val rd = UInt(5.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rs3 = UInt(5.W)
}
class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
val res = Wire(new ExpandedInstruction)
res.bits := bits
res.rd := rd
res.rs1 := rs1
res.rs2 := rs2
res.rs3 := rs3
res
}
def rs1p = Cat(1.U(2.W), x(9,7))
def rs2p = Cat(1.U(2.W), x(4,2))
def rs2 = x(6,2)
def rd = x(11,7)
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
def addiImm = Cat(Fill(7, x(12)), x(6,2))
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
def shamt = Cat(x(12), x(6,2))
def x0 = 0.U(5.W)
def ra = 1.U(5.W)
def sp = 2.U(5.W)
def q0 = {
def addi4spn = {
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
}
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
def flw = {
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
else ld
}
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
def fsw = {
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
else sd
}
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
}
def q1 = {
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
def addiw = {
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def jal = {
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
else addiw
}
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
def addi16sp = {
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def lui = {
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
Mux(rd === x0 || rd === sp, addi16sp, me)
}
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
def arith = {
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
def srai = srli | (1 << 30).U
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
def rtype = {
val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
}
inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
}
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
}
def q2 = {
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
def flwsp = {
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
else ldsp
}
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
def fswsp = {
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
else sdsp
}
def jalr = {
val mv = {
if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0)
else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
}
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
Mux(x(12), jalr_add, jr_mv)
}
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
}
def q3 = Seq.fill(8)(passthrough)
def passthrough = inst(x)
def decode = {
val s = q0 ++ q1 ++ q2 ++ q3
s(Cat(x(1,0), x(15,13)))
}
def q0_ill = {
def allz = !(x(12, 2).orR)
def fld = if (fLen >= 64) false.B else true.B
def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
def fsd = if (fLen >= 64) false.B else true.B
def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
}
def q1_ill = {
def rd0 = if (xLen == 32) false.B else rd === 0.U
def immz = !(x(12) | x(6, 2).orR)
def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U)
Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B)
}
def q2_ill = {
def fldsp = if (fLen >= 64) false.B else true.B
def rd0 = rd === 0.U
def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B
def jr_res = !(x(12 ,2).orR)
def fsdsp = if (fLen >= 64) false.B else true.B
def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B
Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32)
}
def q3_ill = Seq.fill(8)(false.B)
def ill = {
val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill
s(Cat(x(1,0), x(15,13)))
}
}
class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(new ExpandedInstruction)
val rvc = Output(Bool())
val ill = Output(Bool())
})
if (usingCompressed) {
io.rvc := io.in(1,0) =/= 3.U
val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)
io.out := decoder.decode
io.ill := decoder.ill
} else {
io.rvc := false.B
io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough
io.ill := false.B // only used for RVC
}
}
| module Frontend( // @[Frontend.scala:82:7]
input clock, // @[Frontend.scala:82:7]
input reset, // @[Frontend.scala:82:7]
input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_cpu_might_request, // @[Frontend.scala:85:14]
input io_cpu_req_valid, // @[Frontend.scala:85:14]
input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14]
input io_cpu_sfence_valid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14]
input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_asid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hv, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hg, // @[Frontend.scala:85:14]
input io_cpu_resp_ready, // @[Frontend.scala:85:14]
output io_cpu_resp_valid, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_cfiType, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14]
output [38:0] io_cpu_resp_bits_btb_target, // @[Frontend.scala:85:14]
output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14]
output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bht_value, // @[Frontend.scala:85:14]
output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14]
output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14]
output io_cpu_gpa_valid, // @[Frontend.scala:85:14]
output [39:0] io_cpu_gpa_bits, // @[Frontend.scala:85:14]
output io_cpu_gpa_is_pte, // @[Frontend.scala:85:14]
input io_cpu_btb_update_valid, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:85:14]
input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14]
input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14]
input io_cpu_bht_update_valid, // @[Frontend.scala:85:14]
input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14]
input io_cpu_flush_icache, // @[Frontend.scala:85:14]
output [39:0] io_cpu_npc, // @[Frontend.scala:85:14]
output io_cpu_perf_acquire, // @[Frontend.scala:85:14]
output io_cpu_perf_tlbMiss, // @[Frontend.scala:85:14]
input io_cpu_progress, // @[Frontend.scala:85:14]
input io_ptw_req_ready, // @[Frontend.scala:85:14]
output io_ptw_req_valid, // @[Frontend.scala:85:14]
output io_ptw_req_bits_valid, // @[Frontend.scala:85:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14]
output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14]
input io_ptw_resp_valid, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:85:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:85:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:85:14]
input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14]
input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:85:14]
input io_ptw_status_debug, // @[Frontend.scala:85:14]
input io_ptw_status_cease, // @[Frontend.scala:85:14]
input io_ptw_status_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_status_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_dprv, // @[Frontend.scala:85:14]
input io_ptw_status_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14]
input io_ptw_status_v, // @[Frontend.scala:85:14]
input io_ptw_status_mpv, // @[Frontend.scala:85:14]
input io_ptw_status_gva, // @[Frontend.scala:85:14]
input io_ptw_status_tsr, // @[Frontend.scala:85:14]
input io_ptw_status_tw, // @[Frontend.scala:85:14]
input io_ptw_status_tvm, // @[Frontend.scala:85:14]
input io_ptw_status_mxr, // @[Frontend.scala:85:14]
input io_ptw_status_sum, // @[Frontend.scala:85:14]
input io_ptw_status_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_mpp, // @[Frontend.scala:85:14]
input io_ptw_status_spp, // @[Frontend.scala:85:14]
input io_ptw_status_mpie, // @[Frontend.scala:85:14]
input io_ptw_status_spie, // @[Frontend.scala:85:14]
input io_ptw_status_mie, // @[Frontend.scala:85:14]
input io_ptw_status_sie, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spvp, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spv, // @[Frontend.scala:85:14]
input io_ptw_hstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_debug, // @[Frontend.scala:85:14]
input io_ptw_gstatus_cease, // @[Frontend.scala:85:14]
input io_ptw_gstatus_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_v, // @[Frontend.scala:85:14]
input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mbe, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sbe, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:85:14]
input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tsr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tw, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tvm, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mxr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sum, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spp, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_ube, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_upie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_hie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_uie, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[Frontend.scala:85:14]
);
wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40]
wire _btb_io_resp_valid; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_mask; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21]
wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21]
wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21]
wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21]
wire _tlb_io_req_ready; // @[Frontend.scala:105:19]
wire _tlb_io_resp_miss; // @[Frontend.scala:105:19]
wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19]
wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ma_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19]
wire _tlb_io_resp_prefetchable; // @[Frontend.scala:105:19]
wire _fq_io_enq_ready; // @[Frontend.scala:91:64]
wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64]
wire _icache_io_resp_valid; // @[Frontend.scala:70:26]
wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26]
wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26]
wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:82:7]
wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:82:7]
wire [63:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:82:7]
wire io_cpu_might_request_0 = io_cpu_might_request; // @[Frontend.scala:82:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_req_bits_speculative_0 = io_cpu_req_bits_speculative; // @[Frontend.scala:82:7]
wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:82:7]
wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:82:7]
wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:82:7]
wire io_cpu_progress_0 = io_cpu_progress; // @[Frontend.scala:82:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:82:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:82:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:82:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:82:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:82:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:82:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:82:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:82:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:82:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:82:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:82:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:82:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:82:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:82:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:82:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:82:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:82:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:82:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:82:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:82:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:82:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_ready = 1'h1; // @[Frontend.scala:82:7]
wire io_cpu_clock_enabled = 1'h1; // @[Frontend.scala:82:7]
wire io_ptw_status_sd = 1'h1; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd = 1'h1; // @[Frontend.scala:82:7]
wire clock_en = 1'h1; // @[Frontend.scala:94:31]
wire _taken_rviImm_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_3 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_6 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_7 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_17 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_12 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_13 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_T_6 = 1'h1; // @[Frontend.scala:270:13]
wire _taken_btb_io_ras_update_bits_cfiType_T_3 = 1'h1; // @[Frontend.scala:276:85]
wire _taken_rviImm_b19_12_T_10 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_25 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_15 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_16 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_17 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_39 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_32 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_33 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_btb_io_ras_update_bits_cfiType_T_11 = 1'h1; // @[Frontend.scala:276:85]
wire _clock_en_reg_T = 1'h1; // @[Frontend.scala:376:19]
wire _clock_en_reg_T_1 = 1'h1; // @[Frontend.scala:376:45]
wire _clock_en_reg_T_2 = 1'h1; // @[Frontend.scala:377:26]
wire _clock_en_reg_T_3 = 1'h1; // @[Frontend.scala:378:34]
wire _clock_en_reg_T_4 = 1'h1; // @[Frontend.scala:379:14]
wire _clock_en_reg_T_6 = 1'h1; // @[Frontend.scala:379:26]
wire _clock_en_reg_T_9 = 1'h1; // @[Frontend.scala:380:23]
wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_ras_update_valid = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[Frontend.scala:82:7]
wire taken_rvcJAL = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_14 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_1 = 1'h0; // @[RocketCore.scala:1351:17]
wire taken_rvcJAL_1 = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T_6 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_6 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_11 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_12 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_22 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_23 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_24 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_28 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T_8 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_9 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_10 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_20 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_21 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_22 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_23 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_25 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_16 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_18 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_20 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_22 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_23 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_2 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_9 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_9 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_33 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_34 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_35 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_36 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_12 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_13 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_14 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_30 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_31 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_35 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_24 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_26 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_28 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_30 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_31 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_3 = 1'h0; // @[RocketCore.scala:1351:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_xs = 2'h3; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_ras_update_bits_cfiType = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:82:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:82:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:82:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:82:7]
wire [7:0] auto_icache_master_out_a_bits_mask = 8'hFF; // @[Frontend.scala:82:7]
wire [63:0] auto_icache_master_out_a_bits_data = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:82:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] _s2_pc_T_2 = 32'h10000; // @[Frontend.scala:384:27]
wire [38:0] io_cpu_ras_update_bits_returnAddr = 39'h0; // @[Frontend.scala:82:7]
wire [31:0] _s2_pc_T = 32'hFFFEFFFF; // @[Frontend.scala:384:29]
wire [31:0] _s2_pc_T_1 = 32'hFFFEFFFF; // @[Frontend.scala:384:33]
wire [39:0] _io_cpu_npc_T_3; // @[Frontend.scala:384:27]
wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_resp_bits_btb_bht_history_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bht_value_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_cfiType_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_taken_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bridx_0; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_resp_bits_btb_target_0; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_resp_bits_btb_entry_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_pf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_gf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_ae_inst_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_resp_bits_pc_0; // @[Frontend.scala:82:7]
wire [31:0] io_cpu_resp_bits_data_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_replay_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_valid_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_valid_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_gpa_bits_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_acquire_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_tlbMiss_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_is_pte_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_npc_0; // @[Frontend.scala:82:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_valid_0; // @[Frontend.scala:82:7]
wire io_ptw_req_valid_0; // @[Frontend.scala:82:7]
wire io_errors_bus_valid; // @[Frontend.scala:82:7]
wire [31:0] io_errors_bus_bits; // @[Frontend.scala:82:7]
reg s1_valid; // @[Frontend.scala:107:21]
reg s2_valid; // @[Frontend.scala:108:25]
wire _s0_fq_has_space_T = _fq_io_mask[2]; // @[Frontend.scala:91:64, :110:16]
wire _s0_fq_has_space_T_1 = ~_s0_fq_has_space_T; // @[Frontend.scala:110:{5,16}]
wire _s0_fq_has_space_T_2 = _fq_io_mask[3]; // @[Frontend.scala:91:64, :111:17]
wire _s0_fq_has_space_T_3 = ~_s0_fq_has_space_T_2; // @[Frontend.scala:111:{6,17}]
wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala:107:21, :111:45]
wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala:108:25, :111:58]
wire _s0_fq_has_space_T_6 = _s0_fq_has_space_T_4 | _s0_fq_has_space_T_5; // @[Frontend.scala:111:{45,55,58}]
wire _s0_fq_has_space_T_7 = _s0_fq_has_space_T_3 & _s0_fq_has_space_T_6; // @[Frontend.scala:111:{6,41,55}]
wire _s0_fq_has_space_T_8 = _s0_fq_has_space_T_1 | _s0_fq_has_space_T_7; // @[Frontend.scala:110:{5,40}, :111:41]
wire _s0_fq_has_space_T_9 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17]
wire _clock_en_reg_T_7 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17, :381:16]
wire _s0_fq_has_space_T_10 = ~_s0_fq_has_space_T_9; // @[Frontend.scala:112:{6,17}]
wire _s0_fq_has_space_T_11 = ~s1_valid; // @[Frontend.scala:107:21, :111:45, :112:45]
wire _s0_fq_has_space_T_12 = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :112:58]
wire _s0_fq_has_space_T_13 = _s0_fq_has_space_T_11 & _s0_fq_has_space_T_12; // @[Frontend.scala:112:{45,55,58}]
wire _s0_fq_has_space_T_14 = _s0_fq_has_space_T_10 & _s0_fq_has_space_T_13; // @[Frontend.scala:112:{6,41,55}]
wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala:110:40, :111:70, :112:41]
wire s0_valid = io_cpu_req_valid_0 | s0_fq_has_space; // @[Frontend.scala:82:7, :111:70, :113:35]
reg [39:0] s1_pc; // @[Frontend.scala:115:18]
reg s1_speculative; // @[Frontend.scala:116:27]
reg [39:0] s2_pc; // @[Frontend.scala:117:22]
reg s2_btb_resp_valid; // @[Frontend.scala:118:44]
reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29]
reg [1:0] s2_btb_resp_bits_mask; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29]
wire _taken_T_30 = s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:119:29]
reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29]
reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_23 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T_1 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_52 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40]
reg s2_tlb_resp_miss; // @[Frontend.scala:121:24]
reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:121:24]
reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ma_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24]
reg s2_tlb_resp_prefetchable; // @[Frontend.scala:121:24]
wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37]
wire s2_xcpt = _s2_xcpt_T; // @[Frontend.scala:122:{37,60}]
reg s2_speculative; // @[Frontend.scala:123:31]
reg s2_partial_insn_valid; // @[Frontend.scala:124:38]
reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28]
reg wrong_path; // @[Frontend.scala:126:27]
wire [39:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala:115:18, :128:22]
wire [39:0] _s1_base_pc_T_1 = {_s1_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:128:{22,29}]
wire [39:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala:128:{20,29}]
wire [40:0] _ntpc_T = {1'h0, s1_base_pc} + 41'h4; // @[Frontend.scala:128:20, :129:25]
wire [39:0] ntpc = _ntpc_T[39:0]; // @[Frontend.scala:129:25]
wire [39:0] predicted_npc; // @[Frontend.scala:130:34]
wire predicted_taken; // @[Frontend.scala:131:36]
wire _s2_replay_T_5; // @[Frontend.scala:134:46]
wire s2_replay; // @[Frontend.scala:133:23]
wire _fq_io_enq_valid_T_6; // @[Frontend.scala:184:52]
wire _T_37 = _fq_io_enq_ready & _fq_io_enq_valid_T_6; // @[Decoupled.scala:51:35]
wire _s2_replay_T; // @[Decoupled.scala:51:35]
assign _s2_replay_T = _T_37; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T; // @[Decoupled.scala:51:35]
assign _btb_io_btb_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_8; // @[Decoupled.scala:51:35]
assign _taken_T_8 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_9; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T_9 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_37; // @[Decoupled.scala:51:35]
assign _taken_T_37 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T_3; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T_3 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_57; // @[Decoupled.scala:51:35]
assign _taken_T_57 = _T_37; // @[Decoupled.scala:51:35]
wire _s2_replay_T_1 = ~_s2_replay_T; // @[Decoupled.scala:51:35]
wire _s2_replay_T_2 = s2_valid & _s2_replay_T_1; // @[Frontend.scala:108:25, :134:{26,29}]
wire _s2_replay_T_3 = ~s0_valid; // @[Frontend.scala:113:35, :134:70]
wire _s2_replay_T_4 = s2_replay & _s2_replay_T_3; // @[Frontend.scala:133:23, :134:{67,70}]
reg s2_replay_REG; // @[Frontend.scala:134:56]
assign _s2_replay_T_5 = _s2_replay_T_2 | s2_replay_REG; // @[Frontend.scala:134:{26,46,56}]
assign s2_replay = _s2_replay_T_5; // @[Frontend.scala:133:23, :134:46]
wire [39:0] npc = s2_replay ? s2_pc : predicted_npc; // @[Frontend.scala:117:22, :130:34, :133:23, :135:16]
wire _s0_speculative_T = ~s2_speculative; // @[Frontend.scala:123:31, :141:56]
wire _s0_speculative_T_1 = s2_valid & _s0_speculative_T; // @[Frontend.scala:108:25, :141:{53,56}]
wire _s0_speculative_T_2 = s1_speculative | _s0_speculative_T_1; // @[Frontend.scala:116:27, :141:{41,53}]
wire s0_speculative = _s0_speculative_T_2 | predicted_taken; // @[Frontend.scala:131:36, :141:{41,72}]
wire _s1_speculative_T = s2_replay ? s2_speculative : s0_speculative; // @[Frontend.scala:123:31, :133:23, :141:72, :143:75]
wire _s1_speculative_T_1 = io_cpu_req_valid_0 ? io_cpu_req_bits_speculative_0 : _s1_speculative_T; // @[Frontend.scala:82:7, :143:{24,75}]
wire s2_redirect; // @[Frontend.scala:145:32]
wire _s2_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17]
reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40]
wire recent_progress = |recent_progress_counter; // @[Frontend.scala:155:40, :156:49]
assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35]
wire [2:0] _recent_progress_counter_T = {1'h0, recent_progress_counter} - 3'h1; // @[Frontend.scala:155:40, :157:97]
wire [1:0] _recent_progress_counter_T_1 = _recent_progress_counter_T[1:0]; // @[Frontend.scala:157:97]
wire _s2_kill_speculative_tlb_refill_T = ~recent_progress; // @[Frontend.scala:156:49, :160:58]
wire s2_kill_speculative_tlb_refill = s2_speculative & _s2_kill_speculative_tlb_refill_T; // @[Frontend.scala:123:31, :160:{55,58}]
wire _tlb_io_req_valid_T = ~s2_replay; // @[Frontend.scala:133:23, :147:9, :163:35]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:107:21, :163:{32,35}]
wire _tlb_io_kill_T = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :171:18]
wire _tlb_io_kill_T_1 = _tlb_io_kill_T | s2_kill_speculative_tlb_refill; // @[Frontend.scala:160:55, :171:{18,28}]
wire _icache_io_s1_kill_T = s2_redirect | _tlb_io_resp_miss; // @[Frontend.scala:105:19, :145:32, :178:36]
wire _icache_io_s1_kill_T_1 = _icache_io_s1_kill_T | s2_replay; // @[Frontend.scala:133:23, :178:{36,56}]
wire _s2_can_speculatively_refill_T = io_ptw_customCSRs_csrs_0_value_0[3]; // @[CustomCSRs.scala:46:69]
wire _s2_can_speculatively_refill_T_1 = ~_s2_can_speculatively_refill_T; // @[CustomCSRs.scala:46:69]
wire s2_can_speculatively_refill = s2_tlb_resp_cacheable & _s2_can_speculatively_refill_T_1; // @[Frontend.scala:121:24, :179:{59,62}]
wire _icache_io_s2_kill_T = ~s2_can_speculatively_refill; // @[Frontend.scala:179:59, :180:42]
wire _icache_io_s2_kill_T_1 = s2_speculative & _icache_io_s2_kill_T; // @[Frontend.scala:123:31, :180:{39,42}]
wire _icache_io_s2_kill_T_2 = _icache_io_s2_kill_T_1 | s2_xcpt; // @[Frontend.scala:122:60, :180:{39,71}]
wire _icache_io_s2_prefetch_T = io_ptw_customCSRs_csrs_0_value_0[17]; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_1 = ~_icache_io_s2_prefetch_T; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_2 = s2_tlb_resp_prefetchable & _icache_io_s2_prefetch_T_1; // @[Frontend.scala:121:24, :182:{53,56}]
reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29]
wire _fq_io_enq_valid_T = fq_io_enq_valid_REG & s2_valid; // @[Frontend.scala:108:25, :184:{29,40}]
wire _GEN = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112]
wire _fq_io_enq_valid_T_1; // @[Frontend.scala:184:112]
assign _fq_io_enq_valid_T_1 = _GEN; // @[Frontend.scala:184:112]
wire _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:150]
assign _fq_io_enq_bits_replay_T_5 = _GEN; // @[Frontend.scala:184:112, :190:150]
wire _fq_io_enq_valid_T_2 = _icache_io_resp_valid | _fq_io_enq_valid_T_1; // @[Frontend.scala:70:26, :184:{77,112}]
wire _fq_io_enq_valid_T_3 = ~s2_tlb_resp_miss; // @[Frontend.scala:121:24, :184:137]
wire _fq_io_enq_valid_T_4 = _fq_io_enq_valid_T_3 & _icache_io_s2_kill_T_2; // @[Frontend.scala:180:71, :184:{137,155}]
wire _fq_io_enq_valid_T_5 = _fq_io_enq_valid_T_2 | _fq_io_enq_valid_T_4; // @[Frontend.scala:184:{77,133,155}]
assign _fq_io_enq_valid_T_6 = _fq_io_enq_valid_T & _fq_io_enq_valid_T_5; // @[Frontend.scala:184:{40,52,133}]
wire [39:0] _io_cpu_npc_T = io_cpu_req_valid_0 ? io_cpu_req_bits_pc_0 : npc; // @[Frontend.scala:82:7, :135:16, :186:28]
wire [39:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala:186:28, :384:29]
wire [39:0] _io_cpu_npc_T_2 = {_io_cpu_npc_T_1[39:1], 1'h1}; // @[Frontend.scala:384:{29,33}]
assign _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala:384:{27,33}]
assign io_cpu_npc_0 = _io_cpu_npc_T_3; // @[Frontend.scala:82:7, :384:27]
wire _fq_io_enq_bits_mask_T = s2_pc[1]; // @[package.scala:163:13]
wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << _fq_io_enq_bits_mask_T; // @[package.scala:163:13]
wire _fq_io_enq_bits_replay_T = ~_icache_io_resp_valid; // @[Frontend.scala:70:26, :190:80]
wire _fq_io_enq_bits_replay_T_1 = _icache_io_s2_kill_T_2 & _fq_io_enq_bits_replay_T; // @[Frontend.scala:180:71, :190:{77,80}]
wire _fq_io_enq_bits_replay_T_2 = ~s2_xcpt; // @[Frontend.scala:122:60, :190:105]
wire _fq_io_enq_bits_replay_T_3 = _fq_io_enq_bits_replay_T_1 & _fq_io_enq_bits_replay_T_2; // @[Frontend.scala:190:{77,102,105}]
wire _fq_io_enq_bits_replay_T_4 = _fq_io_enq_bits_replay_T_3; // @[Frontend.scala:190:{56,102}]
wire _fq_io_enq_bits_replay_T_6 = _fq_io_enq_bits_replay_T_4 | _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:{56,115,150}]
wire _btb_io_req_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17, :209:27]
assign predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:131:36, :198:21, :213:29]
wire _predicted_npc_T = _btb_io_resp_bits_target[38]; // @[package.scala:132:38]
wire [39:0] _predicted_npc_T_1 = {_predicted_npc_T, _btb_io_resp_bits_target}; // @[package.scala:132:{15,38}]
wire [39:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala:117:22, :222:24]
wire [39:0] _s2_base_pc_T_1 = {_s2_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:222:{24,31}]
wire [39:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala:222:{22,31}]
wire [39:0] taken_pc = s2_base_pc; // @[Frontend.scala:222:22, :287:33]
wire _taken_T_35; // @[Frontend.scala:270:13]
wire taken_idx; // @[Frontend.scala:223:25]
wire [1:0] after_idx; // @[Frontend.scala:224:25]
wire useRAS; // @[Frontend.scala:225:29]
wire updateBTB; // @[Frontend.scala:226:32]
wire _fetch_bubble_likely_T = _fq_io_mask[1]; // @[Frontend.scala:91:64, :318:44]
wire fetch_bubble_likely = ~_fetch_bubble_likely_T; // @[Frontend.scala:318:{33,44}]
wire _btb_io_btb_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :319:52]
wire _btb_io_btb_update_valid_T_2 = _btb_io_btb_update_valid_T & _btb_io_btb_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T_3 = _btb_io_btb_update_valid_T_2 & fetch_bubble_likely; // @[Frontend.scala:318:33, :319:{49,64}]
wire _btb_io_btb_update_valid_T_4 = _btb_io_btb_update_valid_T_3 & updateBTB; // @[Frontend.scala:226:32, :319:{64,87}]
wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala:223:25, :323:63]
wire [39:0] _btb_io_btb_update_bits_br_pc_T_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala:222:22, :323:{50,63}]
wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala:224:25, :327:66]
wire [40:0] _btb_io_ras_update_bits_returnAddr_T_1 = {1'h0, s2_base_pc} + {38'h0, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala:129:25, :222:22, :327:{53,66}]
wire [39:0] _btb_io_ras_update_bits_returnAddr_T_2 = _btb_io_ras_update_bits_returnAddr_T_1[39:0]; // @[Frontend.scala:327:53]
wire [1:0] _taken_prevRVI_T = s2_partial_insn[1:0]; // @[Frontend.scala:125:28, :233:39]
wire _taken_prevRVI_T_1 = _taken_prevRVI_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_2 = ~_taken_prevRVI_T_1; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI = s2_partial_insn_valid & _taken_prevRVI_T_2; // @[Frontend.scala:124:38, :234:{31,34}]
wire _taken_valid_T = _fq_io_enq_bits_mask_T_1[0]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_1 = ~taken_prevRVI; // @[Frontend.scala:234:31, :235:47]
wire taken_valid = _taken_valid_T & _taken_valid_T_1; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits = _icache_io_resp_bits_data[15:0]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire [1:0] _taken_prevRVI_T_3 = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc = _taken_rvc_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits = {taken_bits, s2_partial_insn}; // @[Frontend.scala:125:28, :236:37, :238:24]
wire [6:0] _taken_rviBranch_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch = _taken_rviBranch_T == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump = _taken_rviJump_T == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR = _taken_rviJALR_T == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_1 = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_7 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_1 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_18 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_9 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_1 = ~_taken_rviReturn_T; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_2 = taken_rviJALR & _taken_rviReturn_T_1; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_3 = taken_rviBits[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_4 = _taken_rviReturn_T_3 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_5 = _taken_rviReturn_T_4 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn = _taken_rviReturn_T_2 & _taken_rviReturn_T_5; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_0 = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T; // @[Frontend.scala:243:30]
assign _taken_rviCall_T = _GEN_0; // @[Frontend.scala:243:30]
wire _taken_taken_T; // @[Frontend.scala:255:29]
assign _taken_taken_T = _GEN_0; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall = _taken_rviCall_T & _taken_rviCall_T_1; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_1 = taken_bits & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T = _GEN_1; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_2; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_2 = _GEN_1; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T = _GEN_1; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T = _GEN_1; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_1 = _taken_rvcBranch_T == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_3 = _taken_rvcBranch_T_2 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch = _taken_rvcBranch_T_1 | _taken_rvcBranch_T_3; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_1 = _taken_rvcJAL_T == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_1 = _taken_rvcJump_T == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump = _taken_rvcJump_T_1; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T = taken_bits[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_1 = taken_bits[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_9 = taken_bits[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_2 = {5{_taken_rvcImm_T_1}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_3 = taken_bits[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_4 = taken_bits[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_15 = taken_bits[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_5 = taken_bits[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_6 = taken_bits[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi = {_taken_rvcImm_T_5, _taken_rvcImm_T_6}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo = {taken_rvcImm_lo_hi, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi = {_taken_rvcImm_T_2, _taken_rvcImm_T_3}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi = {taken_rvcImm_hi_hi, _taken_rvcImm_T_4}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_7 = {taken_rvcImm_hi, taken_rvcImm_lo}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_8 = _taken_rvcImm_T_7; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_10 = {10{_taken_rvcImm_T_9}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_11 = taken_bits[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_12 = taken_bits[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_13 = taken_bits[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_14 = taken_bits[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_16 = taken_bits[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_17 = taken_bits[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo = {_taken_rvcImm_T_17, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_1 = {_taken_rvcImm_T_15, _taken_rvcImm_T_16}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_1 = {taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo = {_taken_rvcImm_T_13, _taken_rvcImm_T_14}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi = {_taken_rvcImm_T_10, _taken_rvcImm_T_11}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_1 = {taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_1 = {taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_18 = {taken_rvcImm_hi_1, taken_rvcImm_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_19 = _taken_rvcImm_T_18; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm = _taken_rvcImm_T ? {{8{_taken_rvcImm_T_8[12]}}, _taken_rvcImm_T_8} : _taken_rvcImm_T_19; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_2 = taken_bits & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T = _GEN_2; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T = _GEN_2; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_1 = _taken_rvcJR_T == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_3 = _taken_rvcJR_T_2 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR = _taken_rvcJR_T_1 & _taken_rvcJR_T_3; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T = taken_bits[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_1 = _taken_rvcReturn_T & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_2 = _taken_rvcReturn_T_1 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn = taken_rvcJR & _taken_rvcReturn_T_2; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_1 = _taken_rvcJALR_T == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_3 = _taken_rvcJALR_T_2 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR = _taken_rvcJALR_T_1 & _taken_rvcJALR_T_3; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall = taken_rvcJALR; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T = taken_rviBits[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_1 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_4 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_2 = _taken_rviImm_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign = _taken_rviImm_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_9 = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_1 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_4 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_2 = _taken_rviImm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20 = {11{taken_rviImm_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo = taken_rviImm_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_3 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_8 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_4 = _taken_rviImm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12 = _taken_rviImm_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi = taken_rviImm_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_4 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_3 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_15 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_11 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_5 = _taken_rviImm_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_10 = _taken_rviImm_b11_T_5; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_8 = _taken_rviImm_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11 = _taken_rviImm_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo = taken_rviImm_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_3 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_7 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5 = _taken_rviImm_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_4 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_14 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_6 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_16 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_7 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_17 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_8 = _taken_rviImm_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_9 = _taken_rviImm_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1 = _taken_rviImm_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_5 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_13 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi = {taken_rviImm_b10_5, taken_rviImm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo = {taken_rviImm_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo = {taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi = {taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi = {taken_rviImm_hi_hi, taken_rviImm_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_1 = {taken_rviImm_hi, taken_rviImm_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_2 = _taken_rviImm_T_1; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_5 = _taken_rviImm_sign_T_4; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_1 = _taken_rviImm_sign_T_5; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_1 = taken_rviImm_sign_1; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_5 = _taken_rviImm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_1 = {11{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_1 = taken_rviImm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_9 = _taken_rviImm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_1 = {8{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_1 = taken_rviImm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_16 = _taken_rviImm_b11_T_15; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_19 = _taken_rviImm_b11_T_18; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_20 = _taken_rviImm_b11_T_19; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_21 = _taken_rviImm_b11_T_20; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_1 = _taken_rviImm_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_1 = taken_rviImm_b11_1; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_1 = _taken_rviImm_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_19 = _taken_rviImm_b4_1_T_14; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_18 = _taken_rviImm_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_1 = _taken_rviImm_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_1 = {taken_rviImm_b10_5_1, taken_rviImm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_1 = {taken_rviImm_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_1 = {taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_1 = {taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_1 = {taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_3 = {taken_rviImm_hi_1, taken_rviImm_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_4 = _taken_rviImm_T_3; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm = _taken_rviImm_T ? _taken_rviImm_T_2 : _taken_rviImm_T_4; // @[RocketCore.scala:1355:53]
wire taken_predict_taken = _taken_predict_taken_T; // @[Frontend.scala:253:54]
wire _taken_taken_T_1 = taken_rviBranch & taken_predict_taken; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_2 = _taken_taken_T | _taken_taken_T_1; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_3 = taken_prevRVI & _taken_taken_T_2; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_4 = taken_rvcJump | taken_rvcJALR; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_5 = _taken_taken_T_4 | taken_rvcJR; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_6 = taken_rvcBranch & taken_predict_taken; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_7 = _taken_taken_T_5 | _taken_taken_T_6; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_8 = taken_valid & _taken_taken_T_7; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken = _taken_taken_T_3 | _taken_taken_T_8; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_T_28 = taken_taken; // @[Frontend.scala:255:71, :313:51]
wire _taken_predictReturn_T = taken_prevRVI & taken_rviReturn; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_1 = taken_valid & taken_rvcReturn; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_2 = _taken_predictReturn_T | _taken_predictReturn_T_1; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn = _btb_io_ras_head_valid & _taken_predictReturn_T_2; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T = taken_prevRVI & taken_rviJump; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_1 = taken_valid & taken_rvcJump; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump = _taken_predictJump_T | _taken_predictJump_T_1; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_3 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T = _GEN_3; // @[Frontend.scala:259:53]
wire _taken_T_19; // @[Frontend.scala:294:23]
assign _taken_T_19 = _GEN_3; // @[Frontend.scala:259:53, :294:23]
wire _GEN_4 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_1; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_1 = _GEN_4; // @[Frontend.scala:259:75]
wire _taken_T_20; // @[Frontend.scala:294:45]
assign _taken_T_20 = _GEN_4; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_2 = _taken_predictBranch_T | _taken_predictBranch_T_1; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch = taken_predict_taken & _taken_predictBranch_T_2; // @[Frontend.scala:253:54, :259:{41,66}]
wire _GEN_5 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22]
wire _taken_T; // @[Frontend.scala:261:22]
assign _taken_T = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_29; // @[Frontend.scala:261:22]
assign _taken_T_29 = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_1 = ~s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
wire _taken_T_2 = _taken_T & _taken_T_1; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_3 = _taken_T_2 & taken_valid; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_4 = ~taken_rvc; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_5 = _taken_T_3 & _taken_T_4; // @[Frontend.scala:261:{79,88,91}]
wire _taken_btb_io_ras_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_2 = _taken_btb_io_ras_update_valid_T & _taken_btb_io_ras_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_3 = taken_rviCall | taken_rviReturn; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_4 = taken_prevRVI & _taken_btb_io_ras_update_valid_T_3; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_5 = taken_rvcCall | taken_rvcReturn; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_6 = taken_valid & _taken_btb_io_ras_update_valid_T_5; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_7 = _taken_btb_io_ras_update_valid_T_4 | _taken_btb_io_ras_update_valid_T_6; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_8 = _taken_btb_io_ras_update_valid_T_2 & _taken_btb_io_ras_update_valid_T_7; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_4 = _taken_btb_io_ras_update_bits_cfiType_T_2; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_5 = ~_taken_btb_io_ras_update_bits_cfiType_T_4; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala:274:{46,50}, :275:46]
wire _taken_T_7 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_9 = _taken_T_8 & taken_taken; // @[Decoupled.scala:51:35]
wire _taken_T_10 = ~taken_predictBranch; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_11 = _taken_T_9 & _taken_T_10; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_12 = ~taken_predictJump; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_13 = _taken_T_11 & _taken_T_12; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_14 = ~taken_predictReturn; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_15 = _taken_T_13 & _taken_T_14; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala:108:25, :257:49, :283:26]
wire _taken_T_17 = taken_predictBranch | taken_predictJump; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_18 = s2_valid & _taken_T_17; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] _taken_npc_T = taken_pc; // @[Frontend.scala:287:33, :289:32]
wire [32:0] _taken_npc_T_1 = {taken_rviImm[31], taken_rviImm} - 33'h2; // @[Frontend.scala:252:23, :289:61]
wire [32:0] _taken_npc_T_2 = taken_prevRVI ? _taken_npc_T_1 : {{12{taken_rvcImm[20]}}, taken_rvcImm}; // @[Frontend.scala:234:31, :247:23, :289:{44,61}]
wire [40:0] _taken_npc_T_3 = {_taken_npc_T[39], _taken_npc_T} + {{8{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:289:{32,39,44}]
wire [39:0] _taken_npc_T_4 = _taken_npc_T_3[39:0]; // @[Frontend.scala:289:39]
wire [39:0] taken_npc = _taken_npc_T_4; // @[Frontend.scala:289:39]
wire [39:0] _taken_predicted_npc_T = taken_npc; // @[Frontend.scala:289:39, :291:34]
wire _taken_T_21 = _taken_T_19 | _taken_T_20; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_2 = _taken_btb_io_bht_advance_valid_T & _taken_btb_io_bht_advance_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_T_22 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_24 = taken_predictBranch & _taken_T_23; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_25 = _taken_T_24 | taken_predictJump; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_26 = _taken_T_25 | taken_predictReturn; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_27 = _taken_T_22 & _taken_T_26; // @[Frontend.scala:298:{15,34,106}]
wire _taken_prevRVI_T_4 = _taken_prevRVI_T_3 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI_1 = taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala:234:{31,34}, :235:44]
wire _taken_valid_T_2 = _fq_io_enq_bits_mask_T_1[1]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_3 = ~taken_prevRVI_1; // @[Frontend.scala:234:31, :235:47]
wire taken_valid_1 = _taken_valid_T_2 & _taken_valid_T_3; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits_1 = _icache_io_resp_bits_data[31:16]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T_1 = taken_bits_1[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc_1 = _taken_rvc_T_1 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits_1 = {taken_bits_1, taken_bits}; // @[Frontend.scala:236:37, :238:24]
wire [6:0] _taken_rviBranch_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch_1 = _taken_rviBranch_T_1 == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump_1 = _taken_rviJump_T_1 == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR_1 = _taken_rviJALR_T_1 == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T_6 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_3 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_29 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_17 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_40 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_25 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_7 = ~_taken_rviReturn_T_6; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_8 = taken_rviJALR_1 & _taken_rviReturn_T_7; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_9 = taken_rviBits_1[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_10 = _taken_rviReturn_T_9 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_11 = _taken_rviReturn_T_10 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn_1 = _taken_rviReturn_T_8 & _taken_rviReturn_T_11; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_6 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T_2; // @[Frontend.scala:243:30]
assign _taken_rviCall_T_2 = _GEN_6; // @[Frontend.scala:243:30]
wire _taken_taken_T_9; // @[Frontend.scala:255:29]
assign _taken_taken_T_9 = _GEN_6; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall_1 = _taken_rviCall_T_2 & _taken_rviCall_T_3; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_7 = taken_bits_1 & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T_4; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T_4 = _GEN_7; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_6; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_6 = _GEN_7; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T_2; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T_2 = _GEN_7; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T_2; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T_2 = _GEN_7; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_5 = _taken_rvcBranch_T_4 == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_7 = _taken_rvcBranch_T_6 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch_1 = _taken_rvcBranch_T_5 | _taken_rvcBranch_T_7; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_3 = _taken_rvcJAL_T_2 == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_3 = _taken_rvcJump_T_2 == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump_1 = _taken_rvcJump_T_3; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T_20 = taken_bits_1[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_21 = taken_bits_1[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_29 = taken_bits_1[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_22 = {5{_taken_rvcImm_T_21}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_23 = taken_bits_1[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_24 = taken_bits_1[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_35 = taken_bits_1[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_25 = taken_bits_1[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_26 = taken_bits_1[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi_2 = {_taken_rvcImm_T_25, _taken_rvcImm_T_26}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo_2 = {taken_rvcImm_lo_hi_2, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi_2 = {_taken_rvcImm_T_22, _taken_rvcImm_T_23}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi_2 = {taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_27 = {taken_rvcImm_hi_2, taken_rvcImm_lo_2}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_28 = _taken_rvcImm_T_27; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_30 = {10{_taken_rvcImm_T_29}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_31 = taken_bits_1[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_32 = taken_bits_1[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_33 = taken_bits_1[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_34 = taken_bits_1[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_36 = taken_bits_1[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_37 = taken_bits_1[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo_1 = {_taken_rvcImm_T_37, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_3 = {_taken_rvcImm_T_35, _taken_rvcImm_T_36}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_3 = {taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo_1 = {_taken_rvcImm_T_33, _taken_rvcImm_T_34}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi_1 = {_taken_rvcImm_T_30, _taken_rvcImm_T_31}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_3 = {taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_3 = {taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_38 = {taken_rvcImm_hi_3, taken_rvcImm_lo_3}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_39 = _taken_rvcImm_T_38; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm_1 = _taken_rvcImm_T_20 ? {{8{_taken_rvcImm_T_28[12]}}, _taken_rvcImm_T_28} : _taken_rvcImm_T_39; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_8 = taken_bits_1 & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T_4; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T_4 = _GEN_8; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T_4; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T_4 = _GEN_8; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_5 = _taken_rvcJR_T_4 == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_7 = _taken_rvcJR_T_6 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR_1 = _taken_rvcJR_T_5 & _taken_rvcJR_T_7; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T_3 = taken_bits_1[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_4 = _taken_rvcReturn_T_3 & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_5 = _taken_rvcReturn_T_4 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn_1 = taken_rvcJR_1 & _taken_rvcReturn_T_5; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_5 = _taken_rvcJALR_T_4 == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_7 = _taken_rvcJALR_T_6 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR_1 = _taken_rvcJALR_T_5 & _taken_rvcJALR_T_7; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall_1 = taken_rvcJALR_1; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T_5 = taken_rviBits_1[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_7 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_10 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_8 = _taken_rviImm_sign_T_7; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_2 = _taken_rviImm_sign_T_8; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_31 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi_2 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_7 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_10 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_8 = _taken_rviImm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_2 = {11{taken_rviImm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_2 = taken_rviImm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_13 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_18 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_14 = _taken_rviImm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_2 = _taken_rviImm_b19_12_T_14; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviImm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_26 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_19 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_37 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_27 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_27 = _taken_rviImm_b11_T_26; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_32 = _taken_rviImm_b11_T_27; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_30 = _taken_rviImm_b11_T_29; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11_2 = _taken_rviImm_b11_T_32; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_2 = taken_rviImm_b11_2; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_11 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_15 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5_2 = _taken_rviImm_b10_5_T_11; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_24 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_34 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_26 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_36 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_27 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_37 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_28 = _taken_rviImm_b4_1_T_27; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_29 = _taken_rviImm_b4_1_T_28; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1_2 = _taken_rviImm_b4_1_T_29; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_21 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_29 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi_2 = {taken_rviImm_b10_5_2, taken_rviImm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_2 = {taken_rviImm_lo_hi_2, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_2 = {taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_2 = {taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_2 = {taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_6 = {taken_rviImm_hi_2, taken_rviImm_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_7 = _taken_rviImm_T_6; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_11 = _taken_rviImm_sign_T_10; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_3 = _taken_rviImm_sign_T_11; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_3 = taken_rviImm_sign_3; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_11 = _taken_rviImm_b30_20_T_10; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_3 = {11{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_3 = taken_rviImm_b30_20_3; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_19 = _taken_rviImm_b19_12_T_18; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_3 = {8{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_3 = taken_rviImm_b19_12_3; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_38 = _taken_rviImm_b11_T_37; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_41 = _taken_rviImm_b11_T_40; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_42 = _taken_rviImm_b11_T_41; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_43 = _taken_rviImm_b11_T_42; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_3 = _taken_rviImm_b11_T_43; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_3 = taken_rviImm_b11_3; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_3 = _taken_rviImm_b10_5_T_15; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_39 = _taken_rviImm_b4_1_T_34; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_38 = _taken_rviImm_b4_1_T_37; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_3 = _taken_rviImm_b4_1_T_39; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_3 = {taken_rviImm_b10_5_3, taken_rviImm_b4_1_3}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_3 = {taken_rviImm_lo_hi_3, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_3 = {taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_3 = {taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_3 = {taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_8 = {taken_rviImm_hi_3, taken_rviImm_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_9 = _taken_rviImm_T_8; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm_1 = _taken_rviImm_T_5 ? _taken_rviImm_T_7 : _taken_rviImm_T_9; // @[RocketCore.scala:1355:53]
wire taken_predict_taken_1 = _taken_predict_taken_T_1; // @[Frontend.scala:253:54]
wire _taken_taken_T_10 = taken_rviBranch_1 & taken_predict_taken_1; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_11 = _taken_taken_T_9 | _taken_taken_T_10; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_12 = taken_prevRVI_1 & _taken_taken_T_11; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_13 = taken_rvcJump_1 | taken_rvcJALR_1; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_14 = _taken_taken_T_13 | taken_rvcJR_1; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_15 = taken_rvcBranch_1 & taken_predict_taken_1; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_16 = _taken_taken_T_14 | _taken_taken_T_15; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_17 = taken_valid_1 & _taken_taken_T_16; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken_1 = _taken_taken_T_12 | _taken_taken_T_17; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_predictReturn_T_3 = taken_prevRVI_1 & taken_rviReturn_1; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_4 = taken_valid_1 & taken_rvcReturn_1; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_5 = _taken_predictReturn_T_3 | _taken_predictReturn_T_4; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn_1 = _btb_io_ras_head_valid & _taken_predictReturn_T_5; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T_2 = taken_prevRVI_1 & taken_rviJump_1; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_3 = taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump_1 = _taken_predictJump_T_2 | _taken_predictJump_T_3; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_9 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T_3; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T_3 = _GEN_9; // @[Frontend.scala:259:53]
wire _taken_T_48; // @[Frontend.scala:294:23]
assign _taken_T_48 = _GEN_9; // @[Frontend.scala:259:53, :294:23]
wire _GEN_10 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_4; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_4 = _GEN_10; // @[Frontend.scala:259:75]
wire _taken_T_49; // @[Frontend.scala:294:45]
assign _taken_T_49 = _GEN_10; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_5 = _taken_predictBranch_T_3 | _taken_predictBranch_T_4; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch_1 = taken_predict_taken_1 & _taken_predictBranch_T_5; // @[Frontend.scala:253:54, :259:{41,66}]
wire _taken_T_31 = _taken_T_29 & _taken_T_30; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_32 = _taken_T_31 & taken_valid_1; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_34 = _taken_T_32 & _taken_T_33; // @[Frontend.scala:261:{79,88,91}]
assign _taken_T_35 = ~_taken_T_28; // @[Frontend.scala:270:13, :313:51]
assign taken_idx = _taken_T_35; // @[Frontend.scala:223:25, :270:13]
assign after_idx = _taken_T_35 ? 2'h2 : 2'h1; // @[Frontend.scala:224:25, :270:{13,25}, :272:19]
wire _taken_btb_io_ras_update_valid_T_10 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_11 = _taken_btb_io_ras_update_valid_T_9 & _taken_btb_io_ras_update_valid_T_10; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_12 = taken_rviCall_1 | taken_rviReturn_1; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_13 = taken_prevRVI_1 & _taken_btb_io_ras_update_valid_T_12; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_14 = taken_rvcCall_1 | taken_rvcReturn_1; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_15 = taken_valid_1 & _taken_btb_io_ras_update_valid_T_14; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_16 = _taken_btb_io_ras_update_valid_T_13 | _taken_btb_io_ras_update_valid_T_15; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_17 = _taken_btb_io_ras_update_valid_T_11 & _taken_btb_io_ras_update_valid_T_16; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_12 = _taken_btb_io_ras_update_bits_cfiType_T_10; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_13 = ~_taken_btb_io_ras_update_bits_cfiType_T_12; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala:274:{46,50}, :275:46]
assign btb_io_ras_update_bits_cfiType = _taken_T_35 ? _taken_btb_io_ras_update_bits_cfiType_T_15 : _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala:270:{13,25}, :274:{40,46}]
wire _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_38 = _taken_T_37 & taken_taken_1; // @[Decoupled.scala:51:35]
wire _taken_T_39 = ~taken_predictBranch_1; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_40 = _taken_T_38 & _taken_T_39; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_41 = ~taken_predictJump_1; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_42 = _taken_T_40 & _taken_T_41; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_43 = ~taken_predictReturn_1; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_44 = _taken_T_42 & _taken_T_43; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_45 = s2_valid & taken_predictReturn_1; // @[Frontend.scala:108:25, :257:49, :283:26]
assign useRAS = _taken_T_35 & _taken_T_36 & _taken_T_45 | _taken_T_7 & _taken_T_16; // @[Frontend.scala:225:29, :270:{13,25}, :279:{15,30}, :283:{26,44}, :284:20]
wire _taken_T_46 = taken_predictBranch_1 | taken_predictJump_1; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_47 = s2_valid & _taken_T_46; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] taken_pc_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | 2'h2}; // @[Frontend.scala:222:22, :287:33, :323:50]
wire [40:0] _taken_npc_T_5 = {1'h0, taken_pc_1} - 41'h2; // @[Frontend.scala:287:33, :290:36]
wire [39:0] _taken_npc_T_6 = _taken_npc_T_5[39:0]; // @[Frontend.scala:290:36]
wire [39:0] _taken_npc_T_7 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala:234:31, :287:33, :290:{23,36}]
wire [39:0] _taken_npc_T_8 = _taken_npc_T_7; // @[Frontend.scala:290:{23,59}]
wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? taken_rviImm_1 : {{11{taken_rvcImm_1[20]}}, taken_rvcImm_1}; // @[Frontend.scala:234:31, :247:23, :252:23, :290:71]
wire [40:0] _taken_npc_T_10 = {_taken_npc_T_8[39], _taken_npc_T_8} + {{9{_taken_npc_T_9[31]}}, _taken_npc_T_9}; // @[Frontend.scala:290:{59,66,71}]
wire [39:0] _taken_npc_T_11 = _taken_npc_T_10[39:0]; // @[Frontend.scala:290:66]
wire [39:0] taken_npc_1 = _taken_npc_T_11; // @[Frontend.scala:290:66]
wire [39:0] _taken_predicted_npc_T_1 = taken_npc_1; // @[Frontend.scala:290:66, :291:34]
wire _taken_T_50 = _taken_T_48 | _taken_T_49; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_4 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_5 = _taken_btb_io_bht_advance_valid_T_3 & _taken_btb_io_bht_advance_valid_T_4; // @[Decoupled.scala:51:35]
wire _taken_T_51 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_53 = taken_predictBranch_1 & _taken_T_52; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_54 = _taken_T_53 | taken_predictJump_1; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_55 = _taken_T_54 | taken_predictReturn_1; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_56 = _taken_T_51 & _taken_T_55; // @[Frontend.scala:298:{15,34,106}]
assign updateBTB = _taken_T_35 & _taken_T_56 | _taken_T_27; // @[Frontend.scala:226:32, :270:{13,25}, :298:{34,125}, :299:21]
wire _taken_T_58 = ~_taken_T_28; // @[Frontend.scala:270:13, :306:26, :313:51]
wire _taken_T_59 = taken_valid_1 & _taken_T_58; // @[Frontend.scala:235:44, :306:{23,26}]
wire _taken_T_60 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91, :306:40]
wire _taken_T_61 = _taken_T_59 & _taken_T_60; // @[Frontend.scala:306:{23,37,40}]
wire [15:0] _taken_s2_partial_insn_T = {taken_bits_1[15:2], 2'h3}; // @[Frontend.scala:236:37, :308:37]
wire taken = _taken_T_28 | taken_taken_1; // @[Frontend.scala:255:71, :311:19, :313:51]
assign predicted_npc = useRAS ? {1'h0, _btb_io_ras_head_bits} : _taken_T_35 & _taken_T_36 & _taken_T_47 ? _taken_predicted_npc_T_1 : _taken_T_7 & _taken_T_18 ? _taken_predicted_npc_T : predicted_taken ? _predicted_npc_T_1 : ntpc; // @[package.scala:132:15]
wire _GEN_11 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34]
assign s2_redirect = ~s2_btb_taken & taken & _T_37 | io_cpu_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File StoreSequencer.scala:
package saturn.backend
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import saturn.common._
class StoreSequencer(implicit p: Parameters) extends PipeSequencer(new StoreDataMicroOp)(p) {
def accepts(inst: VectorIssueInst) = inst.vmu && inst.opcode(5)
val valid = RegInit(false.B)
val inst = Reg(new VectorIssueInst)
val eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val sidx = Reg(UInt(3.W))
val rvd_mask = Reg(UInt(egsTotal.W))
val rvm_mask = Reg(UInt(egsPerVReg.W))
val sub_dlen = Reg(UInt(2.W))
val head = Reg(Bool())
val renvm = !inst.vm && inst.mop === mopUnit
val next_eidx = get_next_eidx(inst.vconfig.vl, eidx, inst.mem_elem_size, sub_dlen, false.B, false.B)
val tail = next_eidx === inst.vconfig.vl && sidx === inst.seg_nf
io.dis.ready := !valid || (tail && io.iss.fire) && !io.dis_stall
when (io.dis.fire) {
val iss_inst = io.dis.bits
valid := true.B
inst := iss_inst
eidx := iss_inst.vstart
sidx := 0.U
val rvd_arch_mask = Wire(Vec(32, Bool()))
for (i <- 0 until 32) {
val group = i.U >> iss_inst.emul
val rd_group = iss_inst.rd >> iss_inst.emul
rvd_arch_mask(i) := group >= rd_group && group <= (rd_group + iss_inst.nf)
}
rvd_mask := FillInterleaved(egsPerVReg, rvd_arch_mask.asUInt)
rvm_mask := Mux(!iss_inst.vm, ~(0.U(egsPerVReg.W)), 0.U)
sub_dlen := Mux(iss_inst.seg_nf =/= 0.U && (dLenOffBits.U > (3.U +& iss_inst.mem_elem_size)),
dLenOffBits.U - 3.U - iss_inst.mem_elem_size,
0.U)
head := true.B
} .elsewhen (io.iss.fire) {
valid := !tail
head := false.B
}
io.vat := inst.vat
io.seq_hazard.valid := valid
io.seq_hazard.bits.rintent := hazardMultiply(rvd_mask | rvm_mask)
io.seq_hazard.bits.wintent := 0.U
io.seq_hazard.bits.vat := inst.vat
val vd_read_oh = UIntToOH(io.rvd.req.bits.eg)
val vm_read_oh = Mux(renvm, UIntToOH(io.rvm.req.bits.eg), 0.U)
val raw_hazard = ((vm_read_oh | vd_read_oh) & io.older_writes) =/= 0.U
val data_hazard = raw_hazard
val oldest = inst.vat === io.vat_head
io.rvd.req.valid := valid && io.iss.ready
io.rvd.req.bits.eg := getEgId(inst.rd + (sidx << inst.emul), eidx, inst.mem_elem_size, false.B)
io.rvd.req.bits.oldest := oldest
io.rvm.req.valid := valid && renvm && io.iss.ready
io.rvm.req.bits.eg := getEgId(0.U, eidx, 0.U, true.B)
io.rvm.req.bits.oldest := oldest
io.iss.valid := valid && !data_hazard && (!renvm || io.rvm.req.ready) && io.rvd.req.ready
io.iss.bits.stdata := io.rvd.resp
val head_mask = get_head_mask(~(0.U(dLenB.W)), eidx , inst.mem_elem_size)
val tail_mask = get_tail_mask(~(0.U(dLenB.W)), next_eidx, inst.mem_elem_size)
val vm_mask = Mux(!renvm, ~(0.U(dLenB.W)), get_vm_mask(io.rvm.resp, eidx, inst.mem_elem_size))
io.iss.bits.stmask := vm_mask
io.iss.bits.debug_id := inst.debug_id
io.iss.bits.tail := tail
io.iss.bits.vat := inst.vat
when (io.iss.fire && !tail) {
when (next_is_new_eg(eidx, next_eidx, inst.mem_elem_size, false.B) && vParams.enableChaining.B) {
rvd_mask := rvd_mask & ~UIntToOH(io.rvd.req.bits.eg)
}
when (next_is_new_eg(eidx, next_eidx, 0.U, true.B) && vParams.enableChaining.B) {
rvm_mask := rvm_mask & ~UIntToOH(io.rvm.req.bits.eg)
}
when (sidx === inst.seg_nf) {
sidx := 0.U
eidx := next_eidx
} .otherwise {
sidx := sidx + 1.U
}
}
io.busy := valid
io.head := head
}
File Parameters.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy.{BufferParams}
import saturn.exu._
object VectorParams {
// minParams:
// For a very small area-efficient vector unit with iterative
// and element-wise functional units
def minParams = VectorParams()
// refParams
// For a standard modestly capable small vector unit with
// SIMD functional units
def refParams = minParams.copy(
vlrobEntries = 4,
vlissqEntries = 3,
vsissqEntries = 3,
vxissqEntries = 3,
vatSz = 5,
useSegmentedIMul = true,
doubleBufferSegments = true,
useScalarFPFMA = false,
vrfBanking = 4,
)
// dspParams
// For a wide high-performance vector unit with multi-issue
def dspParams = refParams.copy(
issStructure = VectorIssueStructure.Shared
)
// genParams:
// For a vector unit that performs better on less-optimized
// code sequences
def genParams = dspParams.copy(
issStructure = VectorIssueStructure.Split,
vlifqEntries = 16,
vlrobEntries = 16
)
// multiFMAParams:
// Provides a second sequencer and set of functional units for FMA operations
def multiFMAParams = genParams.copy(
issStructure = VectorIssueStructure.MultiFMA
)
// multiMACParams:
// Provides a second sequencer and set of functional units for integer MAC operations
def multiMACParams = genParams.copy(
issStructure = VectorIssueStructure.MultiMAC
)
// dmaParams:
// For a vector unit that only does memcpys, and no arithmetic
def dmaParams = VectorParams(
vdqEntries = 2,
vliqEntries = 4,
vsiqEntries = 4,
vlifqEntries = 32,
vlrobEntries = 4,
vsifqEntries = 32,
vlissqEntries = 2,
vsissqEntries = 1,
vrfBanking = 1,
useIterativeIMul = true
)
// The parameters below are approximations
// hwaParams
// For a vector unit with limited sequencer slots akin to Hwacha
def hwaParams = genParams.copy(
vatSz = 3, // 8 mseq Entries
vdqEntries = 1,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
hwachaLimiter = Some(8), // sequencer slots
)
// lgvParams
// For a vector unit with very long vector lengths
def lgvParams = VectorParams(
vatSz = 5,
vlifqEntries = 32,
vsifqEntries = 32,
vlrobEntries = 32,
vlissqEntries = 8,
vsissqEntries = 8,
vxissqEntries = 8,
vpissqEntries = 8,
useSegmentedIMul = true,
useScalarFPMisc = false,
useScalarFPFMA = false,
vrfBanking = 4,
issStructure = VectorIssueStructure.Split
)
}
case class VXSequencerParams(
name: String,
fus: Seq[FunctionalUnitFactory]
) {
def insns = fus.map(_.insns).flatten
}
case class VXIssuePathParams(
name: String,
depth: Int,
seqs: Seq[VXSequencerParams]
) {
def insns = seqs.map(_.insns).flatten
}
object VXFunctionalUnitGroups {
def integerFUs(idivDoesImul: Boolean = false) = Seq(
IntegerPipeFactory,
ShiftPipeFactory,
BitwisePipeFactory,
IntegerDivideFactory(idivDoesImul),
MaskUnitFactory,
PermuteUnitFactory
)
def integerMAC(pipeDepth: Int, useSegmented: Boolean) = Seq(
IntegerMultiplyFactory(pipeDepth, useSegmented)
)
def allIntegerFUs(idivDoesImul: Boolean, imaDepth: Int, useSegmentedImul: Boolean) = (
integerFUs(idivDoesImul) ++ integerMAC(imaDepth, useSegmentedImul)
)
def sharedFPFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, true)
)
def sharedFPMisc = Seq(
SharedFPMiscFactory
)
def fpFMA(pipeDepth: Int) = Seq(
FPFMAFactory(pipeDepth, false)
)
def fpMisc = Seq(
FPDivSqrtFactory,
FPCmpFactory,
FPConvFactory
)
def allFPFUs(fmaPipeDepth: Int, useScalarFPFMA: Boolean, useScalarFPMisc: Boolean) = (
(if (useScalarFPFMA) sharedFPFMA(fmaPipeDepth) else fpFMA(fmaPipeDepth)) ++
(if (useScalarFPMisc) sharedFPMisc else fpMisc)
)
}
sealed trait VectorIssueStructure {
def generate(params: VectorParams): Seq[VXIssuePathParams]
}
object VectorIssueStructure {
import VXFunctionalUnitGroups._
case object Unified extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp_int", (
allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul) ++
allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)
))
)
)
Seq(fp_int_path)
}
}
case object Shared extends VectorIssueStructure {
def generate(params: VectorParams) = {
val fp_int_path = VXIssuePathParams(
name = "fp_int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(fp_int_path)
}
}
case object Split extends VectorIssueStructure {
def generate(params: VectorParams) = {
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
case object MultiFMA extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useScalarFPFMA)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp0", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc)),
VXSequencerParams("fp1", fpFMA(params.fmaPipeDepth))
)
)
Seq(int_path, fp_path)
}
}
case object MultiMAC extends VectorIssueStructure {
def generate(params: VectorParams) = {
require(!params.useIterativeIMul && params.useSegmentedIMul)
val int_path = VXIssuePathParams(
name = "int",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("int0", allIntegerFUs(params.useIterativeIMul, params.imaPipeDepth, params.useSegmentedIMul)),
VXSequencerParams("int1", integerMAC(params.imaPipeDepth, params.useSegmentedIMul))
)
)
val fp_path = VXIssuePathParams(
name = "fp",
depth = params.vxissqEntries,
seqs = Seq(
VXSequencerParams("fp", allFPFUs(params.fmaPipeDepth, params.useScalarFPFMA, params.useScalarFPMisc))
)
)
Seq(int_path, fp_path)
}
}
}
case class VectorParams(
// In-order dispatch Queue
vdqEntries: Int = 4,
// Load store instruction queues (in VLSU)
vliqEntries: Int = 4,
vsiqEntries: Int = 4,
// Load store in-flight queues (in VLSU)
vlifqEntries: Int = 8,
vsifqEntries: Int = 16,
vlrobEntries: Int = 2,
// Scatter-gather engine params
vsgPorts: Int = 8,
vsgifqEntries: Int = 4,
vsgBuffers: Int = 3,
// Load/store/execute/permute/maskindex issue queues
vlissqEntries: Int = 0,
vsissqEntries: Int = 0,
vxissqEntries: Int = 0,
vpissqEntries: Int = 0,
dLen: Int = 64,
vatSz: Int = 3,
useSegmentedIMul: Boolean = false,
useScalarFPFMA: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useScalarFPMisc: Boolean = true, // Use shared scalar FPU all non-FMA FP instructions
useIterativeIMul: Boolean = false,
fmaPipeDepth: Int = 4,
imaPipeDepth: Int = 3,
// for comparisons only
hazardingMultiplier: Int = 0,
hwachaLimiter: Option[Int] = None,
enableChaining: Boolean = true,
latencyInject: Boolean = false,
enableDAE: Boolean = true,
enableOOO: Boolean = true,
enableScalarVectorAddrDisambiguation: Boolean = true,
doubleBufferSegments: Boolean = false,
vrfBanking: Int = 2,
vrfHiccupBuffer: Boolean = true,
issStructure: VectorIssueStructure = VectorIssueStructure.Unified,
tlBuffer: BufferParams = BufferParams.default,
) {
def supported_ex_insns = issStructure.generate(this).map(_.insns).flatten
}
case object VectorParamsKey extends Field[VectorParams]
trait HasVectorParams extends HasVectorConsts { this: HasCoreParameters =>
implicit val p: Parameters
def vParams: VectorParams = p(VectorParamsKey)
def dLen = vParams.dLen
def dLenB = dLen / 8
def dLenOffBits = log2Ceil(dLenB)
def dmemTagBits = log2Ceil(vParams.vlifqEntries.max(vParams.vsifqEntries))
def sgmemTagBits = log2Ceil(vParams.vsgifqEntries)
def egsPerVReg = vLen / dLen
def egsTotal = (vLen / dLen) * 32
def vrfBankBits = log2Ceil(vParams.vrfBanking)
def lsiqIdBits = log2Ceil(vParams.vliqEntries.max(vParams.vsiqEntries))
val debugIdSz = 16
val nRelease = vParams.issStructure match {
case VectorIssueStructure.Unified => 3
case VectorIssueStructure.Shared | VectorIssueStructure.Split => 4
case VectorIssueStructure.MultiFMA | VectorIssueStructure.MultiMAC => 5
}
def getEgId(vreg: UInt, eidx: UInt, eew: UInt, bitwise: Bool): UInt = {
val base = vreg << log2Ceil(egsPerVReg)
val off = eidx >> Mux(bitwise, log2Ceil(dLen).U, (log2Ceil(dLenB).U - eew))
base +& off
}
def getByteId(vreg: UInt, eidx: UInt, eew: UInt): UInt = {
Cat(getEgId(vreg, eidx, eew, false.B), (eidx << eew)(log2Ceil(dLenB)-1,0))
}
def eewByteMask(eew: UInt) = (0 until (1+log2Ceil(eLen/8))).map { e =>
Mux(e.U === eew, ((1 << (1 << e)) - 1).U, 0.U)
}.reduce(_|_)((eLen/8)-1,0)
def eewBitMask(eew: UInt) = FillInterleaved(8, eewByteMask(eew))
def cqOlder(i0: UInt, i1: UInt, tail: UInt) = (i0 < i1) ^ (i0 < tail) ^ (i1 < tail)
def dLenSplat(in: UInt, eew: UInt) = {
val v = Wire(UInt(64.W))
v := in
Mux1H(UIntToOH(eew), (0 until 4).map { i => Fill(dLenB >> i, v((8<<i)-1,0)) })
}
def sextElem(in: UInt, in_eew: UInt): UInt = VecInit.tabulate(4)( { eew =>
Cat(in((8 << eew)-1), in((8 << eew)-1,0)).asSInt
})(in_eew)(64,0)
def extractElem(in: UInt, in_eew: UInt, eidx: UInt): UInt = {
val bytes = in.asTypeOf(Vec(dLenB, UInt(8.W)))
VecInit.tabulate(4) { eew =>
val elem = if (dLen == 64 && eew == 3) {
in
} else {
VecInit(bytes.grouped(1 << eew).map(g => VecInit(g).asUInt).toSeq)(eidx(log2Ceil(dLenB)-1-eew,0))
}
elem((8 << eew)-1,0)
}(in_eew)
}
def maxPosUInt(sew: Int) = Cat(0.U, ~(0.U(((8 << sew)-1).W)))
def minNegUInt(sew: Int) = Cat(1.U, 0.U(((8 << sew)-1).W))
def maxPosSInt(sew: Int) = ((1 << ((8 << sew)-1))-1).S
def minNegSInt(sew: Int) = (-1 << ((8 << sew)-1)).S
def maxPosFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(0.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def minNegFPUInt(sew: Int) = {
val expBits = Seq(4, 5, 8, 11)(sew)
val fracBits = (8 << sew) - expBits - 1
Cat(1.U, ~(0.U(expBits.W)), 0.U(fracBits.W))
}
def get_arch_mask(reg: UInt, emul: UInt) = VecInit.tabulate(4)({ lmul =>
FillInterleaved(1 << lmul, UIntToOH(reg >> lmul)((32>>lmul)-1,0))
})(emul)
def log2_up(f: UInt, max: Int) = VecInit.tabulate(max)({nf => log2Ceil(nf+1).U})(f)
def hazardMultiply(mask: UInt): UInt = if (vParams.hazardingMultiplier == 0) { mask } else {
require((1 << vParams.hazardingMultiplier) <= egsTotal)
VecInit(mask.asBools.grouped(1 << vParams.hazardingMultiplier).map { g =>
Fill(1 << vParams.hazardingMultiplier, g.orR)
}.toSeq).asUInt
}
}
File PipeSequencer.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile.{CoreModule}
import saturn.common._
abstract class PipeSequencer[T <: Data](issType: T)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val dis = Flipped(Decoupled(new BackendIssueInst))
val dis_stall = Input(Bool()) // used to disable OOO
val seq_hazard = Output(Valid(new SequencerHazard))
val vat = Output(UInt(vParams.vatSz.W))
val vat_head = Input(UInt(vParams.vatSz.W))
val older_writes = Input(UInt(egsTotal.W))
val older_reads = Input(UInt(egsTotal.W))
val busy = Output(Bool())
val head = Output(Bool())
val rvs1 = new VectorReadIO
val rvs2 = new VectorReadIO
val rvd = new VectorReadIO
val rvm = new VectorReadIO
val perm = new Bundle {
val req = Decoupled(new CompactorReq(dLenB))
val data = Input(UInt(dLen.W))
}
val iss = Decoupled(issType)
val acc = Input(Valid(new VectorWrite(dLen)))
})
def accepts(inst: VectorIssueInst): Bool
def min(a: UInt, b: UInt) = Mux(a > b, b, a)
def get_max_offset(offset: UInt): UInt = min(offset, maxVLMax.U)(log2Ceil(maxVLMax),0)
def get_head_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask << (eidx << eew)(dLenOffBits-1,0)
def get_tail_mask(bit_mask: UInt, eidx: UInt, eew: UInt) = bit_mask >> (0.U(dLenOffBits.W) - (eidx << eew)(dLenOffBits-1,0))
def get_vm_mask(mask_resp: UInt, eidx: UInt, eew: UInt) = {
val vm_off = ((1 << dLenOffBits) - 1).U(log2Ceil(dLen).W)
val vm_eidx = (eidx & ~(vm_off >> eew))(log2Ceil(dLen)-1,0)
val vm_resp = (mask_resp >> vm_eidx)(dLenB-1,0)
Mux1H(UIntToOH(eew), (0 until 4).map { w => FillInterleaved(1 << w, vm_resp) })
}
def get_next_eidx(vl: UInt, eidx: UInt, eew: UInt, sub_dlen: UInt, reads_mask: Bool, elementwise: Bool) = {
val next = Wire(UInt((1+log2Ceil(maxVLMax)).W))
next := Mux(elementwise, eidx +& 1.U, Mux(reads_mask,
eidx +& dLen.U,
(((eidx >> (dLenOffBits.U - eew - sub_dlen)) +& 1.U) << (dLenOffBits.U - eew - sub_dlen))
))
min(vl, next)
}
def next_is_new_eg(eidx: UInt, next_eidx: UInt, eew: UInt, masked: Bool) = {
val offset = Mux(masked, log2Ceil(dLen).U, dLenOffBits.U - eew)
(next_eidx >> offset) =/= (eidx >> offset)
}
io.rvs1.req.valid := false.B
io.rvs1.req.bits := DontCare
io.rvs2.req.valid := false.B
io.rvs2.req.bits := DontCare
io.rvd.req.valid := false.B
io.rvd.req.bits := DontCare
io.rvm.req.valid := false.B
io.rvm.req.bits := DontCare
io.perm.req.valid := false.B
io.perm.req.bits := DontCare
}
| module StoreSequencer( // @[StoreSequencer.scala:8:7]
input clock, // @[StoreSequencer.scala:8:7]
input reset, // @[StoreSequencer.scala:8:7]
output io_dis_ready, // @[PipeSequencer.scala:11:14]
input io_dis_valid, // @[PipeSequencer.scala:11:14]
input [31:0] io_dis_bits_bits, // @[PipeSequencer.scala:11:14]
input [8:0] io_dis_bits_vconfig_vl, // @[PipeSequencer.scala:11:14]
input [2:0] io_dis_bits_vconfig_vtype_vsew, // @[PipeSequencer.scala:11:14]
input [7:0] io_dis_bits_vstart, // @[PipeSequencer.scala:11:14]
input [4:0] io_dis_bits_vat, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_emul, // @[PipeSequencer.scala:11:14]
input [15:0] io_dis_bits_debug_id, // @[PipeSequencer.scala:11:14]
input [1:0] io_dis_bits_mop, // @[PipeSequencer.scala:11:14]
output io_seq_hazard_valid, // @[PipeSequencer.scala:11:14]
output [4:0] io_seq_hazard_bits_vat, // @[PipeSequencer.scala:11:14]
output [127:0] io_seq_hazard_bits_rintent, // @[PipeSequencer.scala:11:14]
output [4:0] io_vat, // @[PipeSequencer.scala:11:14]
input [4:0] io_vat_head, // @[PipeSequencer.scala:11:14]
input [127:0] io_older_writes, // @[PipeSequencer.scala:11:14]
output io_busy, // @[PipeSequencer.scala:11:14]
input io_rvd_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvd_req_valid, // @[PipeSequencer.scala:11:14]
output [6:0] io_rvd_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvd_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvd_resp, // @[PipeSequencer.scala:11:14]
input io_rvm_req_ready, // @[PipeSequencer.scala:11:14]
output io_rvm_req_valid, // @[PipeSequencer.scala:11:14]
output [6:0] io_rvm_req_bits_eg, // @[PipeSequencer.scala:11:14]
output io_rvm_req_bits_oldest, // @[PipeSequencer.scala:11:14]
input [63:0] io_rvm_resp, // @[PipeSequencer.scala:11:14]
input io_iss_ready, // @[PipeSequencer.scala:11:14]
output io_iss_valid, // @[PipeSequencer.scala:11:14]
output [63:0] io_iss_bits_stdata, // @[PipeSequencer.scala:11:14]
output [7:0] io_iss_bits_stmask, // @[PipeSequencer.scala:11:14]
output [15:0] io_iss_bits_debug_id, // @[PipeSequencer.scala:11:14]
output io_iss_bits_tail, // @[PipeSequencer.scala:11:14]
output [4:0] io_iss_bits_vat // @[PipeSequencer.scala:11:14]
);
wire io_iss_valid_0; // @[StoreSequencer.scala:71:{25,41,73}]
wire [1:0] _eidx_7to6; // @[Parameters.scala:343:{20,26}]
wire [6:0] _io_rvd_req_bits_eg_T_7; // @[Parameters.scala:344:10]
reg valid; // @[StoreSequencer.scala:11:25]
reg [31:0] inst_bits; // @[StoreSequencer.scala:12:21]
reg [8:0] inst_vconfig_vl; // @[StoreSequencer.scala:12:21]
reg [2:0] inst_vconfig_vtype_vsew; // @[StoreSequencer.scala:12:21]
reg [4:0] inst_vat; // @[StoreSequencer.scala:12:21]
reg [1:0] inst_emul; // @[StoreSequencer.scala:12:21]
reg [15:0] inst_debug_id; // @[StoreSequencer.scala:12:21]
reg [1:0] inst_mop; // @[StoreSequencer.scala:12:21]
reg [7:0] eidx; // @[StoreSequencer.scala:13:21]
reg [2:0] sidx; // @[StoreSequencer.scala:14:21]
reg [127:0] rvd_mask; // @[StoreSequencer.scala:15:21]
reg [3:0] rvm_mask; // @[StoreSequencer.scala:16:21]
reg [1:0] sub_dlen; // @[StoreSequencer.scala:17:21]
wire renvm = ~(inst_bits[25]) & inst_mop == 2'h0; // @[Bundles.scala:60:16]
wire [2:0] _GEN = {1'h0, inst_bits[13:12]}; // @[Bundles.scala:59:{26,59}]
wire [2:0] _next_eidx_next_T_8 = 3'h3 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Bundles.scala:59:{26,30}]
wire [2:0] _GEN_0 = {1'h0, sub_dlen}; // @[StoreSequencer.scala:17:21]
wire [15:0] _next_eidx_next_T_14 = {7'h0, {1'h0, eidx >> _next_eidx_next_T_8 - _GEN_0} + 9'h1} << _next_eidx_next_T_8 - _GEN_0; // @[StoreSequencer.scala:13:21]
wire [8:0] next_eidx = inst_vconfig_vl > _next_eidx_next_T_14[8:0] ? _next_eidx_next_T_14[8:0] : inst_vconfig_vl; // @[StoreSequencer.scala:12:21]
wire tail = next_eidx == inst_vconfig_vl & sidx == (~(|(inst_bits[27:26])) & inst_bits[24:20] == 5'h8 ? 3'h0 : inst_bits[31:29]); // @[Bundles.scala:61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
wire _io_dis_ready_T_1 = io_iss_ready & io_iss_valid_0; // @[Decoupled.scala:51:35]
wire io_dis_ready_0 = ~valid | tail & _io_dis_ready_T_1; // @[Decoupled.scala:51:35]
wire [127:0] vd_read_oh = 128'h1 << _io_rvd_req_bits_eg_T_7; // @[OneHot.scala:58:35]
wire [127:0] _rvm_mask_T_4 = 128'h1 << _eidx_7to6; // @[OneHot.scala:58:35]
wire oldest = inst_vat == io_vat_head; // @[StoreSequencer.scala:12:21, :62:25]
wire [5:0] _io_rvd_req_bits_eg_T_1 = {3'h0, sidx} << inst_emul; // @[StoreSequencer.scala:12:21, :14:21, :65:49]
wire [7:0] io_rvd_req_bits_eg_off = eidx >> 3'h3 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Parameters.scala:343:{20,73}]
assign _io_rvd_req_bits_eg_T_7 = {inst_bits[11:7] + _io_rvd_req_bits_eg_T_1[4:0], 2'h0} + io_rvd_req_bits_eg_off[6:0]; // @[Parameters.scala:343:20, :344:10]
assign _eidx_7to6 = eidx[7:6]; // @[Parameters.scala:343:{20,26}]
assign io_iss_valid_0 = valid & (((renvm ? _rvm_mask_T_4 : 128'h0) | vd_read_oh) & io_older_writes) == 128'h0 & (~renvm | io_rvm_req_ready) & io_rvd_req_ready; // @[OneHot.scala:58:35]
wire [2:0] _vm_mask_T_4 = inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN; // @[Bundles.scala:59:{26,30}]
wire [63:0] _vm_mask_vm_resp_T = io_rvm_resp >> (eidx[5:0] & ~(6'h7 >> _vm_mask_T_4)); // @[Bundles.scala:59:26]
wire [4:0] _GEN_1 = {3'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:36:34]
wire [4:0] rd_group = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [1:0] group = 2'h0 >> io_dis_bits_emul; // @[StoreSequencer.scala:35:23]
wire [4:0] _GEN_2 = {4'h0, group[0]}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_1 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [1:0] group_1 = 2'h1 >> io_dis_bits_emul; // @[StoreSequencer.scala:35:23]
wire [4:0] _GEN_3 = {4'h0, group_1[0]}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_2 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_4 = {3'h0, 2'h2 >> io_dis_bits_emul}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_3 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_5 = {3'h0, 2'h3 >> io_dis_bits_emul}; // @[StoreSequencer.scala:35:23, :37:33]
wire [2:0] _GEN_6 = {1'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:35:23]
wire [4:0] rd_group_4 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_7 = {2'h0, 3'h4 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_5 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_8 = {2'h0, 3'h5 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_6 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_9 = {2'h0, 3'h6 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [4:0] rd_group_7 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_10 = {2'h0, 3'h7 >> _GEN_6}; // @[StoreSequencer.scala:35:23, :37:33]
wire [3:0] _GEN_11 = {2'h0, io_dis_bits_emul}; // @[StoreSequencer.scala:35:23]
wire [4:0] rd_group_8 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_12 = {1'h0, 4'h8 >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_9 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_13 = {1'h0, 4'h9 >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_10 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_14 = {1'h0, 4'hA >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_11 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_15 = {1'h0, 4'hB >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_12 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_16 = {1'h0, 4'hC >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_13 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_17 = {1'h0, 4'hD >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_14 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_18 = {1'h0, 4'hE >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] rd_group_15 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] _GEN_19 = {1'h0, 4'hF >> _GEN_11}; // @[StoreSequencer.scala:8:7, :35:23, :37:33]
wire [4:0] group_16 = 5'h10 >> _GEN_1; // @[StoreSequencer.scala:8:7, :35:23, :36:34]
wire [4:0] rd_group_16 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_17 = 5'h11 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_17 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_18 = 5'h12 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_18 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_19 = 5'h13 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_19 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_20 = 5'h14 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_20 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_21 = 5'h15 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_21 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_22 = 5'h16 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_22 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_23 = 5'h17 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_23 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_24 = 5'h18 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_24 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_25 = 5'h19 >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_25 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_26 = 5'h1A >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_26 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_27 = 5'h1B >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_27 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_28 = 5'h1C >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_28 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_29 = 5'h1D >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_29 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_30 = 5'h1E >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_30 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire [4:0] group_31 = 5'h1F >> _GEN_1; // @[StoreSequencer.scala:35:23, :36:34]
wire [4:0] rd_group_31 = io_dis_bits_bits[11:7] >> _GEN_1; // @[Bundles.scala:70:17]
wire _GEN_20 = io_dis_ready_0 & io_dis_valid; // @[Decoupled.scala:51:35]
wire _GEN_21 = _io_dis_ready_T_1 & ~tail; // @[Decoupled.scala:51:35]
wire [2:0] _offset_T = 3'h3 - (inst_mop[0] ? inst_vconfig_vtype_vsew : _GEN); // @[Bundles.scala:59:{26,30}]
wire _GEN_22 = sidx == (~(|(inst_bits[27:26])) & inst_bits[24:20] == 5'h8 ? 3'h0 : inst_bits[31:29]); // @[Bundles.scala:61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
wire [4:0] _GEN_23 = {2'h0, io_dis_bits_bits[31:29]}; // @[Bundles.scala:63:16]
always @(posedge clock) begin // @[StoreSequencer.scala:8:7]
if (reset) // @[StoreSequencer.scala:8:7]
valid <= 1'h0; // @[StoreSequencer.scala:11:25]
else // @[StoreSequencer.scala:8:7]
valid <= _GEN_20 | (_io_dis_ready_T_1 ? ~tail : valid); // @[Decoupled.scala:51:35]
if (_GEN_20) begin // @[Decoupled.scala:51:35]
inst_bits <= io_dis_bits_bits; // @[StoreSequencer.scala:12:21]
inst_vconfig_vl <= io_dis_bits_vconfig_vl; // @[StoreSequencer.scala:12:21]
inst_vconfig_vtype_vsew <= io_dis_bits_vconfig_vtype_vsew; // @[StoreSequencer.scala:12:21]
inst_vat <= io_dis_bits_vat; // @[StoreSequencer.scala:12:21]
inst_emul <= io_dis_bits_emul; // @[StoreSequencer.scala:12:21]
inst_debug_id <= io_dis_bits_debug_id; // @[StoreSequencer.scala:12:21]
inst_mop <= io_dis_bits_mop; // @[StoreSequencer.scala:12:21]
sub_dlen <= (|(io_dis_bits_bits[27:26] == 2'h0 & io_dis_bits_bits[24:20] == 5'h8 ? 3'h0 : io_dis_bits_bits[31:29])) & {1'h0, io_dis_bits_mop[0] ? io_dis_bits_vconfig_vtype_vsew : {1'h0, io_dis_bits_bits[13:12]}} + 4'h3 < 4'h3 ? 2'h0 - (io_dis_bits_mop[0] ? io_dis_bits_vconfig_vtype_vsew[1:0] : io_dis_bits_bits[13:12]) : 2'h0; // @[Bundles.scala:59:{26,30,59}, :61:22, :62:18, :63:16, :64:{21,33,41}, :65:19]
end
if (_GEN_21 & _GEN_22) // @[StoreSequencer.scala:26:22, :81:{21,31}, :88:{16,33}, :90:12]
eidx <= next_eidx[7:0]; // @[StoreSequencer.scala:13:21, :90:12]
else if (_GEN_20) // @[Decoupled.scala:51:35]
eidx <= io_dis_bits_vstart; // @[StoreSequencer.scala:13:21]
if (_GEN_21) // @[StoreSequencer.scala:81:21]
sidx <= _GEN_22 ? 3'h0 : sidx + 3'h1; // @[StoreSequencer.scala:14:21, :88:{16,33}, :89:12, :92:{12,20}]
else if (_GEN_20) // @[Decoupled.scala:51:35]
sidx <= 3'h0; // @[StoreSequencer.scala:14:21]
if (~_GEN_21 | next_eidx >> _offset_T == {1'h0, eidx >> _offset_T}) begin // @[StoreSequencer.scala:13:21, :26:22, :81:{21,31}, :82:101, :83:16]
if (_GEN_20) // @[Decoupled.scala:51:35]
rvd_mask <=
{{4{group_31 >= rd_group_31 & group_31 <= rd_group_31 + _GEN_23}},
{4{group_30 >= rd_group_30 & group_30 <= rd_group_30 + _GEN_23}},
{4{group_29 >= rd_group_29 & group_29 <= rd_group_29 + _GEN_23}},
{4{group_28 >= rd_group_28 & group_28 <= rd_group_28 + _GEN_23}},
{4{group_27 >= rd_group_27 & group_27 <= rd_group_27 + _GEN_23}},
{4{group_26 >= rd_group_26 & group_26 <= rd_group_26 + _GEN_23}},
{4{group_25 >= rd_group_25 & group_25 <= rd_group_25 + _GEN_23}},
{4{group_24 >= rd_group_24 & group_24 <= rd_group_24 + _GEN_23}},
{4{group_23 >= rd_group_23 & group_23 <= rd_group_23 + _GEN_23}},
{4{group_22 >= rd_group_22 & group_22 <= rd_group_22 + _GEN_23}},
{4{group_21 >= rd_group_21 & group_21 <= rd_group_21 + _GEN_23}},
{4{group_20 >= rd_group_20 & group_20 <= rd_group_20 + _GEN_23}},
{4{group_19 >= rd_group_19 & group_19 <= rd_group_19 + _GEN_23}},
{4{group_18 >= rd_group_18 & group_18 <= rd_group_18 + _GEN_23}},
{4{group_17 >= rd_group_17 & group_17 <= rd_group_17 + _GEN_23}},
{4{group_16 >= rd_group_16 & group_16 <= rd_group_16 + _GEN_23}},
{4{_GEN_19 >= rd_group_15 & _GEN_19 <= rd_group_15 + _GEN_23}},
{4{_GEN_18 >= rd_group_14 & _GEN_18 <= rd_group_14 + _GEN_23}},
{4{_GEN_17 >= rd_group_13 & _GEN_17 <= rd_group_13 + _GEN_23}},
{4{_GEN_16 >= rd_group_12 & _GEN_16 <= rd_group_12 + _GEN_23}},
{4{_GEN_15 >= rd_group_11 & _GEN_15 <= rd_group_11 + _GEN_23}},
{4{_GEN_14 >= rd_group_10 & _GEN_14 <= rd_group_10 + _GEN_23}},
{4{_GEN_13 >= rd_group_9 & _GEN_13 <= rd_group_9 + _GEN_23}},
{4{_GEN_12 >= rd_group_8 & _GEN_12 <= rd_group_8 + _GEN_23}},
{4{_GEN_10 >= rd_group_7 & _GEN_10 <= rd_group_7 + _GEN_23}},
{4{_GEN_9 >= rd_group_6 & _GEN_9 <= rd_group_6 + _GEN_23}},
{4{_GEN_8 >= rd_group_5 & _GEN_8 <= rd_group_5 + _GEN_23}},
{4{_GEN_7 >= rd_group_4 & _GEN_7 <= rd_group_4 + _GEN_23}},
{4{_GEN_5 >= rd_group_3 & _GEN_5 <= rd_group_3 + _GEN_23}},
{4{_GEN_4 >= rd_group_2 & _GEN_4 <= rd_group_2 + _GEN_23}},
{4{_GEN_3 >= rd_group_1 & _GEN_3 <= rd_group_1 + _GEN_23}},
{4{_GEN_2 >= rd_group & _GEN_2 <= rd_group + _GEN_23}}}; // @[StoreSequencer.scala:15:21, :35:23, :36:34, :37:{33,45,54,67}, :39:32]
end
else // @[StoreSequencer.scala:26:22, :81:31, :82:101]
rvd_mask <= rvd_mask & ~vd_read_oh; // @[OneHot.scala:58:35]
if (~_GEN_21 | {6'h0, next_eidx[8:6]} == {7'h0, _eidx_7to6}) begin // @[Parameters.scala:342:21, :343:{20,26}, :344:10]
if (_GEN_20) // @[Decoupled.scala:51:35]
rvm_mask <= {4{~(io_dis_bits_bits[25])}}; // @[Bundles.scala:60:16]
end
else // @[StoreSequencer.scala:26:22, :81:31, :85:85]
rvm_mask <= ~(_rvm_mask_T_4[3:0]) & rvm_mask; // @[OneHot.scala:58:35]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59]
wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14]
wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27]
wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25]
wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28]
wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28]
wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49]
wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File dpath.scala:
//**************************************************************************
// RISCV Processor 1-Stage Datapath
//--------------------------------------------------------------------------
//
// Christopher Celio
// 2012 Jan 11
package sodor.stage1
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.{CSRFile, Causes}
import freechips.rocketchip.rocket.CoreInterrupts
import sodor.stage1.Constants._
import sodor.common._
class DatToCtlIo(implicit val conf: SodorCoreParams) extends Bundle()
{
val inst = Output(UInt(32.W))
val imiss = Output(Bool())
val br_eq = Output(Bool())
val br_lt = Output(Bool())
val br_ltu = Output(Bool())
val csr_eret = Output(Bool())
val csr_interrupt = Output(Bool())
val inst_misaligned = Output(Bool())
val mem_address_low = Output(UInt(3.W))
}
class DpathIo(implicit val p: Parameters, val conf: SodorCoreParams) extends Bundle()
{
val ddpath = Flipped(new DebugDPath())
val imem = new MemPortIo(conf.xprlen)
val dmem = new MemPortIo(conf.xprlen)
val ctl = Flipped(new CtlToDatIo())
val dat = new DatToCtlIo()
val interrupt = Input(new CoreInterrupts(false))
val hartid = Input(UInt())
val reset_vector = Input(UInt())
}
class DatPath(implicit val p: Parameters, val conf: SodorCoreParams) extends Module
{
val io = IO(new DpathIo())
io := DontCare
// Exception handling values
val tval_data_ma = Wire(UInt(conf.xprlen.W))
val tval_inst_ma = Wire(UInt(conf.xprlen.W))
// Interrupt kill
val interrupt_edge = Wire(Bool())
// Instruction Fetch
val pc_next = Wire(UInt(32.W))
val pc_plus4 = Wire(UInt(32.W))
val br_target = Wire(UInt(32.W))
val jmp_target = Wire(UInt(32.W))
val jump_reg_target = Wire(UInt(32.W))
val exception_target = Wire(UInt(32.W))
// PC Register
pc_next := MuxCase(pc_plus4, Array(
(io.ctl.pc_sel === PC_4) -> pc_plus4,
(io.ctl.pc_sel === PC_BR) -> br_target,
(io.ctl.pc_sel === PC_J ) -> jmp_target,
(io.ctl.pc_sel === PC_JR) -> jump_reg_target,
(io.ctl.pc_sel === PC_EXC) -> exception_target
))
val pc_reg = RegInit(io.reset_vector)
when (!io.ctl.stall)
{
pc_reg := pc_next
}
pc_plus4 := (pc_reg + 4.asUInt(conf.xprlen.W))
// Instruction memory buffer to store instruction during multicycle data request
io.dat.imiss := (io.imem.req.valid && !io.imem.resp.valid)
val reg_dmiss = RegNext(io.ctl.dmiss, false.B)
val if_inst_buffer = RegInit(0.U(32.W))
when (io.imem.resp.valid) {
assert(!reg_dmiss, "instruction arrived during data miss")
if_inst_buffer := io.imem.resp.bits.data
}
io.imem.req.bits.fcn := M_XRD
io.imem.req.bits.typ := MT_WU
io.imem.req.bits.addr := pc_reg
io.imem.req.valid := !reg_dmiss
val inst = Mux(reg_dmiss, if_inst_buffer, io.imem.resp.bits.data)
// Instruction misalign detection
// In control path, instruction misalignment exception is always raised in the next cycle once the misaligned instruction reaches
// execution stage, regardless whether the pipeline stalls or not
io.dat.inst_misaligned := (br_target(1, 0).orR && io.ctl.pc_sel_no_xept === PC_BR) ||
(jmp_target(1, 0).orR && io.ctl.pc_sel_no_xept === PC_J) ||
(jump_reg_target(1, 0).orR && io.ctl.pc_sel_no_xept === PC_JR)
tval_inst_ma := MuxCase(0.U, Array(
(io.ctl.pc_sel_no_xept === PC_BR) -> br_target,
(io.ctl.pc_sel_no_xept === PC_J) -> jmp_target,
(io.ctl.pc_sel_no_xept === PC_JR) -> jump_reg_target
))
// Decode
val rs1_addr = inst(RS1_MSB, RS1_LSB)
val rs2_addr = inst(RS2_MSB, RS2_LSB)
val wb_addr = inst(RD_MSB, RD_LSB)
val wb_data = Wire(UInt(conf.xprlen.W))
val wb_wen = io.ctl.rf_wen && !io.ctl.exception && !interrupt_edge
// Register File
val regfile = Mem(32, UInt(conf.xprlen.W))
when (wb_wen && (wb_addr =/= 0.U))
{
regfile(wb_addr) := wb_data
}
//// DebugModule
io.ddpath.rdata := regfile(io.ddpath.addr)
when(io.ddpath.validreq){
regfile(io.ddpath.addr) := io.ddpath.wdata
}
///
val rs1_data = Mux((rs1_addr =/= 0.U), regfile(rs1_addr), 0.asUInt(conf.xprlen.W))
val rs2_data = Mux((rs2_addr =/= 0.U), regfile(rs2_addr), 0.asUInt(conf.xprlen.W))
// immediates
val imm_i = inst(31, 20)
val imm_s = Cat(inst(31, 25), inst(11,7))
val imm_b = Cat(inst(31), inst(7), inst(30,25), inst(11,8))
val imm_u = inst(31, 12)
val imm_j = Cat(inst(31), inst(19,12), inst(20), inst(30,21))
val imm_z = Cat(Fill(27,0.U), inst(19,15))
// sign-extend immediates
val imm_i_sext = Cat(Fill(20,imm_i(11)), imm_i)
val imm_s_sext = Cat(Fill(20,imm_s(11)), imm_s)
val imm_b_sext = Cat(Fill(19,imm_b(11)), imm_b, 0.U)
val imm_u_sext = Cat(imm_u, Fill(12,0.U))
val imm_j_sext = Cat(Fill(11,imm_j(19)), imm_j, 0.U)
val alu_op1 = MuxCase(0.U, Array(
(io.ctl.op1_sel === OP1_RS1) -> rs1_data,
(io.ctl.op1_sel === OP1_IMU) -> imm_u_sext,
(io.ctl.op1_sel === OP1_IMZ) -> imm_z
)).asUInt
val alu_op2 = MuxCase(0.U, Array(
(io.ctl.op2_sel === OP2_RS2) -> rs2_data,
(io.ctl.op2_sel === OP2_PC) -> pc_reg,
(io.ctl.op2_sel === OP2_IMI) -> imm_i_sext,
(io.ctl.op2_sel === OP2_IMS) -> imm_s_sext
)).asUInt
// ALU
val alu_out = Wire(UInt(conf.xprlen.W))
val alu_shamt = alu_op2(4,0).asUInt
alu_out := MuxCase(0.U, Array(
(io.ctl.alu_fun === ALU_ADD) -> (alu_op1 + alu_op2).asUInt,
(io.ctl.alu_fun === ALU_SUB) -> (alu_op1 - alu_op2).asUInt,
(io.ctl.alu_fun === ALU_AND) -> (alu_op1 & alu_op2).asUInt,
(io.ctl.alu_fun === ALU_OR) -> (alu_op1 | alu_op2).asUInt,
(io.ctl.alu_fun === ALU_XOR) -> (alu_op1 ^ alu_op2).asUInt,
(io.ctl.alu_fun === ALU_SLT) -> (alu_op1.asSInt < alu_op2.asSInt).asUInt,
(io.ctl.alu_fun === ALU_SLTU) -> (alu_op1 < alu_op2).asUInt,
(io.ctl.alu_fun === ALU_SLL) -> ((alu_op1 << alu_shamt)(conf.xprlen-1, 0)).asUInt,
(io.ctl.alu_fun === ALU_SRA) -> (alu_op1.asSInt >> alu_shamt).asUInt,
(io.ctl.alu_fun === ALU_SRL) -> (alu_op1 >> alu_shamt).asUInt,
(io.ctl.alu_fun === ALU_COPY1)-> alu_op1
))
// Branch/Jump Target Calculation
br_target := pc_reg + imm_b_sext
jmp_target := pc_reg + imm_j_sext
jump_reg_target := (rs1_data.asUInt + imm_i_sext.asUInt) & ~1.U(conf.xprlen.W)
// Control Status Registers
val csr = Module(new CSRFile(perfEventSets=CSREvents.events))
csr.io := DontCare
csr.io.decode(0).inst := inst
csr.io.rw.addr := inst(CSR_ADDR_MSB,CSR_ADDR_LSB)
csr.io.rw.cmd := io.ctl.csr_cmd
csr.io.rw.wdata := alu_out
csr.io.retire := !(io.ctl.stall || io.ctl.exception)
csr.io.exception := io.ctl.exception
csr.io.pc := pc_reg
exception_target := csr.io.evec
csr.io.tval := MuxCase(0.U, Array(
(io.ctl.exception_cause === Causes.illegal_instruction.U) -> inst,
(io.ctl.exception_cause === Causes.misaligned_fetch.U) -> tval_inst_ma,
(io.ctl.exception_cause === Causes.misaligned_store.U) -> tval_data_ma,
(io.ctl.exception_cause === Causes.misaligned_load.U) -> tval_data_ma,
))
// Interrupt rising edge detector (output trap signal for one cycle on rising edge)
val reg_interrupt_edge = RegInit(false.B)
when (!io.ctl.stall) {
reg_interrupt_edge := csr.io.interrupt
}
interrupt_edge := csr.io.interrupt && !reg_interrupt_edge
io.dat.csr_eret := csr.io.eret
csr.io.interrupts := io.interrupt
csr.io.hartid := io.hartid
io.dat.csr_interrupt := interrupt_edge
csr.io.cause := Mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause)
csr.io.ungated_clock := clock
// Add your own uarch counters here!
csr.io.counters.foreach(_.inc := false.B)
// WB Mux
wb_data := MuxCase(alu_out, Array(
(io.ctl.wb_sel === WB_ALU) -> alu_out,
(io.ctl.wb_sel === WB_MEM) -> io.dmem.resp.bits.data,
(io.ctl.wb_sel === WB_PC4) -> pc_plus4,
(io.ctl.wb_sel === WB_CSR) -> csr.io.rw.rdata
))
// datapath to controlpath outputs
io.dat.inst := inst
io.dat.br_eq := (rs1_data === rs2_data)
io.dat.br_lt := (rs1_data.asSInt < rs2_data.asSInt)
io.dat.br_ltu := (rs1_data.asUInt < rs2_data.asUInt)
// datapath to data memory outputs
io.dmem.req.bits.addr := alu_out
io.dmem.req.bits.data := rs2_data.asUInt
io.dat.mem_address_low := alu_out(2, 0)
tval_data_ma := alu_out
// Printout
// pass output through the spike-dasm binary (found in riscv-tools) to turn
// the DASM(%x) into a disassembly string.
printf("Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n",
csr.io.time(31,0),
csr.io.retire,
pc_reg,
wb_addr,
wb_data,
wb_wen,
rs1_addr,
alu_op1,
rs2_addr,
alu_op2,
inst,
Mux(io.ctl.stall, Str("S"), Str(" ")),
MuxLookup(io.ctl.pc_sel, Str("?"))(Seq(
PC_BR -> Str("B"),
PC_J -> Str("J"),
PC_JR -> Str("R"),
PC_EXC -> Str("E"),
PC_4 -> Str(" "))),
Mux(csr.io.exception, Str("X"), Str(" ")),
inst)
if (PRINT_COMMIT_LOG)
{
when (!io.ctl.stall)
{
// use "sed" to parse out "@@@" from the other printf code above.
val rd = inst(RD_MSB,RD_LSB)
when (io.ctl.rf_wen && rd =/= 0.U)
{
printf("@@@ 0x%x (0x%x) x%d 0x%x\n", pc_reg, inst, rd, Cat(Fill(32,wb_data(31)),wb_data))
}
.otherwise
{
printf("@@@ 0x%x (0x%x)\n", pc_reg, inst)
}
}
}
}
File Events.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) {
def size = events.size
val hits = WireDefault(VecInit(Seq.fill(size)(false.B)))
def check(mask: UInt) = {
hits := events.map(_._2())
gate(mask, hits.asUInt)
}
def dump(): Unit = {
for (((name, _), i) <- events.zipWithIndex)
when (check(1.U << i)) { printf(s"Event $name\n") }
}
def withCovers: Unit = {
events.zipWithIndex.foreach {
case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name)
}
}
}
class EventSets(val eventSets: Seq[EventSet]) {
def maskEventSelector(eventSel: UInt): UInt = {
// allow full associativity between counters and event sets (for now?)
val setMask = (BigInt(1) << eventSetIdBits) - 1
val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits
eventSel & (setMask | maskMask).U
}
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
def evaluate(eventSel: UInt): Bool = {
val (set, mask) = decode(eventSel)
val sets = for (e <- eventSets) yield {
require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}")
e check mask
}
sets(set)
}
def cover() = eventSets.foreach { _.withCovers }
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSetIdBits <= maxEventSetIdBits)
}
class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) {
def evaluate(eventSel: UInt): UInt = {
val (set, mask) = decode(eventSel)
val sets = for ((sets, reducer) <- eventSets) yield {
sets.map { set =>
require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}")
set.check(mask)
}.reduce(reducer)
}
val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U)
zeroPadded(set)
}
def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))
def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size)))
require(eventSetIdBits <= maxEventSetIdBits)
}
| module DatPath( // @[dpath.scala:45:7]
input clock, // @[dpath.scala:45:7]
input reset, // @[dpath.scala:45:7]
output [31:0] io_ddpath_rdata, // @[dpath.scala:47:15]
input io_imem_req_ready, // @[dpath.scala:47:15]
output io_imem_req_valid, // @[dpath.scala:47:15]
output [31:0] io_imem_req_bits_addr, // @[dpath.scala:47:15]
input io_imem_resp_valid, // @[dpath.scala:47:15]
input [31:0] io_imem_resp_bits_data, // @[dpath.scala:47:15]
input io_dmem_req_ready, // @[dpath.scala:47:15]
output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:47:15]
output [31:0] io_dmem_req_bits_data, // @[dpath.scala:47:15]
input io_dmem_resp_valid, // @[dpath.scala:47:15]
input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:47:15]
input io_ctl_stall, // @[dpath.scala:47:15]
input io_ctl_dmiss, // @[dpath.scala:47:15]
input [2:0] io_ctl_pc_sel, // @[dpath.scala:47:15]
input [1:0] io_ctl_op1_sel, // @[dpath.scala:47:15]
input [1:0] io_ctl_op2_sel, // @[dpath.scala:47:15]
input [3:0] io_ctl_alu_fun, // @[dpath.scala:47:15]
input [1:0] io_ctl_wb_sel, // @[dpath.scala:47:15]
input io_ctl_rf_wen, // @[dpath.scala:47:15]
input [2:0] io_ctl_csr_cmd, // @[dpath.scala:47:15]
input io_ctl_exception, // @[dpath.scala:47:15]
input [31:0] io_ctl_exception_cause, // @[dpath.scala:47:15]
input [2:0] io_ctl_pc_sel_no_xept, // @[dpath.scala:47:15]
output [31:0] io_dat_inst, // @[dpath.scala:47:15]
output io_dat_imiss, // @[dpath.scala:47:15]
output io_dat_br_eq, // @[dpath.scala:47:15]
output io_dat_br_lt, // @[dpath.scala:47:15]
output io_dat_br_ltu, // @[dpath.scala:47:15]
output io_dat_csr_eret, // @[dpath.scala:47:15]
output io_dat_csr_interrupt, // @[dpath.scala:47:15]
output io_dat_inst_misaligned, // @[dpath.scala:47:15]
output [2:0] io_dat_mem_address_low, // @[dpath.scala:47:15]
input io_interrupt_debug, // @[dpath.scala:47:15]
input io_interrupt_mtip, // @[dpath.scala:47:15]
input io_interrupt_msip, // @[dpath.scala:47:15]
input io_interrupt_meip, // @[dpath.scala:47:15]
input io_hartid // @[dpath.scala:47:15]
);
wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:194:20]
wire [31:0] _csr_io_time; // @[dpath.scala:194:20]
wire _csr_io_interrupt; // @[dpath.scala:194:20]
wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:194:20]
wire [31:0] _regfile_ext_R0_data; // @[dpath.scala:120:21]
wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:120:21]
wire io_imem_req_ready_0 = io_imem_req_ready; // @[dpath.scala:45:7]
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:45:7]
wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[dpath.scala:45:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:45:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:45:7]
wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:45:7]
wire io_ctl_stall_0 = io_ctl_stall; // @[dpath.scala:45:7]
wire io_ctl_dmiss_0 = io_ctl_dmiss; // @[dpath.scala:45:7]
wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:45:7]
wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:45:7]
wire [1:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:45:7]
wire [3:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:45:7]
wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:45:7]
wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:45:7]
wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:45:7]
wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:45:7]
wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:45:7]
wire [2:0] io_ctl_pc_sel_no_xept_0 = io_ctl_pc_sel_no_xept; // @[dpath.scala:45:7]
wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:45:7]
wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:45:7]
wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:45:7]
wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:45:7]
wire io_hartid_0 = io_hartid; // @[dpath.scala:45:7]
wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:45:7]
wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:45:7]
wire [31:0] io_imem_req_bits_data = 32'h0; // @[dpath.scala:45:7]
wire io_ddpath_validreq = 1'h0; // @[dpath.scala:45:7]
wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:45:7]
wire io_imem_req_bits_fcn = 1'h0; // @[dpath.scala:45:7]
wire io_dmem_req_valid = 1'h0; // @[dpath.scala:45:7]
wire io_dmem_req_bits_fcn = 1'h0; // @[dpath.scala:45:7]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire hits_0 = 1'h0; // @[Events.scala:13:25]
wire [2:0] io_imem_req_bits_typ = 3'h7; // @[dpath.scala:45:7]
wire [2:0] io_dmem_req_bits_typ = 3'h0; // @[dpath.scala:45:7]
wire [31:0] io_reset_vector = 32'h10000; // @[dpath.scala:45:7]
wire [31:0] _jump_reg_target_T_2 = 32'hFFFFFFFE; // @[dpath.scala:191:63]
wire [11:0] _imm_u_sext_T = 12'h0; // @[dpath.scala:150:36]
wire [26:0] _imm_z_T = 27'h0; // @[dpath.scala:144:24]
wire _io_imem_req_valid_T; // @[dpath.scala:96:25]
wire [31:0] alu_out; // @[dpath.scala:170:24]
wire [31:0] rs2_data; // @[dpath.scala:135:22]
wire [31:0] inst; // @[dpath.scala:97:18]
wire _io_dat_imiss_T_1; // @[dpath.scala:85:39]
wire _io_dat_br_eq_T; // @[dpath.scala:242:31]
wire _io_dat_br_lt_T_2; // @[dpath.scala:243:38]
wire _io_dat_br_ltu_T; // @[dpath.scala:244:38]
wire interrupt_edge; // @[dpath.scala:55:29]
wire _io_dat_inst_misaligned_T_13; // @[dpath.scala:103:94]
wire [2:0] _io_dat_mem_address_low_T; // @[dpath.scala:251:37]
wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:45:7]
wire [31:0] io_imem_req_bits_addr_0; // @[dpath.scala:45:7]
wire io_imem_req_valid_0; // @[dpath.scala:45:7]
wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:45:7]
wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:45:7]
wire [31:0] io_dat_inst_0; // @[dpath.scala:45:7]
wire io_dat_imiss_0; // @[dpath.scala:45:7]
wire io_dat_br_eq_0; // @[dpath.scala:45:7]
wire io_dat_br_lt_0; // @[dpath.scala:45:7]
wire io_dat_br_ltu_0; // @[dpath.scala:45:7]
wire io_dat_csr_eret_0; // @[dpath.scala:45:7]
wire io_dat_csr_interrupt_0; // @[dpath.scala:45:7]
wire io_dat_inst_misaligned_0; // @[dpath.scala:45:7]
wire [2:0] io_dat_mem_address_low_0; // @[dpath.scala:45:7]
wire [31:0] tval_data_ma; // @[dpath.scala:51:27]
wire [31:0] _tval_inst_ma_T_5; // @[Mux.scala:126:16]
wire [31:0] tval_inst_ma; // @[dpath.scala:52:27]
wire _interrupt_edge_T_1; // @[dpath.scala:218:39]
assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:45:7, :55:29]
wire [31:0] _pc_next_T_9; // @[Mux.scala:126:16]
wire [31:0] pc_next; // @[dpath.scala:58:31]
wire [31:0] _pc_plus4_T_1; // @[dpath.scala:81:24]
wire [31:0] pc_plus4; // @[dpath.scala:59:31]
wire [31:0] _br_target_T_1; // @[dpath.scala:189:30]
wire [31:0] br_target; // @[dpath.scala:60:31]
wire [31:0] _jmp_target_T_1; // @[dpath.scala:190:30]
wire [31:0] jmp_target; // @[dpath.scala:61:31]
wire [31:0] _jump_reg_target_T_3; // @[dpath.scala:191:61]
wire [31:0] jump_reg_target; // @[dpath.scala:62:31]
wire [31:0] exception_target; // @[dpath.scala:63:31]
wire _pc_next_T = io_ctl_pc_sel_0 == 3'h0; // @[dpath.scala:45:7, :67:34]
wire _pc_next_T_1 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:45:7, :68:34]
wire _pc_next_T_2 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:45:7, :69:34]
wire _pc_next_T_3 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:45:7, :70:34]
wire _pc_next_T_4 = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:45:7, :71:34]
wire [31:0] _pc_next_T_5 = _pc_next_T_4 ? exception_target : pc_plus4; // @[Mux.scala:126:16]
wire [31:0] _pc_next_T_6 = _pc_next_T_3 ? jump_reg_target : _pc_next_T_5; // @[Mux.scala:126:16]
wire [31:0] _pc_next_T_7 = _pc_next_T_2 ? jmp_target : _pc_next_T_6; // @[Mux.scala:126:16]
wire [31:0] _pc_next_T_8 = _pc_next_T_1 ? br_target : _pc_next_T_7; // @[Mux.scala:126:16]
assign _pc_next_T_9 = _pc_next_T ? pc_plus4 : _pc_next_T_8; // @[Mux.scala:126:16]
assign pc_next = _pc_next_T_9; // @[Mux.scala:126:16]
reg [31:0] pc_reg; // @[dpath.scala:74:24]
assign io_imem_req_bits_addr_0 = pc_reg; // @[dpath.scala:45:7, :74:24]
wire [32:0] _GEN = {1'h0, pc_reg}; // @[dpath.scala:74:24, :81:24]
wire [32:0] _pc_plus4_T = _GEN + 33'h4; // @[dpath.scala:81:24]
assign _pc_plus4_T_1 = _pc_plus4_T[31:0]; // @[dpath.scala:81:24]
assign pc_plus4 = _pc_plus4_T_1; // @[dpath.scala:59:31, :81:24]
wire _io_dat_imiss_T = ~io_imem_resp_valid_0; // @[dpath.scala:45:7, :85:42]
assign _io_dat_imiss_T_1 = io_imem_req_valid_0 & _io_dat_imiss_T; // @[dpath.scala:45:7, :85:{39,42}]
assign io_dat_imiss_0 = _io_dat_imiss_T_1; // @[dpath.scala:45:7, :85:39]
reg reg_dmiss; // @[dpath.scala:86:27]
reg [31:0] if_inst_buffer; // @[dpath.scala:87:32]
assign _io_imem_req_valid_T = ~reg_dmiss; // @[dpath.scala:86:27, :96:25]
assign io_imem_req_valid_0 = _io_imem_req_valid_T; // @[dpath.scala:45:7, :96:25]
assign inst = reg_dmiss ? if_inst_buffer : io_imem_resp_bits_data_0; // @[dpath.scala:45:7, :86:27, :87:32, :97:18]
assign io_dat_inst_0 = inst; // @[dpath.scala:45:7, :97:18]
wire [1:0] _io_dat_inst_misaligned_T = br_target[1:0]; // @[dpath.scala:60:31, :102:41]
wire _io_dat_inst_misaligned_T_1 = |_io_dat_inst_misaligned_T; // @[dpath.scala:102:{41,48}]
wire _GEN_0 = io_ctl_pc_sel_no_xept_0 == 3'h1; // @[dpath.scala:45:7, :102:83]
wire _io_dat_inst_misaligned_T_2; // @[dpath.scala:102:83]
assign _io_dat_inst_misaligned_T_2 = _GEN_0; // @[dpath.scala:102:83]
wire _tval_inst_ma_T; // @[dpath.scala:106:45]
assign _tval_inst_ma_T = _GEN_0; // @[dpath.scala:102:83, :106:45]
wire _io_dat_inst_misaligned_T_3 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_2; // @[dpath.scala:102:{48,58,83}]
wire [1:0] _io_dat_inst_misaligned_T_4 = jmp_target[1:0]; // @[dpath.scala:61:31, :103:42]
wire _io_dat_inst_misaligned_T_5 = |_io_dat_inst_misaligned_T_4; // @[dpath.scala:103:{42,49}]
wire _GEN_1 = io_ctl_pc_sel_no_xept_0 == 3'h2; // @[dpath.scala:45:7, :103:83]
wire _io_dat_inst_misaligned_T_6; // @[dpath.scala:103:83]
assign _io_dat_inst_misaligned_T_6 = _GEN_1; // @[dpath.scala:103:83]
wire _tval_inst_ma_T_1; // @[dpath.scala:107:45]
assign _tval_inst_ma_T_1 = _GEN_1; // @[dpath.scala:103:83, :107:45]
wire _io_dat_inst_misaligned_T_7 = _io_dat_inst_misaligned_T_5 & _io_dat_inst_misaligned_T_6; // @[dpath.scala:103:{49,58,83}]
wire _io_dat_inst_misaligned_T_8 = _io_dat_inst_misaligned_T_3 | _io_dat_inst_misaligned_T_7; // @[dpath.scala:102:{58,94}, :103:58]
wire [1:0] _io_dat_inst_misaligned_T_9 = jump_reg_target[1:0]; // @[dpath.scala:62:31, :104:47]
wire _io_dat_inst_misaligned_T_10 = |_io_dat_inst_misaligned_T_9; // @[dpath.scala:104:{47,54}]
wire _GEN_2 = io_ctl_pc_sel_no_xept_0 == 3'h3; // @[dpath.scala:45:7, :104:83]
wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:104:83]
assign _io_dat_inst_misaligned_T_11 = _GEN_2; // @[dpath.scala:104:83]
wire _tval_inst_ma_T_2; // @[dpath.scala:108:45]
assign _tval_inst_ma_T_2 = _GEN_2; // @[dpath.scala:104:83, :108:45]
wire _io_dat_inst_misaligned_T_12 = _io_dat_inst_misaligned_T_10 & _io_dat_inst_misaligned_T_11; // @[dpath.scala:104:{54,58,83}]
assign _io_dat_inst_misaligned_T_13 = _io_dat_inst_misaligned_T_8 | _io_dat_inst_misaligned_T_12; // @[dpath.scala:102:94, :103:94, :104:58]
assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_13; // @[dpath.scala:45:7, :103:94]
wire [31:0] _tval_inst_ma_T_3 = _tval_inst_ma_T_2 ? jump_reg_target : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _tval_inst_ma_T_4 = _tval_inst_ma_T_1 ? jmp_target : _tval_inst_ma_T_3; // @[Mux.scala:126:16]
assign _tval_inst_ma_T_5 = _tval_inst_ma_T ? br_target : _tval_inst_ma_T_4; // @[Mux.scala:126:16]
assign tval_inst_ma = _tval_inst_ma_T_5; // @[Mux.scala:126:16]
wire [4:0] rs1_addr = inst[19:15]; // @[dpath.scala:97:18, :112:23]
wire [4:0] _imm_z_T_1 = inst[19:15]; // @[dpath.scala:97:18, :112:23, :144:38]
wire [4:0] rs2_addr = inst[24:20]; // @[dpath.scala:97:18, :113:23]
wire [4:0] wb_addr = inst[11:7]; // @[dpath.scala:97:18, :114:23]
wire [4:0] _imm_s_T_1 = inst[11:7]; // @[dpath.scala:97:18, :114:23, :140:38]
wire [31:0] _wb_data_T_7; // @[Mux.scala:126:16]
wire [31:0] wb_data; // @[dpath.scala:116:22]
wire _wb_wen_T = ~io_ctl_exception_0; // @[dpath.scala:45:7, :117:34]
wire _wb_wen_T_1 = io_ctl_rf_wen_0 & _wb_wen_T; // @[dpath.scala:45:7, :117:{31,34}]
wire _wb_wen_T_2 = ~interrupt_edge; // @[dpath.scala:55:29, :117:55]
wire wb_wen = _wb_wen_T_1 & _wb_wen_T_2; // @[dpath.scala:117:{31,52,55}]
wire _rs1_data_T = |rs1_addr; // @[dpath.scala:112:23, :134:33]
wire [31:0] rs1_data = _rs1_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:120:21, :134:{22,33}]
wire [31:0] _io_dat_br_lt_T = rs1_data; // @[dpath.scala:134:22, :243:31]
wire _rs2_data_T = |rs2_addr; // @[dpath.scala:113:23, :135:33]
assign rs2_data = _rs2_data_T ? _regfile_ext_R0_data : 32'h0; // @[dpath.scala:120:21, :135:{22,33}]
assign io_dmem_req_bits_data_0 = rs2_data; // @[dpath.scala:45:7, :135:22]
wire [31:0] _io_dat_br_lt_T_1 = rs2_data; // @[dpath.scala:135:22, :243:49]
wire [11:0] imm_i = inst[31:20]; // @[dpath.scala:97:18, :139:20]
wire [11:0] _csr_io_rw_addr_T = inst[31:20]; // @[dpath.scala:97:18, :139:20, :197:28]
wire [6:0] _imm_s_T = inst[31:25]; // @[dpath.scala:97:18, :140:24]
wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:140:{19,24,38}]
wire _imm_b_T = inst[31]; // @[dpath.scala:97:18, :141:24]
wire _imm_j_T = inst[31]; // @[dpath.scala:97:18, :141:24, :143:24]
wire _imm_b_T_1 = inst[7]; // @[dpath.scala:97:18, :141:34]
wire [5:0] _imm_b_T_2 = inst[30:25]; // @[dpath.scala:97:18, :141:43]
wire [3:0] _imm_b_T_3 = inst[11:8]; // @[dpath.scala:97:18, :141:56]
wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:141:{19,43,56}]
wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:141:{19,24,34}]
wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:141:19]
wire [19:0] imm_u = inst[31:12]; // @[dpath.scala:97:18, :142:20]
wire [7:0] _imm_j_T_1 = inst[19:12]; // @[dpath.scala:97:18, :143:34]
wire _imm_j_T_2 = inst[20]; // @[dpath.scala:97:18, :143:47]
wire [9:0] _imm_j_T_3 = inst[30:21]; // @[dpath.scala:97:18, :143:57]
wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:143:{19,47,57}]
wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:143:{19,24,34}]
wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:143:19]
wire [31:0] imm_z = {27'h0, _imm_z_T_1}; // @[dpath.scala:144:{19,38}]
wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:139:20, :147:38]
wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:147:{29,38}]
wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:139:20, :147:{24,29}]
wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:140:19, :148:38]
wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:148:{29,38}]
wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:140:19, :148:{24,29}]
wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:141:19, :149:38]
wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:149:{29,38}]
wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:141:19, :149:{24,29}]
wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:149:24]
wire [31:0] imm_u_sext = {imm_u, 12'h0}; // @[dpath.scala:142:20, :150:24]
wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:143:19, :151:38]
wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:151:{29,38}]
wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:143:19, :151:{24,29}]
wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:151:24]
wire _alu_op1_T = io_ctl_op1_sel_0 == 2'h0; // @[dpath.scala:45:7, :102:48, :155:32]
wire _alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:45:7, :156:32]
wire _alu_op1_T_2 = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:45:7, :157:32]
wire [31:0] _alu_op1_T_3 = _alu_op1_T_2 ? imm_z : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _alu_op1_T_4 = _alu_op1_T_1 ? imm_u_sext : _alu_op1_T_3; // @[Mux.scala:126:16]
wire [31:0] alu_op1 = _alu_op1_T ? rs1_data : _alu_op1_T_4; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_13 = alu_op1; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_22 = alu_op1; // @[Mux.scala:126:16]
wire _alu_op2_T = io_ctl_op2_sel_0 == 2'h0; // @[dpath.scala:45:7, :102:48, :161:32]
wire _alu_op2_T_1 = &io_ctl_op2_sel_0; // @[dpath.scala:45:7, :162:32]
wire _alu_op2_T_2 = io_ctl_op2_sel_0 == 2'h1; // @[dpath.scala:45:7, :163:32]
wire _alu_op2_T_3 = io_ctl_op2_sel_0 == 2'h2; // @[dpath.scala:45:7, :164:32]
wire [31:0] _alu_op2_T_4 = _alu_op2_T_3 ? imm_s_sext : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _alu_op2_T_5 = _alu_op2_T_2 ? imm_i_sext : _alu_op2_T_4; // @[Mux.scala:126:16]
wire [31:0] _alu_op2_T_6 = _alu_op2_T_1 ? pc_reg : _alu_op2_T_5; // @[Mux.scala:126:16]
wire [31:0] alu_op2 = _alu_op2_T ? rs2_data : _alu_op2_T_6; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_14 = alu_op2; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_38; // @[Mux.scala:126:16]
assign io_dmem_req_bits_addr_0 = alu_out; // @[dpath.scala:45:7, :170:24]
assign tval_data_ma = alu_out; // @[dpath.scala:51:27, :170:24]
wire [4:0] alu_shamt = alu_op2[4:0]; // @[Mux.scala:126:16]
wire _alu_out_T = io_ctl_alu_fun_0 == 4'h1; // @[dpath.scala:45:7, :175:35]
wire [32:0] _GEN_3 = {1'h0, alu_op1}; // @[Mux.scala:126:16]
wire [32:0] _GEN_4 = {1'h0, alu_op2}; // @[Mux.scala:126:16]
wire [32:0] _alu_out_T_1 = _GEN_3 + _GEN_4; // @[dpath.scala:175:61]
wire [31:0] _alu_out_T_2 = _alu_out_T_1[31:0]; // @[dpath.scala:175:61]
wire _alu_out_T_3 = io_ctl_alu_fun_0 == 4'h2; // @[dpath.scala:45:7, :176:35]
wire [32:0] _alu_out_T_4 = _GEN_3 - _GEN_4; // @[dpath.scala:175:61, :176:61]
wire [31:0] _alu_out_T_5 = _alu_out_T_4[31:0]; // @[dpath.scala:176:61]
wire _alu_out_T_6 = io_ctl_alu_fun_0 == 4'h6; // @[dpath.scala:45:7, :177:35]
wire [31:0] _alu_out_T_7 = alu_op1 & alu_op2; // @[Mux.scala:126:16]
wire _alu_out_T_8 = io_ctl_alu_fun_0 == 4'h7; // @[dpath.scala:45:7, :178:35]
wire [31:0] _alu_out_T_9 = alu_op1 | alu_op2; // @[Mux.scala:126:16]
wire _alu_out_T_10 = io_ctl_alu_fun_0 == 4'h8; // @[dpath.scala:45:7, :179:35]
wire [31:0] _alu_out_T_11 = alu_op1 ^ alu_op2; // @[Mux.scala:126:16]
wire _alu_out_T_12 = io_ctl_alu_fun_0 == 4'h9; // @[dpath.scala:45:7, :180:35]
wire _alu_out_T_15 = $signed(_alu_out_T_13) < $signed(_alu_out_T_14); // @[dpath.scala:180:{61,68,78}]
wire _alu_out_T_16 = io_ctl_alu_fun_0 == 4'hA; // @[dpath.scala:45:7, :181:35]
wire _alu_out_T_17 = alu_op1 < alu_op2; // @[Mux.scala:126:16]
wire _alu_out_T_18 = io_ctl_alu_fun_0 == 4'h3; // @[dpath.scala:45:7, :182:35]
wire [62:0] _alu_out_T_19 = {31'h0, alu_op1} << alu_shamt; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_20 = _alu_out_T_19[31:0]; // @[dpath.scala:182:{62,75}]
wire _alu_out_T_21 = io_ctl_alu_fun_0 == 4'h5; // @[dpath.scala:45:7, :183:35]
wire [31:0] _GEN_5 = {27'h0, alu_shamt}; // @[dpath.scala:172:27, :183:68]
wire [31:0] _alu_out_T_23 = $signed($signed(_alu_out_T_22) >>> _GEN_5); // @[dpath.scala:183:{61,68}]
wire [31:0] _alu_out_T_24 = _alu_out_T_23; // @[dpath.scala:183:{68,82}]
wire _alu_out_T_25 = io_ctl_alu_fun_0 == 4'h4; // @[dpath.scala:45:7, :184:35]
wire [31:0] _alu_out_T_26 = alu_op1 >> _GEN_5; // @[Mux.scala:126:16]
wire _alu_out_T_27 = io_ctl_alu_fun_0 == 4'hB; // @[dpath.scala:45:7, :185:35]
wire [31:0] _alu_out_T_28 = _alu_out_T_27 ? alu_op1 : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_29 = _alu_out_T_25 ? _alu_out_T_26 : _alu_out_T_28; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_30 = _alu_out_T_21 ? _alu_out_T_24 : _alu_out_T_29; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_31 = _alu_out_T_18 ? _alu_out_T_20 : _alu_out_T_30; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_32 = _alu_out_T_16 ? {31'h0, _alu_out_T_17} : _alu_out_T_31; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_33 = _alu_out_T_12 ? {31'h0, _alu_out_T_15} : _alu_out_T_32; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_34 = _alu_out_T_10 ? _alu_out_T_11 : _alu_out_T_33; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_35 = _alu_out_T_8 ? _alu_out_T_9 : _alu_out_T_34; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_36 = _alu_out_T_6 ? _alu_out_T_7 : _alu_out_T_35; // @[Mux.scala:126:16]
wire [31:0] _alu_out_T_37 = _alu_out_T_3 ? _alu_out_T_5 : _alu_out_T_36; // @[Mux.scala:126:16]
assign _alu_out_T_38 = _alu_out_T ? _alu_out_T_2 : _alu_out_T_37; // @[Mux.scala:126:16]
assign alu_out = _alu_out_T_38; // @[Mux.scala:126:16]
wire [32:0] _br_target_T = _GEN + {1'h0, imm_b_sext}; // @[dpath.scala:81:24, :149:24, :189:30]
assign _br_target_T_1 = _br_target_T[31:0]; // @[dpath.scala:189:30]
assign br_target = _br_target_T_1; // @[dpath.scala:60:31, :189:30]
wire [32:0] _jmp_target_T = _GEN + {1'h0, imm_j_sext}; // @[dpath.scala:81:24, :151:24, :190:30]
assign _jmp_target_T_1 = _jmp_target_T[31:0]; // @[dpath.scala:190:30]
assign jmp_target = _jmp_target_T_1; // @[dpath.scala:61:31, :190:30]
wire [32:0] _jump_reg_target_T = {1'h0, rs1_data} + {1'h0, imm_i_sext}; // @[dpath.scala:134:22, :147:24, :191:40]
wire [31:0] _jump_reg_target_T_1 = _jump_reg_target_T[31:0]; // @[dpath.scala:191:40]
assign _jump_reg_target_T_3 = _jump_reg_target_T_1 & 32'hFFFFFFFE; // @[dpath.scala:191:{40,61}]
assign jump_reg_target = _jump_reg_target_T_3; // @[dpath.scala:62:31, :191:61]
wire _csr_io_retire_T = io_ctl_stall_0 | io_ctl_exception_0; // @[dpath.scala:45:7, :201:39]
wire _csr_io_retire_T_1 = ~_csr_io_retire_T; // @[dpath.scala:201:{24,39}]
wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:45:7, :207:43]
wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:45:7, :208:43]
wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:45:7, :209:43]
wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:45:7, :210:43]
wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? inst : _csr_io_tval_T_6; // @[Mux.scala:126:16]
reg reg_interrupt_edge; // @[dpath.scala:214:36]
wire _interrupt_edge_T = ~reg_interrupt_edge; // @[dpath.scala:214:36, :218:42]
assign _interrupt_edge_T_1 = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:194:20, :218:{39,42}]
assign interrupt_edge = _interrupt_edge_T_1; // @[dpath.scala:55:29, :218:39]
wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:45:7, :194:20, :225:23]
wire _wb_data_T = io_ctl_wb_sel_0 == 2'h0; // @[dpath.scala:45:7, :102:48, :233:34]
wire _wb_data_T_1 = io_ctl_wb_sel_0 == 2'h1; // @[dpath.scala:45:7, :234:34]
wire _wb_data_T_2 = io_ctl_wb_sel_0 == 2'h2; // @[dpath.scala:45:7, :235:34]
wire _wb_data_T_3 = &io_ctl_wb_sel_0; // @[dpath.scala:45:7, :236:34]
wire [31:0] _wb_data_T_4 = _wb_data_T_3 ? _csr_io_rw_rdata : alu_out; // @[Mux.scala:126:16]
wire [31:0] _wb_data_T_5 = _wb_data_T_2 ? pc_plus4 : _wb_data_T_4; // @[Mux.scala:126:16]
wire [31:0] _wb_data_T_6 = _wb_data_T_1 ? io_dmem_resp_bits_data_0 : _wb_data_T_5; // @[Mux.scala:126:16]
assign _wb_data_T_7 = _wb_data_T ? alu_out : _wb_data_T_6; // @[Mux.scala:126:16]
assign wb_data = _wb_data_T_7; // @[Mux.scala:126:16]
assign _io_dat_br_eq_T = rs1_data == rs2_data; // @[dpath.scala:134:22, :135:22, :242:31]
assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:45:7, :242:31]
assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:243:{31,38,49}]
assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:45:7, :243:38]
assign _io_dat_br_ltu_T = rs1_data < rs2_data; // @[dpath.scala:134:22, :135:22, :244:38]
assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:45:7, :244:38]
assign _io_dat_mem_address_low_T = alu_out[2:0]; // @[dpath.scala:170:24, :251:37]
assign io_dat_mem_address_low_0 = _io_dat_mem_address_low_T; // @[dpath.scala:45:7, :251:37] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_519( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_332( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_76 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router_42( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_2_to_14_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_2_to_14_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_12_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_12_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_4_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_4_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire [2:0] _input_unit_2_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_2_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_4_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_4_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_14_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_4( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_2( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_64( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
| module FPUDecoder_5( // @[FPU.scala:55:7]
input clock, // @[FPU.scala:55:7]
input reset, // @[FPU.scala:55:7]
input [31:0] io_inst, // @[FPU.scala:56:14]
output io_sigs_ldst, // @[FPU.scala:56:14]
output io_sigs_wen, // @[FPU.scala:56:14]
output io_sigs_ren1, // @[FPU.scala:56:14]
output io_sigs_ren2, // @[FPU.scala:56:14]
output io_sigs_ren3, // @[FPU.scala:56:14]
output io_sigs_swap12, // @[FPU.scala:56:14]
output io_sigs_swap23, // @[FPU.scala:56:14]
output [1:0] io_sigs_typeTagIn, // @[FPU.scala:56:14]
output [1:0] io_sigs_typeTagOut, // @[FPU.scala:56:14]
output io_sigs_fromint, // @[FPU.scala:56:14]
output io_sigs_toint, // @[FPU.scala:56:14]
output io_sigs_fastpipe, // @[FPU.scala:56:14]
output io_sigs_fma, // @[FPU.scala:56:14]
output io_sigs_div, // @[FPU.scala:56:14]
output io_sigs_sqrt, // @[FPU.scala:56:14]
output io_sigs_wflags, // @[FPU.scala:56:14]
output io_sigs_vec // @[FPU.scala:56:14]
);
wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:55:7]
wire [31:0] decoder_decoded_plaInput = io_inst_0; // @[pla.scala:77:22]
wire decoder_0; // @[Decode.scala:50:77]
wire decoder_1; // @[Decode.scala:50:77]
wire decoder_2; // @[Decode.scala:50:77]
wire decoder_3; // @[Decode.scala:50:77]
wire decoder_4; // @[Decode.scala:50:77]
wire decoder_5; // @[Decode.scala:50:77]
wire decoder_6; // @[Decode.scala:50:77]
wire [1:0] decoder_7; // @[Decode.scala:50:77]
wire [1:0] decoder_8; // @[Decode.scala:50:77]
wire decoder_9; // @[Decode.scala:50:77]
wire decoder_10; // @[Decode.scala:50:77]
wire decoder_11; // @[Decode.scala:50:77]
wire decoder_12; // @[Decode.scala:50:77]
wire decoder_13; // @[Decode.scala:50:77]
wire decoder_14; // @[Decode.scala:50:77]
wire decoder_15; // @[Decode.scala:50:77]
wire decoder_16; // @[Decode.scala:50:77]
wire io_sigs_ldst_0; // @[FPU.scala:55:7]
wire io_sigs_wen_0; // @[FPU.scala:55:7]
wire io_sigs_ren1_0; // @[FPU.scala:55:7]
wire io_sigs_ren2_0; // @[FPU.scala:55:7]
wire io_sigs_ren3_0; // @[FPU.scala:55:7]
wire io_sigs_swap12_0; // @[FPU.scala:55:7]
wire io_sigs_swap23_0; // @[FPU.scala:55:7]
wire [1:0] io_sigs_typeTagIn_0; // @[FPU.scala:55:7]
wire [1:0] io_sigs_typeTagOut_0; // @[FPU.scala:55:7]
wire io_sigs_fromint_0; // @[FPU.scala:55:7]
wire io_sigs_toint_0; // @[FPU.scala:55:7]
wire io_sigs_fastpipe_0; // @[FPU.scala:55:7]
wire io_sigs_fma_0; // @[FPU.scala:55:7]
wire io_sigs_div_0; // @[FPU.scala:55:7]
wire io_sigs_sqrt_0; // @[FPU.scala:55:7]
wire io_sigs_wflags_0; // @[FPU.scala:55:7]
wire io_sigs_vec_0; // @[FPU.scala:55:7]
wire [31:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [18:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [18:0] decoder_decoded; // @[pla.scala:81:23]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_72_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoder_decoded_orMatrixOutputs_T_26 = decoder_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [10:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_16_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_1, decoder_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [10:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_19_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_2, decoder_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_2 = {decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_3 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_55_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_3, decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8_3}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_4 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_18_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_4, decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_4 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_5 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_8_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, decoder_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_6 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_7 = {decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_41_2 = &_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_6 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_7 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_8 = {decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_7 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_8 = {decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_74_2 = &_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_9 = {decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_9 = {decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] _decoder_decoded_andMatrixOutputs_T_9 = {decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_71_2 = &_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_8, decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_10 = {decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_10 = {decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_30_2 = &_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_11 = {decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_11 = {decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_66_2 = &_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_12 = {decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] _decoder_decoded_andMatrixOutputs_T_12 = {decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_75_2 = &_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_13 = {decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_37_2 = &_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_14 = {decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [8:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_47_2 = &_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_14, decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_14 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [9:0] _decoder_decoded_andMatrixOutputs_T_15 = {decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_60_2 = &_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_15, decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_16 = {decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [9:0] _decoder_decoded_andMatrixOutputs_T_16 = {decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_15_2 = &_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_17 = {decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_17 = {decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_29_2 = &_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_15 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_17 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_18 = {decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_17 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [11:0] _decoder_decoded_andMatrixOutputs_T_18 = {decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_39_2 = &_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_16 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_18 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_19 = {decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_18 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [12:0] _decoder_decoded_andMatrixOutputs_T_19 = {decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_69_2 = &_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_17 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_19 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_20 = {decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_19 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [12:0] _decoder_decoded_andMatrixOutputs_T_20 = {decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_42_2 = &_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_18 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_20 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_20 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_21 = {decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_49_2 = &_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_19 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_21 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_22 = {decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_21 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_22 = {decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_24_2 = &_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_20 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_20, decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_22 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_23 = {decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_22 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_23 = {decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_9_2 = &_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_21 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_15, decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_23 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_24 = {decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_23 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_24 = {decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_57_2 = &_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_22 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_24 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_25 = {decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_24 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_25 = {decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_50_2 = &_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_23 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_25 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_26 = {decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_25 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_26 = {decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_21_2 = &_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_24 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_26 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_27 = {decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_26 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_27 = {decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_61_2 = &_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_25 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_19, decoder_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_27 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_28 = {decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_27 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [13:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_44_2 = &_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_26 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_28 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_29 = {decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_29 = {decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_43_2 = &_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_27 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_30 = {decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_29 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_30 = {decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_73_2 = &_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_28 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_31 = {decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_30 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_23_2 = &_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_29 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_31 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_32 = {decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_38_2 = &_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_30 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_32 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_10_2 = &_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_31 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_33 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_34 = {decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_40_2 = &_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_32 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_34 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_35 = {decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_35 = {decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_33_2 = &_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_33 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_36 = {decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_35 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_36 = {decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_67_2 = &_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_34 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, decoder_decoded_andMatrixOutputs_andMatrixInput_12_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_28, decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_37 = {decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_36, decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_36 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_37 = {decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_59_2 = &_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_35 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_37 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_38 = {decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, decoder_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_38 = {decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_36 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_12_20}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_39 = {decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_34, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_38 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_39 = {decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_3, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_37 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_40 = {decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_39 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_40 = {decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_14, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_38 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, decoder_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_41 = {decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_38, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_41 = {decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_27_2 = &_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_5, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_39 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_42 = {decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_42 = {decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_53_2 = &_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_40 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_30, decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_43 = {decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_40, decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_42, decoder_decoded_andMatrixOutputs_andMatrixInput_6_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_42 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_43, decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_43 = {decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_70_2 = &_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_41 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_44 = {decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_43 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_44 = {decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_32_2 = &_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_42 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_24, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_44 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_45 = {decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_44, decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_44 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_45 = {decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_13_2 = &_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_25, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_43 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_45 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_46 = {decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_45 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_46 = {decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_52_2 = &_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_44 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_46 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_47 = {decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_46 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_47 = {decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_64_2 = &_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_45 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_47 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_48 = {decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_47, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_47 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_48 = {decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_11_2 = &_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_46 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_40, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_48 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_49 = {decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_48 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_49 = {decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_26_2 = &_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_23, decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_47 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_49 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [17:0] _decoder_decoded_andMatrixOutputs_T_50 = {decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_58_2 = &_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_48 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_32}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_50 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_51 = {decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_50 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_51 = {decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_76_2 = &_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_49 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_51 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_lo_52 = {decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_47, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, decoder_decoded_andMatrixOutputs_andMatrixInput_6_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [18:0] _decoder_decoded_andMatrixOutputs_T_52 = {decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_51_2 = &_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_34, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_50 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_52 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_53 = {decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_51 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_53 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_54 = {decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_54 = {decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_31_2 = &_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_52 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_55 = {decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_68_2 = &_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_53 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_56 = {decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_56 = {decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_62_2 = &_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_57 = {decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_57 = {decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_65_2 = &_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [6:0] decoder_decoded_andMatrixOutputs_lo_58 = {decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [14:0] _decoder_decoded_andMatrixOutputs_T_58 = {decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_45_2 = &_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_59 = {decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_58, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_59 = {decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_25_2 = &_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_60 = {decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_60 = {decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_42, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_61 = {decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_61 = {decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_62 = {decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_62 = {decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_48_2 = &_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_63 = {decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_63 = {decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_46_2 = &_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_64 = {decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [15:0] _decoder_decoded_andMatrixOutputs_T_64 = {decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_63_2 = &_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_65 = {decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_65 = {decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_12_2 = &_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] decoder_decoded_andMatrixOutputs_lo_66 = {decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, decoder_decoded_andMatrixOutputs_andMatrixInput_6_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [8:0] decoder_decoded_andMatrixOutputs_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [16:0] _decoder_decoded_andMatrixOutputs_T_66 = {decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_56_2 = &_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_64 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_67 = {decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_66 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [19:0] _decoder_decoded_andMatrixOutputs_T_67 = {decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_35_2 = &_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_1, decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_65 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_68 = {decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_67 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_68, decoder_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_68 = {decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_34_2 = &_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_66 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_68 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_69 = {decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_68 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [19:0] _decoder_decoded_andMatrixOutputs_T_69 = {decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_20_2 = &_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_67 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_69 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_70 = {decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_69 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_70 = {decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_7_2 = &_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_68 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_70 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_lo_71 = {decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_70 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [21:0] _decoder_decoded_andMatrixOutputs_T_71 = {decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_17_2 = &_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_69 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_45, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_71 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_72 = {decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_71, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_71 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_72 = {decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_36_2 = &_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_6, decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_70 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_46, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_72 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_73 = {decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_72 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_73, decoder_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_73 = {decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_22_2 = &_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_7, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_25, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_71 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_47, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_73 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_74 = {decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_73 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_74 = {decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_14_2 = &_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_8, decoder_decoded_andMatrixOutputs_andMatrixInput_20_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_72 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_74 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [9:0] decoder_decoded_andMatrixOutputs_lo_75 = {decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, decoder_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_74 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [20:0] _decoder_decoded_andMatrixOutputs_T_75 = {decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_28_2 = &_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_73 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_75 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_lo_76 = {decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_75 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [10:0] decoder_decoded_andMatrixOutputs_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [21:0] _decoder_decoded_andMatrixOutputs_T_76 = {decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_54_2 = &_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_2 = _GEN; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN; // @[pla.scala:114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo = {decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_33_2, decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_0 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_0; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [16:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_5 = |_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_1 = {decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_1 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_22 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _decoder_decoded_orMatrixOutputs_T_6 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_7 = |_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_2 = {decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_2 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [7:0] _decoder_decoded_orMatrixOutputs_T_8 = {decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_9 = |_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_3 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_62_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_3 = {decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_4 = {decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:19]
assign _decoder_decoded_orMatrixOutputs_T_24 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_5; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] _decoder_decoded_orMatrixOutputs_T_10 = {decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_11 = |_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_5 = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_4 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] _GEN_6 = {decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [3:0] _decoder_decoded_orMatrixOutputs_T_12 = {decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_13 = |_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_3 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_7 = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = _GEN_7; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_14 = {decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_15 = |_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_36_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] _GEN_8 = {decoder_decoded_andMatrixOutputs_38_2, decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_2; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_4; // @[pla.scala:114:19]
assign decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [11:0] _decoder_decoded_orMatrixOutputs_T_16 = {decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_17 = |_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_21_2, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_18 = {decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_19 = |_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_6 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_lo_8 = {decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [6:0] decoder_decoded_orMatrixOutputs_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [12:0] _decoder_decoded_orMatrixOutputs_T_20 = {decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_21 = |_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_23 = |_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}]
wire _decoder_decoded_orMatrixOutputs_T_25 = |_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] decoder_decoded_orMatrixOutputs_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [10:0] _decoder_decoded_orMatrixOutputs_T_27 = {decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_28 = |_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_8 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_3_2, decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_10 = {decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [18:0] _decoder_decoded_orMatrixOutputs_T_29 = {decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_30 = |_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_27_2, decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [18:0] _decoder_decoded_orMatrixOutputs_T_31 = {decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_32 = |_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] _decoder_decoded_orMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_34 = |_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_1, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {_decoder_decoded_orMatrixOutputs_T_5, _decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_15, _decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:102:36]
wire [8:0] decoder_decoded_orMatrixOutputs_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_19, _decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_25, _decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_10 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:102:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {_decoder_decoded_orMatrixOutputs_T_34, _decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, _decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:102:36]
wire [9:0] decoder_decoded_orMatrixOutputs_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:102:36]
wire [18:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:102:36]
wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_16 = decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_17 = decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_18 = decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_8, _decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_10, _decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_18, _decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoder_0 = decoder_decoded[18]; // @[pla.scala:81:23]
assign io_sigs_ldst_0 = decoder_0; // @[FPU.scala:55:7]
assign decoder_1 = decoder_decoded[17]; // @[pla.scala:81:23]
assign io_sigs_wen_0 = decoder_1; // @[FPU.scala:55:7]
assign decoder_2 = decoder_decoded[16]; // @[pla.scala:81:23]
assign io_sigs_ren1_0 = decoder_2; // @[FPU.scala:55:7]
assign decoder_3 = decoder_decoded[15]; // @[pla.scala:81:23]
assign io_sigs_ren2_0 = decoder_3; // @[FPU.scala:55:7]
assign decoder_4 = decoder_decoded[14]; // @[pla.scala:81:23]
assign io_sigs_ren3_0 = decoder_4; // @[FPU.scala:55:7]
assign decoder_5 = decoder_decoded[13]; // @[pla.scala:81:23]
assign io_sigs_swap12_0 = decoder_5; // @[FPU.scala:55:7]
assign decoder_6 = decoder_decoded[12]; // @[pla.scala:81:23]
assign io_sigs_swap23_0 = decoder_6; // @[FPU.scala:55:7]
assign decoder_7 = decoder_decoded[11:10]; // @[pla.scala:81:23]
assign io_sigs_typeTagIn_0 = decoder_7; // @[FPU.scala:55:7]
assign decoder_8 = decoder_decoded[9:8]; // @[pla.scala:81:23]
assign io_sigs_typeTagOut_0 = decoder_8; // @[FPU.scala:55:7]
assign decoder_9 = decoder_decoded[7]; // @[pla.scala:81:23]
assign io_sigs_fromint_0 = decoder_9; // @[FPU.scala:55:7]
assign decoder_10 = decoder_decoded[6]; // @[pla.scala:81:23]
assign io_sigs_toint_0 = decoder_10; // @[FPU.scala:55:7]
assign decoder_11 = decoder_decoded[5]; // @[pla.scala:81:23]
assign io_sigs_fastpipe_0 = decoder_11; // @[FPU.scala:55:7]
assign decoder_12 = decoder_decoded[4]; // @[pla.scala:81:23]
assign io_sigs_fma_0 = decoder_12; // @[FPU.scala:55:7]
assign decoder_13 = decoder_decoded[3]; // @[pla.scala:81:23]
assign io_sigs_div_0 = decoder_13; // @[FPU.scala:55:7]
assign decoder_14 = decoder_decoded[2]; // @[pla.scala:81:23]
assign io_sigs_sqrt_0 = decoder_14; // @[FPU.scala:55:7]
assign decoder_15 = decoder_decoded[1]; // @[pla.scala:81:23]
assign io_sigs_wflags_0 = decoder_15; // @[FPU.scala:55:7]
assign decoder_16 = decoder_decoded[0]; // @[pla.scala:81:23]
assign io_sigs_vec_0 = decoder_16; // @[FPU.scala:55:7]
assign io_sigs_ldst = io_sigs_ldst_0; // @[FPU.scala:55:7]
assign io_sigs_wen = io_sigs_wen_0; // @[FPU.scala:55:7]
assign io_sigs_ren1 = io_sigs_ren1_0; // @[FPU.scala:55:7]
assign io_sigs_ren2 = io_sigs_ren2_0; // @[FPU.scala:55:7]
assign io_sigs_ren3 = io_sigs_ren3_0; // @[FPU.scala:55:7]
assign io_sigs_swap12 = io_sigs_swap12_0; // @[FPU.scala:55:7]
assign io_sigs_swap23 = io_sigs_swap23_0; // @[FPU.scala:55:7]
assign io_sigs_typeTagIn = io_sigs_typeTagIn_0; // @[FPU.scala:55:7]
assign io_sigs_typeTagOut = io_sigs_typeTagOut_0; // @[FPU.scala:55:7]
assign io_sigs_fromint = io_sigs_fromint_0; // @[FPU.scala:55:7]
assign io_sigs_toint = io_sigs_toint_0; // @[FPU.scala:55:7]
assign io_sigs_fastpipe = io_sigs_fastpipe_0; // @[FPU.scala:55:7]
assign io_sigs_fma = io_sigs_fma_0; // @[FPU.scala:55:7]
assign io_sigs_div = io_sigs_div_0; // @[FPU.scala:55:7]
assign io_sigs_sqrt = io_sigs_sqrt_0; // @[FPU.scala:55:7]
assign io_sigs_wflags = io_sigs_wflags_0; // @[FPU.scala:55:7]
assign io_sigs_vec = io_sigs_vec_0; // @[FPU.scala:55:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File SwitchAllocator.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])
(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val tail = Bool()
}
class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams))))
val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val chosen_oh = Vec(outN, Output(UInt(inN.W)))
})
val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) }
val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_))
val mask = RegInit(0.U(inN.W))
val choices = Wire(Vec(outN, UInt(inN.W)))
var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask))
for (i <- 0 until outN) {
choices(i) := sel | (sel >> inN)
sel = PriorityEncoderOH(unassigned & ~choices(i))
}
io.in.foreach(_.ready := false.B)
var chosens = 0.U(inN.W)
val in_tails = Cat(io.in.map(_.bits.tail).reverse)
for (i <- 0 until outN) {
val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse)
val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i))
io.chosen_oh(i) := chosen
io.out(i).valid := (in_valids & chosen).orR
io.out(i).bits := Mux1H(chosen, io.in.map(_.bits))
for (j <- 0 until inN) {
when (chosen(j) && io.out(i).ready) {
io.in(j).ready := true.B
}
}
chosens = chosens | chosen
when (io.out(i).fire) {
lock(i) := chosen & ~in_tails
}
}
when (io.out(0).fire) {
mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_)
} .otherwise {
mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W))
}
}
class SwitchAllocator(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map(u =>
Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams))))))
val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))})
val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) })
})
val nInputChannels = allInParams.map(_.nVirtualChannels).sum
val arbs = allOutParams.map { oP => Module(new SwitchArbiter(
allInParams.map(_.destSpeedup).reduce(_+_),
oP.srcSpeedup,
outParams,
egressParams
))}
arbs.foreach(_.io.out.foreach(_.ready := true.B))
var idx = 0
io.req.foreach(_.foreach { o =>
val fires = Wire(Vec(arbs.size, Bool()))
arbs.zipWithIndex.foreach { case (a,i) =>
a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_)
a.io.in(idx).bits := o.bits
fires(i) := a.io.in(idx).fire
}
o.ready := fires.reduce(_||_)
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
idx = 0
for (m <- 0 until nAllInputs) {
for (n <- 0 until allInParams(m).destSpeedup) {
io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid
idx += 1
}
}
}
}
io.credit_alloc.foreach(_.foreach(_.alloc := false.B))
io.credit_alloc.foreach(_.foreach(_.tail := false.B))
(arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) =>
for (j <- 0 until i.size) {
for (k <- 0 until a.io.out.size) {
when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) {
i(j).alloc := true.B
i(j).tail := a.io.out(k).bits.tail
}
}
}
}
}
| module SwitchArbiter_30( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_1_ready, // @[SwitchAllocator.scala:18:14]
input io_in_1_valid, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}]
reg [1:0] mask; // @[SwitchAllocator.scala:27:21]
wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71]
wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24]
wire [1:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[1:0] | sel[3:2]; // @[Mux.scala:50:70]
wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38]
mask <= 2'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_io_out_0_valid_T) ? {chosen[1], |chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_34 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_124( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_250( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File rename-stage.scala:
//******************************************************************************
// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Datapath: Rename Logic
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Supports 1-cycle and 2-cycle latencies. (aka, passthrough versus registers between ren1 and ren2).
// - ren1: read the map tables and allocate a new physical register from the freelist.
// - ren2: read the busy table for the physical operands.
//
// Ren1 data is provided as an output to be fed directly into the ROB.
package boom.v4.exu
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
abstract class AbstractRenameStage(
plWidth: Int,
numWbPorts: Int)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val ren_stalls = Output(Vec(plWidth, Bool()))
val kill = Input(Bool())
val dec_fire = Input(Vec(plWidth, Bool())) // will commit state updates
val dec_uops = Input(Vec(plWidth, new MicroOp()))
// physical specifiers available AND busy/ready status available.
val ren2_mask = Vec(plWidth, Output(Bool())) // mask of valid instructions
val ren2_uops = Vec(plWidth, Output(new MicroOp()))
// branch resolution (execute)
val brupdate = Input(new BrUpdateInfo())
val dis_fire = Input(Vec(coreWidth, Bool()))
val dis_ready = Input(Bool())
// wakeup ports
val wakeups = Flipped(Vec(numWbPorts, Valid(new Wakeup)))
val child_rebusys = Input(UInt(aluWidth.W))
// commit stage
val com_valids = Input(Vec(plWidth, Bool()))
val com_uops = Input(Vec(plWidth, new MicroOp()))
val rollback = Input(Bool())
val debug_rob_empty = Input(Bool())
})
def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = { uop }
//-------------------------------------------------------------
// Pipeline State & Wires
// Stage 1
val ren1_fire = Wire(Vec(plWidth, Bool()))
val ren1_uops = Wire(Vec(plWidth, new MicroOp))
// Stage 2
val ren2_fire = io.dis_fire
val ren2_ready = io.dis_ready
val ren2_valids = Wire(Vec(plWidth, Bool()))
val ren2_uops = Wire(Vec(plWidth, new MicroOp))
val ren2_alloc_reqs = Wire(Vec(plWidth, Bool()))
val ren2_alloc_fire = (ren2_fire zip ren2_alloc_reqs).map({case (f, r) => f && r})
val ren2_br_tags = Wire(Vec(plWidth+1, Valid(UInt(brTagSz.W))))
//-------------------------------------------------------------
// pipeline registers
for (w <- 0 until plWidth) {
ren1_fire(w) := io.dec_fire(w)
ren1_uops(w) := io.dec_uops(w)
}
ren2_br_tags(0).valid := false.B
ren2_br_tags(0).bits := DontCare
for (w <- 0 until plWidth) {
val r_valid = RegInit(false.B)
val r_uop = Reg(new MicroOp)
val next_uop = Wire(new MicroOp)
next_uop := r_uop
when (io.kill) {
r_valid := false.B
} .elsewhen (ren2_ready) {
r_valid := ren1_fire(w)
next_uop := ren1_uops(w)
} .otherwise {
r_valid := r_valid && !ren2_fire(w) // clear bit if uop gets dispatched
next_uop := r_uop
}
assert(!(r_valid && r_uop.lrs1_rtype === RT_FIX && r_uop.lrs1 === 0.U))
assert(!(r_valid && r_uop.lrs2_rtype === RT_FIX && r_uop.lrs2 === 0.U))
r_uop := GetNewUopAndBrMask(BypassAllocations(next_uop, ren2_uops, ren2_alloc_fire), io.brupdate)
ren2_valids(w) := r_valid
ren2_uops(w) := r_uop
ren2_br_tags(w+1).valid := ren2_fire(w) && ren2_uops(w).allocate_brtag
ren2_br_tags(w+1).bits := ren2_uops(w).br_tag
}
//-------------------------------------------------------------
// Outputs
io.ren2_mask := ren2_valids
}
/**
* Rename stage that connets the map table, free list, and busy table.
* Can be used in both the FP pipeline and the normal execute pipeline.
*
* @param plWidth pipeline width
* @param numWbPorts number of int writeback ports
* @param numWbPorts number of FP writeback ports
*/
class RenameStage(
plWidth: Int,
numPhysRegs: Int,
numWbPorts: Int,
float: Boolean)
(implicit p: Parameters) extends AbstractRenameStage(plWidth, numWbPorts)(p)
{
val int = !float
val pregSz = log2Ceil(numPhysRegs)
val rtype = if (float) RT_FLT else RT_FIX
//-------------------------------------------------------------
// Helper Functions
override def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {
if (older_uops.size == 0) {
uop
} else {
val bypassed_uop = Wire(new MicroOp)
bypassed_uop := uop
val bypass_hits_rs1 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs1 }
val bypass_hits_rs2 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs2 }
val bypass_hits_rs3 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs3 }
val bypass_hits_dst = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.ldst }
val bypass_sel_rs1 = PriorityEncoderOH(bypass_hits_rs1.reverse).reverse
val bypass_sel_rs2 = PriorityEncoderOH(bypass_hits_rs2.reverse).reverse
val bypass_sel_rs3 = PriorityEncoderOH(bypass_hits_rs3.reverse).reverse
val bypass_sel_dst = PriorityEncoderOH(bypass_hits_dst.reverse).reverse
val do_bypass_rs1 = bypass_hits_rs1.reduce(_||_)
val do_bypass_rs2 = bypass_hits_rs2.reduce(_||_)
val do_bypass_rs3 = bypass_hits_rs3.reduce(_||_)
val do_bypass_dst = bypass_hits_dst.reduce(_||_)
val bypass_pdsts = older_uops.map(_.pdst)
when (do_bypass_rs1) { bypassed_uop.prs1 := Mux1H(bypass_sel_rs1, bypass_pdsts) }
when (do_bypass_rs2) { bypassed_uop.prs2 := Mux1H(bypass_sel_rs2, bypass_pdsts) }
when (do_bypass_rs3) { bypassed_uop.prs3 := Mux1H(bypass_sel_rs3, bypass_pdsts) }
when (do_bypass_dst) { bypassed_uop.stale_pdst := Mux1H(bypass_sel_dst, bypass_pdsts) }
bypassed_uop.prs1_busy := uop.prs1_busy || do_bypass_rs1
bypassed_uop.prs2_busy := uop.prs2_busy || do_bypass_rs2
bypassed_uop.prs3_busy := uop.prs3_busy || do_bypass_rs3
if (int) {
bypassed_uop.prs3 := DontCare
bypassed_uop.prs3_busy := false.B
}
bypassed_uop
}
}
//-------------------------------------------------------------
// Rename Structures
val maptable = Module(new RenameMapTable(
plWidth,
32,
numPhysRegs,
false,
float))
val freelist = Module(
if (
(enableColumnALUWrites && int) ||
(enableBankedFPFreelist && float)
) {
new BankedRenameFreeList(
plWidth,
numPhysRegs
)
} else {
new RenameFreeList(
plWidth,
plWidth,
numPhysRegs,
false
)
}
)
val busytable = Module(new RenameBusyTable(
plWidth,
numPhysRegs,
numWbPorts,
float))
// Commit/Rollback
val com_valids = Wire(Vec(plWidth, Bool()))
for (w <- 0 until plWidth) {
ren2_alloc_reqs(w) := ren2_uops(w).dst_rtype === rtype && ren2_valids(w)
com_valids(w) := io.com_uops(w).dst_rtype === rtype && io.com_valids(w)
}
//-------------------------------------------------------------
// Rename Table
// Maptable inputs.
val map_reqs = Wire(Vec(plWidth, new MapReq(lregSz)))
val remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))
val com_remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))
// Generate maptable requests.
for ((((ren1,ren2),com),w) <- (ren1_uops zip ren2_uops zip io.com_uops).zipWithIndex) {
map_reqs(w).lrs1 := ren1.lrs1
map_reqs(w).lrs2 := ren1.lrs2
map_reqs(w).lrs3 := ren1.lrs3
map_reqs(w).ldst := ren1.ldst
remap_reqs(w).valid := ren2_alloc_fire(w)
remap_reqs(w).ldst := ren2.ldst
remap_reqs(w).pdst := ren2.pdst
com_remap_reqs(w).valid := com_valids(w)
com_remap_reqs(w).ldst := io.com_uops(w).ldst
com_remap_reqs(w).pdst := io.com_uops(w).pdst
}
// Hook up inputs.
maptable.io.map_reqs := map_reqs
maptable.io.remap_reqs := remap_reqs
maptable.io.ren_br_tags := ren2_br_tags
maptable.io.brupdate := io.brupdate
maptable.io.rollback := io.rollback
maptable.io.com_remap_reqs := com_remap_reqs
// Maptable outputs.
for ((uop, w) <- ren1_uops.zipWithIndex) {
val mappings = maptable.io.map_resps(w)
uop.prs1 := mappings.prs1
uop.prs2 := mappings.prs2
uop.prs3 := mappings.prs3 // only FP has 3rd operand
uop.stale_pdst := mappings.stale_pdst
}
//-------------------------------------------------------------
// Free List
// Freelist inputs.
freelist.io.initial_allocation := Cat(~(0.U((numPhysRegs-32).W)), 0.U(32.W))
freelist.io.reqs := ren2_alloc_fire
for (w <- 0 until plWidth) {
freelist.io.despec(w).valid := com_valids(w)
freelist.io.despec(w).bits := io.com_uops(w).pdst
freelist.io.dealloc(w).valid := com_valids(w)
freelist.io.dealloc(w).bits := io.com_uops(w).stale_pdst
}
freelist.io.ren_br_tags := ren2_br_tags
freelist.io.brupdate := io.brupdate
freelist.io.rollback := io.rollback
// Freelist outputs.
for ((uop, w) <- ren2_uops.zipWithIndex) {
val preg = freelist.io.alloc_pregs(w).bits
uop.pdst := preg
uop.dis_col_sel := (if (coreWidth > 1) UIntToOH(preg(log2Ceil(coreWidth)-1,0)) else 0.U(1.W))
}
assert (!RegNext(io.rollback) || PopCount(freelist.io.debug_freelist) === (numPhysRegs - 32).U,
"[freelist] Leaking physical registers.")
//-------------------------------------------------------------
// Busy Table
busytable.io.ren_uops := ren2_uops // expects pdst to be set up.
busytable.io.rebusy_reqs := ren2_alloc_fire
busytable.io.wakeups := io.wakeups
busytable.io.child_rebusys := io.child_rebusys
assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),
"[rename] Wakeup has wrong rtype.")
for ((uop, w) <- ren2_uops.zipWithIndex) {
val busy = busytable.io.busy_resps(w)
uop.prs1_busy := uop.lrs1_rtype === rtype && busy.prs1_busy
uop.prs2_busy := uop.lrs2_rtype === rtype && busy.prs2_busy
uop.prs3_busy := uop.frs3_en && busy.prs3_busy
val valid = ren2_valids(w)
assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1_rtype === RT_FIX && uop.lrs1 === 0.U), "[rename] x0 is busy??")
assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2_rtype === RT_FIX && uop.lrs2 === 0.U), "[rename] x0 is busy??")
}
//-------------------------------------------------------------
// Outputs
for (w <- 0 until plWidth) {
val can_allocate = freelist.io.alloc_pregs(w).valid
// Push back against Decode stage if Rename1 can't proceed.
io.ren_stalls(w) := (ren2_uops(w).dst_rtype === rtype) && !can_allocate
val bypassed_uop = Wire(new MicroOp)
bypassed_uop := BypassAllocations(ren2_uops(w), ren2_uops.take(w), ren2_alloc_reqs.take(w))
io.ren2_uops(w) := GetNewUopAndBrMask(bypassed_uop, io.brupdate)
}
}
class PredRenameStage(
plWidth: Int,
numWbPorts: Int)
(implicit p: Parameters) extends AbstractRenameStage(plWidth, numWbPorts)(p)
{
override def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {
if (older_uops.size == 0) {
uop
} else {
val bypassed_uop = Wire(new MicroOp)
bypassed_uop := uop
val bypass_sel = PriorityEncoderOH(alloc_reqs.reverse).reverse
val do_bypass = alloc_reqs.reduce(_||_)
val bypass_pdsts = older_uops.map(_.ftq_idx)
when (do_bypass) { bypassed_uop.ppred := Mux1H(bypass_sel, bypass_pdsts) }
bypassed_uop.ppred_busy := (uop.ppred_busy || do_bypass) && uop.is_sfb_shadow
bypassed_uop
}
}
val ren1_current_ftq_idx = Reg(UInt(log2Ceil(ftqSz).W))
var next_ftq_idx = ren1_current_ftq_idx
for (w <- 0 until plWidth) {
ren1_uops(w).ppred := next_ftq_idx
when (ren1_uops(w).is_sfb_br) {
ren1_uops(w).pdst := ren1_uops(w).ftq_idx
}
next_ftq_idx = Mux(ren1_uops(w).is_sfb_br && ren1_fire(w), ren1_uops(w).ftq_idx, next_ftq_idx)
}
ren1_current_ftq_idx := next_ftq_idx
val busy_table = RegInit(VecInit(0.U(ftqSz.W).asBools))
val to_busy = WireInit(VecInit(0.U(ftqSz.W).asBools))
val unbusy = WireInit(VecInit(0.U(ftqSz.W).asBools))
for (w <- 0 until plWidth) {
ren2_alloc_reqs(w) := ren2_uops(w).is_sfb_br && ren2_valids(w)
io.ren2_uops(w) := BypassAllocations(ren2_uops(w), ren2_uops.take(w), ren2_alloc_reqs.take(w))
io.ren_stalls(w) := false.B
when (ren2_alloc_reqs(w) && ren2_fire(w)) {
to_busy(ren2_uops(w).ftq_idx) := true.B
}
ren2_uops(w).ppred_busy := ren2_uops(w).is_sfb_shadow && busy_table(ren2_uops(w).ppred) && !unbusy(ren2_uops(w).ppred)
}
for (w <- 0 until numWbPorts) {
when (io.wakeups(w).valid) {
unbusy(io.wakeups(w).bits.uop.pdst) := true.B
}
}
busy_table := ((busy_table.asUInt | to_busy.asUInt) & ~unbusy.asUInt).asBools
}
class ImmRenameStage(plWidth: Int, numWbPorts: Int)(implicit p: Parameters) extends AbstractRenameStage(plWidth, numWbPorts)(p)
{
val freelist = Module(new RenameFreeList(
plWidth,
numWbPorts,
numImmPhysRegs,
true
))
for (w <- 0 until plWidth) {
val imm = ImmGen(ren2_uops(w).imm_packed, ren2_uops(w).imm_sel)
val imm_hi = imm >> (immPregSz-1)
val imm_lo = imm(immPregSz-1, 0)
val short_imm = imm_hi === 0.U || ~imm_hi === 0.U
ren2_alloc_reqs(w) := ren2_uops(w).imm_rename
assert(!ren2_alloc_fire(w) || ren2_uops(w).iq_type(IQ_ALU) || ren2_uops(w).iq_type(IQ_MEM) || ren2_uops(w).iq_type(IQ_UNQ))
val can_allocate = freelist.io.alloc_pregs(w).valid
// Push back against Decode stage if Rename1 can't proceed.
io.ren_stalls(w) := ren2_uops(w).imm_rename && !can_allocate
io.ren2_uops(w) := GetNewUopAndBrMask(ren2_uops(w), io.brupdate)
when (ren2_uops(w).imm_rename) {
io.ren2_uops(w).pimm := freelist.io.alloc_pregs(w).bits
}
}
freelist.io.initial_allocation := ~(0.U(numImmPhysRegs.W))
freelist.io.reqs := ren2_alloc_fire
for (w <- 0 until numWbPorts) {
freelist.io.despec(w).valid := false.B
freelist.io.despec(w).bits := DontCare
freelist.io.dealloc(w).valid := io.wakeups(w).valid
freelist.io.dealloc(w).bits := io.wakeups(w).bits.uop.pimm
}
freelist.io.ren_br_tags := ren2_br_tags
freelist.io.brupdate := io.brupdate
freelist.io.rollback := io.rollback
assert (!RegNext(io.rollback) || PopCount(freelist.io.debug_freelist) === (numImmPhysRegs).U,
"[freelist] Leaking physical registers.")
}
| module ImmRenameStage( // @[rename-stage.scala:414:7]
input clock, // @[rename-stage.scala:414:7]
input reset, // @[rename-stage.scala:414:7]
output io_ren_stalls_0, // @[rename-stage.scala:33:14]
output io_ren_stalls_1, // @[rename-stage.scala:33:14]
output io_ren_stalls_2, // @[rename-stage.scala:33:14]
input io_kill, // @[rename-stage.scala:33:14]
input io_dec_fire_0, // @[rename-stage.scala:33:14]
input io_dec_fire_1, // @[rename-stage.scala:33:14]
input io_dec_fire_2, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_0_inst, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_0_debug_inst, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_dec_uops_0_debug_pc, // @[rename-stage.scala:33:14]
input io_dec_uops_0_iq_type_0, // @[rename-stage.scala:33:14]
input io_dec_uops_0_iq_type_1, // @[rename-stage.scala:33:14]
input io_dec_uops_0_iq_type_2, // @[rename-stage.scala:33:14]
input io_dec_uops_0_iq_type_3, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_0, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_1, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_2, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_3, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_4, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_5, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_6, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_7, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_8, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fu_code_9, // @[rename-stage.scala:33:14]
input [15:0] io_dec_uops_0_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_0_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_0_br_type, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_sfb, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_fence, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_fencei, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_sfence, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_amo, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_eret, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_rocc, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_0_ftq_idx, // @[rename-stage.scala:33:14]
input io_dec_uops_0_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_0_pc_lob, // @[rename-stage.scala:33:14]
input io_dec_uops_0_taken, // @[rename-stage.scala:33:14]
input io_dec_uops_0_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_0_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_0_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_dec_uops_0_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_0_op2_sel, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_dec_uops_0_exception, // @[rename-stage.scala:33:14]
input [63:0] io_dec_uops_0_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_0_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_mem_size, // @[rename-stage.scala:33:14]
input io_dec_uops_0_mem_signed, // @[rename-stage.scala:33:14]
input io_dec_uops_0_uses_ldq, // @[rename-stage.scala:33:14]
input io_dec_uops_0_uses_stq, // @[rename-stage.scala:33:14]
input io_dec_uops_0_is_unique, // @[rename-stage.scala:33:14]
input io_dec_uops_0_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_0_csr_cmd, // @[rename-stage.scala:33:14]
input io_dec_uops_0_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_0_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_0_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_0_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_0_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_dec_uops_0_frs3_en, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_0_fcn_op, // @[rename-stage.scala:33:14]
input io_dec_uops_0_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_0_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_0_fp_typ, // @[rename-stage.scala:33:14]
input io_dec_uops_0_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_dec_uops_0_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_dec_uops_0_bp_debug_if, // @[rename-stage.scala:33:14]
input io_dec_uops_0_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_0_debug_fsrc, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_1_inst, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_1_debug_inst, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_dec_uops_1_debug_pc, // @[rename-stage.scala:33:14]
input io_dec_uops_1_iq_type_0, // @[rename-stage.scala:33:14]
input io_dec_uops_1_iq_type_1, // @[rename-stage.scala:33:14]
input io_dec_uops_1_iq_type_2, // @[rename-stage.scala:33:14]
input io_dec_uops_1_iq_type_3, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_0, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_1, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_2, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_3, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_4, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_5, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_6, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_7, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_8, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fu_code_9, // @[rename-stage.scala:33:14]
input [15:0] io_dec_uops_1_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_1_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_1_br_type, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_sfb, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_fence, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_fencei, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_sfence, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_amo, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_eret, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_rocc, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_1_ftq_idx, // @[rename-stage.scala:33:14]
input io_dec_uops_1_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_1_pc_lob, // @[rename-stage.scala:33:14]
input io_dec_uops_1_taken, // @[rename-stage.scala:33:14]
input io_dec_uops_1_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_1_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_1_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_dec_uops_1_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_1_op2_sel, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_dec_uops_1_exception, // @[rename-stage.scala:33:14]
input [63:0] io_dec_uops_1_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_1_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_mem_size, // @[rename-stage.scala:33:14]
input io_dec_uops_1_mem_signed, // @[rename-stage.scala:33:14]
input io_dec_uops_1_uses_ldq, // @[rename-stage.scala:33:14]
input io_dec_uops_1_uses_stq, // @[rename-stage.scala:33:14]
input io_dec_uops_1_is_unique, // @[rename-stage.scala:33:14]
input io_dec_uops_1_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_1_csr_cmd, // @[rename-stage.scala:33:14]
input io_dec_uops_1_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_1_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_1_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_1_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_1_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_dec_uops_1_frs3_en, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_1_fcn_op, // @[rename-stage.scala:33:14]
input io_dec_uops_1_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_1_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_1_fp_typ, // @[rename-stage.scala:33:14]
input io_dec_uops_1_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_dec_uops_1_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_dec_uops_1_bp_debug_if, // @[rename-stage.scala:33:14]
input io_dec_uops_1_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_1_debug_fsrc, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_2_inst, // @[rename-stage.scala:33:14]
input [31:0] io_dec_uops_2_debug_inst, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_dec_uops_2_debug_pc, // @[rename-stage.scala:33:14]
input io_dec_uops_2_iq_type_0, // @[rename-stage.scala:33:14]
input io_dec_uops_2_iq_type_1, // @[rename-stage.scala:33:14]
input io_dec_uops_2_iq_type_2, // @[rename-stage.scala:33:14]
input io_dec_uops_2_iq_type_3, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_0, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_1, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_2, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_3, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_4, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_5, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_6, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_7, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_8, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fu_code_9, // @[rename-stage.scala:33:14]
input [15:0] io_dec_uops_2_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_2_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_dec_uops_2_br_type, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_sfb, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_fence, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_fencei, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_sfence, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_amo, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_eret, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_rocc, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_2_ftq_idx, // @[rename-stage.scala:33:14]
input io_dec_uops_2_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_2_pc_lob, // @[rename-stage.scala:33:14]
input io_dec_uops_2_taken, // @[rename-stage.scala:33:14]
input io_dec_uops_2_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_2_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_2_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_dec_uops_2_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_2_op2_sel, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_dec_uops_2_exception, // @[rename-stage.scala:33:14]
input [63:0] io_dec_uops_2_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_2_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_mem_size, // @[rename-stage.scala:33:14]
input io_dec_uops_2_mem_signed, // @[rename-stage.scala:33:14]
input io_dec_uops_2_uses_ldq, // @[rename-stage.scala:33:14]
input io_dec_uops_2_uses_stq, // @[rename-stage.scala:33:14]
input io_dec_uops_2_is_unique, // @[rename-stage.scala:33:14]
input io_dec_uops_2_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_2_csr_cmd, // @[rename-stage.scala:33:14]
input io_dec_uops_2_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_2_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_2_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_2_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_dec_uops_2_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_dec_uops_2_frs3_en, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_dec_uops_2_fcn_op, // @[rename-stage.scala:33:14]
input io_dec_uops_2_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_2_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_dec_uops_2_fp_typ, // @[rename-stage.scala:33:14]
input io_dec_uops_2_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_dec_uops_2_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_dec_uops_2_bp_debug_if, // @[rename-stage.scala:33:14]
input io_dec_uops_2_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_dec_uops_2_debug_fsrc, // @[rename-stage.scala:33:14]
output [2:0] io_ren2_uops_0_imm_sel, // @[rename-stage.scala:33:14]
output [4:0] io_ren2_uops_0_pimm, // @[rename-stage.scala:33:14]
output [2:0] io_ren2_uops_1_imm_sel, // @[rename-stage.scala:33:14]
output [4:0] io_ren2_uops_1_pimm, // @[rename-stage.scala:33:14]
output [2:0] io_ren2_uops_2_imm_sel, // @[rename-stage.scala:33:14]
output [4:0] io_ren2_uops_2_pimm, // @[rename-stage.scala:33:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[rename-stage.scala:33:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[rename-stage.scala:33:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_fence, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_amo, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_eret, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_taken, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_is_unique, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_brupdate_b2_mispredict, // @[rename-stage.scala:33:14]
input io_brupdate_b2_taken, // @[rename-stage.scala:33:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rename-stage.scala:33:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rename-stage.scala:33:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rename-stage.scala:33:14]
input [20:0] io_brupdate_b2_target_offset, // @[rename-stage.scala:33:14]
input io_dis_fire_0, // @[rename-stage.scala:33:14]
input io_dis_fire_1, // @[rename-stage.scala:33:14]
input io_dis_fire_2, // @[rename-stage.scala:33:14]
input io_dis_ready, // @[rename-stage.scala:33:14]
input io_wakeups_0_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_0_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_0_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_0_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_0_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_wakeups_1_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_1_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_1_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_1_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_1_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_wakeups_2_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_2_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_2_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_2_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_2_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_2_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_2_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_2_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_2_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_2_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_2_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_2_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_2_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_2_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_2_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_2_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_2_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_2_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_2_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_wakeups_3_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_3_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_3_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_3_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_3_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_3_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_3_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_3_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_3_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_3_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_3_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_3_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_3_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_3_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_3_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_3_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_3_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_3_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_3_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_wakeups_4_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_4_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_4_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_4_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_4_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_4_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_4_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_4_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_4_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_4_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_4_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_4_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_4_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_4_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_4_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_4_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_4_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_4_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_4_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_wakeups_5_valid, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_5_bits_uop_inst, // @[rename-stage.scala:33:14]
input [31:0] io_wakeups_5_bits_uop_debug_inst, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_wakeups_5_bits_uop_debug_pc, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iq_type_0, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iq_type_1, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iq_type_2, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iq_type_3, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_0, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_1, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_2, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_3, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_4, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_5, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_6, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_7, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_8, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fu_code_9, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_issued, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_wakeups_5_bits_uop_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_5_bits_uop_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_wakeups_5_bits_uop_br_type, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_sfb, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_fence, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_fencei, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_sfence, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_amo, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_eret, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_rocc, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_ftq_idx, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_5_bits_uop_pc_lob, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_taken, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_wakeups_5_bits_uop_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_op2_sel, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_ppred, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_prs1_busy, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_prs2_busy, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_prs3_busy, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_wakeups_5_bits_uop_stale_pdst, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_exception, // @[rename-stage.scala:33:14]
input [63:0] io_wakeups_5_bits_uop_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_mem_size, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_mem_signed, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_uses_ldq, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_uses_stq, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_is_unique, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_csr_cmd, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_5_bits_uop_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_5_bits_uop_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_5_bits_uop_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_wakeups_5_bits_uop_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_frs3_en, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_wakeups_5_bits_uop_fcn_op, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_wakeups_5_bits_uop_fp_typ, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_bp_debug_if, // @[rename-stage.scala:33:14]
input io_wakeups_5_bits_uop_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_wakeups_5_bits_uop_debug_tsrc, // @[rename-stage.scala:33:14]
input io_com_valids_0, // @[rename-stage.scala:33:14]
input io_com_valids_1, // @[rename-stage.scala:33:14]
input io_com_valids_2, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_0_inst, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_0_debug_inst, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_com_uops_0_debug_pc, // @[rename-stage.scala:33:14]
input io_com_uops_0_iq_type_0, // @[rename-stage.scala:33:14]
input io_com_uops_0_iq_type_1, // @[rename-stage.scala:33:14]
input io_com_uops_0_iq_type_2, // @[rename-stage.scala:33:14]
input io_com_uops_0_iq_type_3, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_0, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_1, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_2, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_3, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_4, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_5, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_6, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_7, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_8, // @[rename-stage.scala:33:14]
input io_com_uops_0_fu_code_9, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_issued, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_0_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_com_uops_0_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_0_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_0_br_type, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_sfb, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_fence, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_fencei, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_sfence, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_amo, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_eret, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_rocc, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_ftq_idx, // @[rename-stage.scala:33:14]
input io_com_uops_0_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_0_pc_lob, // @[rename-stage.scala:33:14]
input io_com_uops_0_taken, // @[rename-stage.scala:33:14]
input io_com_uops_0_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_com_uops_0_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_op2_sel, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_ppred, // @[rename-stage.scala:33:14]
input io_com_uops_0_prs1_busy, // @[rename-stage.scala:33:14]
input io_com_uops_0_prs2_busy, // @[rename-stage.scala:33:14]
input io_com_uops_0_prs3_busy, // @[rename-stage.scala:33:14]
input io_com_uops_0_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_0_stale_pdst, // @[rename-stage.scala:33:14]
input io_com_uops_0_exception, // @[rename-stage.scala:33:14]
input [63:0] io_com_uops_0_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_mem_size, // @[rename-stage.scala:33:14]
input io_com_uops_0_mem_signed, // @[rename-stage.scala:33:14]
input io_com_uops_0_uses_ldq, // @[rename-stage.scala:33:14]
input io_com_uops_0_uses_stq, // @[rename-stage.scala:33:14]
input io_com_uops_0_is_unique, // @[rename-stage.scala:33:14]
input io_com_uops_0_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_csr_cmd, // @[rename-stage.scala:33:14]
input io_com_uops_0_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_0_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_0_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_0_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_0_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_com_uops_0_frs3_en, // @[rename-stage.scala:33:14]
input io_com_uops_0_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_0_fcn_op, // @[rename-stage.scala:33:14]
input io_com_uops_0_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_0_fp_typ, // @[rename-stage.scala:33:14]
input io_com_uops_0_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_com_uops_0_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_com_uops_0_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_com_uops_0_bp_debug_if, // @[rename-stage.scala:33:14]
input io_com_uops_0_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_0_debug_tsrc, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_1_inst, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_1_debug_inst, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_com_uops_1_debug_pc, // @[rename-stage.scala:33:14]
input io_com_uops_1_iq_type_0, // @[rename-stage.scala:33:14]
input io_com_uops_1_iq_type_1, // @[rename-stage.scala:33:14]
input io_com_uops_1_iq_type_2, // @[rename-stage.scala:33:14]
input io_com_uops_1_iq_type_3, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_0, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_1, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_2, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_3, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_4, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_5, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_6, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_7, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_8, // @[rename-stage.scala:33:14]
input io_com_uops_1_fu_code_9, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_issued, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_1_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_com_uops_1_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_1_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_1_br_type, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_sfb, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_fence, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_fencei, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_sfence, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_amo, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_eret, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_rocc, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_ftq_idx, // @[rename-stage.scala:33:14]
input io_com_uops_1_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_1_pc_lob, // @[rename-stage.scala:33:14]
input io_com_uops_1_taken, // @[rename-stage.scala:33:14]
input io_com_uops_1_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_com_uops_1_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_op2_sel, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_ppred, // @[rename-stage.scala:33:14]
input io_com_uops_1_prs1_busy, // @[rename-stage.scala:33:14]
input io_com_uops_1_prs2_busy, // @[rename-stage.scala:33:14]
input io_com_uops_1_prs3_busy, // @[rename-stage.scala:33:14]
input io_com_uops_1_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_1_stale_pdst, // @[rename-stage.scala:33:14]
input io_com_uops_1_exception, // @[rename-stage.scala:33:14]
input [63:0] io_com_uops_1_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_mem_size, // @[rename-stage.scala:33:14]
input io_com_uops_1_mem_signed, // @[rename-stage.scala:33:14]
input io_com_uops_1_uses_ldq, // @[rename-stage.scala:33:14]
input io_com_uops_1_uses_stq, // @[rename-stage.scala:33:14]
input io_com_uops_1_is_unique, // @[rename-stage.scala:33:14]
input io_com_uops_1_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_csr_cmd, // @[rename-stage.scala:33:14]
input io_com_uops_1_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_1_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_1_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_1_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_1_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_com_uops_1_frs3_en, // @[rename-stage.scala:33:14]
input io_com_uops_1_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_1_fcn_op, // @[rename-stage.scala:33:14]
input io_com_uops_1_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_1_fp_typ, // @[rename-stage.scala:33:14]
input io_com_uops_1_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_com_uops_1_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_com_uops_1_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_com_uops_1_bp_debug_if, // @[rename-stage.scala:33:14]
input io_com_uops_1_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_1_debug_tsrc, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_2_inst, // @[rename-stage.scala:33:14]
input [31:0] io_com_uops_2_debug_inst, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_rvc, // @[rename-stage.scala:33:14]
input [39:0] io_com_uops_2_debug_pc, // @[rename-stage.scala:33:14]
input io_com_uops_2_iq_type_0, // @[rename-stage.scala:33:14]
input io_com_uops_2_iq_type_1, // @[rename-stage.scala:33:14]
input io_com_uops_2_iq_type_2, // @[rename-stage.scala:33:14]
input io_com_uops_2_iq_type_3, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_0, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_1, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_2, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_3, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_4, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_5, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_6, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_7, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_8, // @[rename-stage.scala:33:14]
input io_com_uops_2_fu_code_9, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_issued, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_issued_partial_agen, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_issued_partial_dgen, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_iw_p1_speculative_child, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_iw_p2_speculative_child, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_p1_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_p2_bypass_hint, // @[rename-stage.scala:33:14]
input io_com_uops_2_iw_p3_bypass_hint, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_dis_col_sel, // @[rename-stage.scala:33:14]
input [15:0] io_com_uops_2_br_mask, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_2_br_tag, // @[rename-stage.scala:33:14]
input [3:0] io_com_uops_2_br_type, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_sfb, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_fence, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_fencei, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_sfence, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_amo, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_eret, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_sys_pc2epc, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_rocc, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_mov, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_ftq_idx, // @[rename-stage.scala:33:14]
input io_com_uops_2_edge_inst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_2_pc_lob, // @[rename-stage.scala:33:14]
input io_com_uops_2_taken, // @[rename-stage.scala:33:14]
input io_com_uops_2_imm_rename, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_imm_sel, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_pimm, // @[rename-stage.scala:33:14]
input [19:0] io_com_uops_2_imm_packed, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_op1_sel, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_op2_sel, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_ldst, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_wen, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_ren1, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_ren2, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_ren3, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_swap12, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_swap23, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_fp_ctrl_typeTagIn, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_fp_ctrl_typeTagOut, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_fromint, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_toint, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_fastpipe, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_fma, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_div, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_sqrt, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_wflags, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_ctrl_vec, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_rob_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_ldq_idx, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_stq_idx, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_rxq_idx, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_pdst, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_prs1, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_prs2, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_prs3, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_ppred, // @[rename-stage.scala:33:14]
input io_com_uops_2_prs1_busy, // @[rename-stage.scala:33:14]
input io_com_uops_2_prs2_busy, // @[rename-stage.scala:33:14]
input io_com_uops_2_prs3_busy, // @[rename-stage.scala:33:14]
input io_com_uops_2_ppred_busy, // @[rename-stage.scala:33:14]
input [6:0] io_com_uops_2_stale_pdst, // @[rename-stage.scala:33:14]
input io_com_uops_2_exception, // @[rename-stage.scala:33:14]
input [63:0] io_com_uops_2_exc_cause, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_mem_cmd, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_mem_size, // @[rename-stage.scala:33:14]
input io_com_uops_2_mem_signed, // @[rename-stage.scala:33:14]
input io_com_uops_2_uses_ldq, // @[rename-stage.scala:33:14]
input io_com_uops_2_uses_stq, // @[rename-stage.scala:33:14]
input io_com_uops_2_is_unique, // @[rename-stage.scala:33:14]
input io_com_uops_2_flush_on_commit, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_csr_cmd, // @[rename-stage.scala:33:14]
input io_com_uops_2_ldst_is_rs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_2_ldst, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_2_lrs1, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_2_lrs2, // @[rename-stage.scala:33:14]
input [5:0] io_com_uops_2_lrs3, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_dst_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_lrs1_rtype, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_lrs2_rtype, // @[rename-stage.scala:33:14]
input io_com_uops_2_frs3_en, // @[rename-stage.scala:33:14]
input io_com_uops_2_fcn_dw, // @[rename-stage.scala:33:14]
input [4:0] io_com_uops_2_fcn_op, // @[rename-stage.scala:33:14]
input io_com_uops_2_fp_val, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_fp_rm, // @[rename-stage.scala:33:14]
input [1:0] io_com_uops_2_fp_typ, // @[rename-stage.scala:33:14]
input io_com_uops_2_xcpt_pf_if, // @[rename-stage.scala:33:14]
input io_com_uops_2_xcpt_ae_if, // @[rename-stage.scala:33:14]
input io_com_uops_2_xcpt_ma_if, // @[rename-stage.scala:33:14]
input io_com_uops_2_bp_debug_if, // @[rename-stage.scala:33:14]
input io_com_uops_2_bp_xcpt_if, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_debug_fsrc, // @[rename-stage.scala:33:14]
input [2:0] io_com_uops_2_debug_tsrc, // @[rename-stage.scala:33:14]
input io_rollback, // @[rename-stage.scala:33:14]
input io_debug_rob_empty // @[rename-stage.scala:33:14]
);
wire [2:0] next_uop_2_debug_tsrc; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_debug_fsrc; // @[rename-stage.scala:95:24]
wire next_uop_2_bp_xcpt_if; // @[rename-stage.scala:95:24]
wire next_uop_2_bp_debug_if; // @[rename-stage.scala:95:24]
wire next_uop_2_xcpt_ma_if; // @[rename-stage.scala:95:24]
wire next_uop_2_xcpt_ae_if; // @[rename-stage.scala:95:24]
wire next_uop_2_xcpt_pf_if; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_fp_typ; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_fp_rm; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_val; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_fcn_op; // @[rename-stage.scala:95:24]
wire next_uop_2_fcn_dw; // @[rename-stage.scala:95:24]
wire next_uop_2_frs3_en; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_lrs2_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_lrs1_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_dst_rtype; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_2_lrs3; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_2_lrs2; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_2_lrs1; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_2_ldst; // @[rename-stage.scala:95:24]
wire next_uop_2_ldst_is_rs1; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_csr_cmd; // @[rename-stage.scala:95:24]
wire next_uop_2_flush_on_commit; // @[rename-stage.scala:95:24]
wire next_uop_2_is_unique; // @[rename-stage.scala:95:24]
wire next_uop_2_uses_stq; // @[rename-stage.scala:95:24]
wire next_uop_2_uses_ldq; // @[rename-stage.scala:95:24]
wire next_uop_2_mem_signed; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_mem_size; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_mem_cmd; // @[rename-stage.scala:95:24]
wire [63:0] next_uop_2_exc_cause; // @[rename-stage.scala:95:24]
wire next_uop_2_exception; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_stale_pdst; // @[rename-stage.scala:95:24]
wire next_uop_2_ppred_busy; // @[rename-stage.scala:95:24]
wire next_uop_2_prs3_busy; // @[rename-stage.scala:95:24]
wire next_uop_2_prs2_busy; // @[rename-stage.scala:95:24]
wire next_uop_2_prs1_busy; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_ppred; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_prs3; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_prs2; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_prs1; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_pdst; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_rxq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_stq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_ldq_idx; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_2_rob_idx; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_op2_sel; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_op1_sel; // @[rename-stage.scala:95:24]
wire [19:0] next_uop_2_imm_packed; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_pimm; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_imm_sel; // @[rename-stage.scala:95:24]
wire next_uop_2_imm_rename; // @[rename-stage.scala:95:24]
wire next_uop_2_taken; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_2_pc_lob; // @[rename-stage.scala:95:24]
wire next_uop_2_edge_inst; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_2_ftq_idx; // @[rename-stage.scala:95:24]
wire next_uop_2_is_mov; // @[rename-stage.scala:95:24]
wire next_uop_2_is_rocc; // @[rename-stage.scala:95:24]
wire next_uop_2_is_sys_pc2epc; // @[rename-stage.scala:95:24]
wire next_uop_2_is_eret; // @[rename-stage.scala:95:24]
wire next_uop_2_is_amo; // @[rename-stage.scala:95:24]
wire next_uop_2_is_sfence; // @[rename-stage.scala:95:24]
wire next_uop_2_is_fencei; // @[rename-stage.scala:95:24]
wire next_uop_2_is_fence; // @[rename-stage.scala:95:24]
wire next_uop_2_is_sfb; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_2_br_type; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_2_br_tag; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_dis_col_sel; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_p3_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_p2_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_p1_bypass_hint; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_iw_p2_speculative_child; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_2_iw_p1_speculative_child; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_issued_partial_dgen; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_issued_partial_agen; // @[rename-stage.scala:95:24]
wire next_uop_2_iw_issued; // @[rename-stage.scala:95:24]
wire [39:0] next_uop_2_debug_pc; // @[rename-stage.scala:95:24]
wire next_uop_2_is_rvc; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_2_debug_inst; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_2_inst; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_vec; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_wflags; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_sqrt; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_div; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_fma; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_fastpipe; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_toint; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_fromint; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_swap23; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_swap12; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_ren3; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_ren2; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_ren1; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_wen; // @[rename-stage.scala:95:24]
wire next_uop_2_fp_ctrl_ldst; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_9; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_8; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_7; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_6; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_5; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_4; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_3; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_2; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_1; // @[rename-stage.scala:95:24]
wire next_uop_2_fu_code_0; // @[rename-stage.scala:95:24]
wire next_uop_2_iq_type_3; // @[rename-stage.scala:95:24]
wire next_uop_2_iq_type_2; // @[rename-stage.scala:95:24]
wire next_uop_2_iq_type_1; // @[rename-stage.scala:95:24]
wire next_uop_2_iq_type_0; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_debug_tsrc; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_debug_fsrc; // @[rename-stage.scala:95:24]
wire next_uop_1_bp_xcpt_if; // @[rename-stage.scala:95:24]
wire next_uop_1_bp_debug_if; // @[rename-stage.scala:95:24]
wire next_uop_1_xcpt_ma_if; // @[rename-stage.scala:95:24]
wire next_uop_1_xcpt_ae_if; // @[rename-stage.scala:95:24]
wire next_uop_1_xcpt_pf_if; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_fp_typ; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_fp_rm; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_val; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_fcn_op; // @[rename-stage.scala:95:24]
wire next_uop_1_fcn_dw; // @[rename-stage.scala:95:24]
wire next_uop_1_frs3_en; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_lrs2_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_lrs1_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_dst_rtype; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_1_lrs3; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_1_lrs2; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_1_lrs1; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_1_ldst; // @[rename-stage.scala:95:24]
wire next_uop_1_ldst_is_rs1; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_csr_cmd; // @[rename-stage.scala:95:24]
wire next_uop_1_flush_on_commit; // @[rename-stage.scala:95:24]
wire next_uop_1_is_unique; // @[rename-stage.scala:95:24]
wire next_uop_1_uses_stq; // @[rename-stage.scala:95:24]
wire next_uop_1_uses_ldq; // @[rename-stage.scala:95:24]
wire next_uop_1_mem_signed; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_mem_size; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_mem_cmd; // @[rename-stage.scala:95:24]
wire [63:0] next_uop_1_exc_cause; // @[rename-stage.scala:95:24]
wire next_uop_1_exception; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_stale_pdst; // @[rename-stage.scala:95:24]
wire next_uop_1_ppred_busy; // @[rename-stage.scala:95:24]
wire next_uop_1_prs3_busy; // @[rename-stage.scala:95:24]
wire next_uop_1_prs2_busy; // @[rename-stage.scala:95:24]
wire next_uop_1_prs1_busy; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_ppred; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_prs3; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_prs2; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_prs1; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_pdst; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_rxq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_stq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_ldq_idx; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_1_rob_idx; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_op2_sel; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_op1_sel; // @[rename-stage.scala:95:24]
wire [19:0] next_uop_1_imm_packed; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_pimm; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_imm_sel; // @[rename-stage.scala:95:24]
wire next_uop_1_imm_rename; // @[rename-stage.scala:95:24]
wire next_uop_1_taken; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_1_pc_lob; // @[rename-stage.scala:95:24]
wire next_uop_1_edge_inst; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_1_ftq_idx; // @[rename-stage.scala:95:24]
wire next_uop_1_is_mov; // @[rename-stage.scala:95:24]
wire next_uop_1_is_rocc; // @[rename-stage.scala:95:24]
wire next_uop_1_is_sys_pc2epc; // @[rename-stage.scala:95:24]
wire next_uop_1_is_eret; // @[rename-stage.scala:95:24]
wire next_uop_1_is_amo; // @[rename-stage.scala:95:24]
wire next_uop_1_is_sfence; // @[rename-stage.scala:95:24]
wire next_uop_1_is_fencei; // @[rename-stage.scala:95:24]
wire next_uop_1_is_fence; // @[rename-stage.scala:95:24]
wire next_uop_1_is_sfb; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_1_br_type; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_1_br_tag; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_dis_col_sel; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_p3_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_p2_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_p1_bypass_hint; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_iw_p2_speculative_child; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_1_iw_p1_speculative_child; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_issued_partial_dgen; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_issued_partial_agen; // @[rename-stage.scala:95:24]
wire next_uop_1_iw_issued; // @[rename-stage.scala:95:24]
wire [39:0] next_uop_1_debug_pc; // @[rename-stage.scala:95:24]
wire next_uop_1_is_rvc; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_1_debug_inst; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_1_inst; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_vec; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_wflags; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_sqrt; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_div; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_fma; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_fastpipe; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_toint; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_fromint; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_swap23; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_swap12; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_ren3; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_ren2; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_ren1; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_wen; // @[rename-stage.scala:95:24]
wire next_uop_1_fp_ctrl_ldst; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_9; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_8; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_7; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_6; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_5; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_4; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_3; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_2; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_1; // @[rename-stage.scala:95:24]
wire next_uop_1_fu_code_0; // @[rename-stage.scala:95:24]
wire next_uop_1_iq_type_3; // @[rename-stage.scala:95:24]
wire next_uop_1_iq_type_2; // @[rename-stage.scala:95:24]
wire next_uop_1_iq_type_1; // @[rename-stage.scala:95:24]
wire next_uop_1_iq_type_0; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_debug_tsrc; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_debug_fsrc; // @[rename-stage.scala:95:24]
wire next_uop_bp_xcpt_if; // @[rename-stage.scala:95:24]
wire next_uop_bp_debug_if; // @[rename-stage.scala:95:24]
wire next_uop_xcpt_ma_if; // @[rename-stage.scala:95:24]
wire next_uop_xcpt_ae_if; // @[rename-stage.scala:95:24]
wire next_uop_xcpt_pf_if; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_fp_typ; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_fp_rm; // @[rename-stage.scala:95:24]
wire next_uop_fp_val; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_fcn_op; // @[rename-stage.scala:95:24]
wire next_uop_fcn_dw; // @[rename-stage.scala:95:24]
wire next_uop_frs3_en; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_lrs2_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_lrs1_rtype; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_dst_rtype; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_lrs3; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_lrs2; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_lrs1; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_ldst; // @[rename-stage.scala:95:24]
wire next_uop_ldst_is_rs1; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_csr_cmd; // @[rename-stage.scala:95:24]
wire next_uop_flush_on_commit; // @[rename-stage.scala:95:24]
wire next_uop_is_unique; // @[rename-stage.scala:95:24]
wire next_uop_uses_stq; // @[rename-stage.scala:95:24]
wire next_uop_uses_ldq; // @[rename-stage.scala:95:24]
wire next_uop_mem_signed; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_mem_size; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_mem_cmd; // @[rename-stage.scala:95:24]
wire [63:0] next_uop_exc_cause; // @[rename-stage.scala:95:24]
wire next_uop_exception; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_stale_pdst; // @[rename-stage.scala:95:24]
wire next_uop_ppred_busy; // @[rename-stage.scala:95:24]
wire next_uop_prs3_busy; // @[rename-stage.scala:95:24]
wire next_uop_prs2_busy; // @[rename-stage.scala:95:24]
wire next_uop_prs1_busy; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_ppred; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_prs3; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_prs2; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_prs1; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_pdst; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_rxq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_stq_idx; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_ldq_idx; // @[rename-stage.scala:95:24]
wire [6:0] next_uop_rob_idx; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_op2_sel; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_op1_sel; // @[rename-stage.scala:95:24]
wire [19:0] next_uop_imm_packed; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_pimm; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_imm_sel; // @[rename-stage.scala:95:24]
wire next_uop_imm_rename; // @[rename-stage.scala:95:24]
wire next_uop_taken; // @[rename-stage.scala:95:24]
wire [5:0] next_uop_pc_lob; // @[rename-stage.scala:95:24]
wire next_uop_edge_inst; // @[rename-stage.scala:95:24]
wire [4:0] next_uop_ftq_idx; // @[rename-stage.scala:95:24]
wire next_uop_is_mov; // @[rename-stage.scala:95:24]
wire next_uop_is_rocc; // @[rename-stage.scala:95:24]
wire next_uop_is_sys_pc2epc; // @[rename-stage.scala:95:24]
wire next_uop_is_eret; // @[rename-stage.scala:95:24]
wire next_uop_is_amo; // @[rename-stage.scala:95:24]
wire next_uop_is_sfence; // @[rename-stage.scala:95:24]
wire next_uop_is_fencei; // @[rename-stage.scala:95:24]
wire next_uop_is_fence; // @[rename-stage.scala:95:24]
wire next_uop_is_sfb; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_br_type; // @[rename-stage.scala:95:24]
wire [3:0] next_uop_br_tag; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_dis_col_sel; // @[rename-stage.scala:95:24]
wire next_uop_iw_p3_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_iw_p2_bypass_hint; // @[rename-stage.scala:95:24]
wire next_uop_iw_p1_bypass_hint; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_iw_p2_speculative_child; // @[rename-stage.scala:95:24]
wire [2:0] next_uop_iw_p1_speculative_child; // @[rename-stage.scala:95:24]
wire next_uop_iw_issued_partial_dgen; // @[rename-stage.scala:95:24]
wire next_uop_iw_issued_partial_agen; // @[rename-stage.scala:95:24]
wire next_uop_iw_issued; // @[rename-stage.scala:95:24]
wire [39:0] next_uop_debug_pc; // @[rename-stage.scala:95:24]
wire next_uop_is_rvc; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_debug_inst; // @[rename-stage.scala:95:24]
wire [31:0] next_uop_inst; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_vec; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_wflags; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_sqrt; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_div; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_fma; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_toint; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_fromint; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:95:24]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_swap23; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_swap12; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_ren3; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_ren2; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_ren1; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_wen; // @[rename-stage.scala:95:24]
wire next_uop_fp_ctrl_ldst; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_9; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_8; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_7; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_6; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_5; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_4; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_3; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_2; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_1; // @[rename-stage.scala:95:24]
wire next_uop_fu_code_0; // @[rename-stage.scala:95:24]
wire next_uop_iq_type_3; // @[rename-stage.scala:95:24]
wire next_uop_iq_type_2; // @[rename-stage.scala:95:24]
wire next_uop_iq_type_1; // @[rename-stage.scala:95:24]
wire next_uop_iq_type_0; // @[rename-stage.scala:95:24]
wire [2:0] ren2_uops_2_debug_tsrc; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_debug_fsrc; // @[rename-stage.scala:77:29]
wire ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:77:29]
wire ren2_uops_2_bp_debug_if; // @[rename-stage.scala:77:29]
wire ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:77:29]
wire ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:77:29]
wire ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_fp_typ; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_fp_rm; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_val; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_fcn_op; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fcn_dw; // @[rename-stage.scala:77:29]
wire ren2_uops_2_frs3_en; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_dst_rtype; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_2_lrs3; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_2_lrs2; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_2_lrs1; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_2_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_csr_cmd; // @[rename-stage.scala:77:29]
wire ren2_uops_2_flush_on_commit; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_unique; // @[rename-stage.scala:77:29]
wire ren2_uops_2_uses_stq; // @[rename-stage.scala:77:29]
wire ren2_uops_2_uses_ldq; // @[rename-stage.scala:77:29]
wire ren2_uops_2_mem_signed; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_mem_size; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_mem_cmd; // @[rename-stage.scala:77:29]
wire [63:0] ren2_uops_2_exc_cause; // @[rename-stage.scala:77:29]
wire ren2_uops_2_exception; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_stale_pdst; // @[rename-stage.scala:77:29]
wire ren2_uops_2_ppred_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_2_prs3_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_2_prs2_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_2_prs1_busy; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_ppred; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_prs3; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_prs2; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_prs1; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_pdst; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_rxq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_stq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_ldq_idx; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_2_rob_idx; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_op2_sel; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_op1_sel; // @[rename-stage.scala:77:29]
wire [19:0] ren2_uops_2_imm_packed; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_pimm; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_imm_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_2_imm_rename; // @[rename-stage.scala:77:29]
wire ren2_uops_2_taken; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_2_pc_lob; // @[rename-stage.scala:77:29]
wire ren2_uops_2_edge_inst; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_2_ftq_idx; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_mov; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_rocc; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_eret; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_amo; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_sfence; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_fencei; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_fence; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_sfb; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_2_br_type; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_2_br_tag; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_dis_col_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_p3_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_p2_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_p1_bypass_hint; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_iw_p2_speculative_child; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_2_iw_p1_speculative_child; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_issued_partial_dgen; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_issued_partial_agen; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iw_issued; // @[rename-stage.scala:77:29]
wire [39:0] ren2_uops_2_debug_pc; // @[rename-stage.scala:77:29]
wire ren2_uops_2_is_rvc; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_2_debug_inst; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_2_inst; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_vec; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_wflags; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_sqrt; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_div; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_fma; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_toint; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_fromint; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_swap23; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_swap12; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_ren3; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_ren2; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_ren1; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_wen; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fp_ctrl_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_9; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_8; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_7; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_6; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_5; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_4; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_3; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_2; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_1; // @[rename-stage.scala:77:29]
wire ren2_uops_2_fu_code_0; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iq_type_3; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iq_type_2; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iq_type_1; // @[rename-stage.scala:77:29]
wire ren2_uops_2_iq_type_0; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_debug_tsrc; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_debug_fsrc; // @[rename-stage.scala:77:29]
wire ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:77:29]
wire ren2_uops_1_bp_debug_if; // @[rename-stage.scala:77:29]
wire ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:77:29]
wire ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:77:29]
wire ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_fp_typ; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_fp_rm; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_val; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_fcn_op; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fcn_dw; // @[rename-stage.scala:77:29]
wire ren2_uops_1_frs3_en; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_dst_rtype; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_1_lrs3; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_1_lrs2; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_1_lrs1; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_1_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_csr_cmd; // @[rename-stage.scala:77:29]
wire ren2_uops_1_flush_on_commit; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_unique; // @[rename-stage.scala:77:29]
wire ren2_uops_1_uses_stq; // @[rename-stage.scala:77:29]
wire ren2_uops_1_uses_ldq; // @[rename-stage.scala:77:29]
wire ren2_uops_1_mem_signed; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_mem_size; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_mem_cmd; // @[rename-stage.scala:77:29]
wire [63:0] ren2_uops_1_exc_cause; // @[rename-stage.scala:77:29]
wire ren2_uops_1_exception; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_stale_pdst; // @[rename-stage.scala:77:29]
wire ren2_uops_1_ppred_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_1_prs3_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_1_prs2_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_1_prs1_busy; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_ppred; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_prs3; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_prs2; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_prs1; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_pdst; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_rxq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_stq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_ldq_idx; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_1_rob_idx; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_op2_sel; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_op1_sel; // @[rename-stage.scala:77:29]
wire [19:0] ren2_uops_1_imm_packed; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_pimm; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_imm_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_1_imm_rename; // @[rename-stage.scala:77:29]
wire ren2_uops_1_taken; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_1_pc_lob; // @[rename-stage.scala:77:29]
wire ren2_uops_1_edge_inst; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_1_ftq_idx; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_mov; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_rocc; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_eret; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_amo; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_sfence; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_fencei; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_fence; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_sfb; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_1_br_type; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_1_br_tag; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_dis_col_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_p3_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_p2_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_p1_bypass_hint; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_iw_p2_speculative_child; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_1_iw_p1_speculative_child; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_issued_partial_dgen; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_issued_partial_agen; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iw_issued; // @[rename-stage.scala:77:29]
wire [39:0] ren2_uops_1_debug_pc; // @[rename-stage.scala:77:29]
wire ren2_uops_1_is_rvc; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_1_debug_inst; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_1_inst; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_vec; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_wflags; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_sqrt; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_div; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_fma; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_toint; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_fromint; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_swap23; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_swap12; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_ren3; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_ren2; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_ren1; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_wen; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fp_ctrl_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_9; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_8; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_7; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_6; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_5; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_4; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_3; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_2; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_1; // @[rename-stage.scala:77:29]
wire ren2_uops_1_fu_code_0; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iq_type_3; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iq_type_2; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iq_type_1; // @[rename-stage.scala:77:29]
wire ren2_uops_1_iq_type_0; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_debug_tsrc; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_debug_fsrc; // @[rename-stage.scala:77:29]
wire ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:77:29]
wire ren2_uops_0_bp_debug_if; // @[rename-stage.scala:77:29]
wire ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:77:29]
wire ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:77:29]
wire ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_fp_typ; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_fp_rm; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_val; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_fcn_op; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fcn_dw; // @[rename-stage.scala:77:29]
wire ren2_uops_0_frs3_en; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_dst_rtype; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_0_lrs3; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_0_lrs2; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_0_lrs1; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_0_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_csr_cmd; // @[rename-stage.scala:77:29]
wire ren2_uops_0_flush_on_commit; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_unique; // @[rename-stage.scala:77:29]
wire ren2_uops_0_uses_stq; // @[rename-stage.scala:77:29]
wire ren2_uops_0_uses_ldq; // @[rename-stage.scala:77:29]
wire ren2_uops_0_mem_signed; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_mem_size; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_mem_cmd; // @[rename-stage.scala:77:29]
wire [63:0] ren2_uops_0_exc_cause; // @[rename-stage.scala:77:29]
wire ren2_uops_0_exception; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_stale_pdst; // @[rename-stage.scala:77:29]
wire ren2_uops_0_ppred_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_0_prs3_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_0_prs2_busy; // @[rename-stage.scala:77:29]
wire ren2_uops_0_prs1_busy; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_ppred; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_prs3; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_prs2; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_prs1; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_pdst; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_rxq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_stq_idx; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_ldq_idx; // @[rename-stage.scala:77:29]
wire [6:0] ren2_uops_0_rob_idx; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_op2_sel; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_op1_sel; // @[rename-stage.scala:77:29]
wire [19:0] ren2_uops_0_imm_packed; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_pimm; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_imm_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_0_imm_rename; // @[rename-stage.scala:77:29]
wire ren2_uops_0_taken; // @[rename-stage.scala:77:29]
wire [5:0] ren2_uops_0_pc_lob; // @[rename-stage.scala:77:29]
wire ren2_uops_0_edge_inst; // @[rename-stage.scala:77:29]
wire [4:0] ren2_uops_0_ftq_idx; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_mov; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_rocc; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_eret; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_amo; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_sfence; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_fencei; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_fence; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_sfb; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_0_br_type; // @[rename-stage.scala:77:29]
wire [3:0] ren2_uops_0_br_tag; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_dis_col_sel; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_p3_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_p2_bypass_hint; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_p1_bypass_hint; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_iw_p2_speculative_child; // @[rename-stage.scala:77:29]
wire [2:0] ren2_uops_0_iw_p1_speculative_child; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_issued_partial_dgen; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_issued_partial_agen; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iw_issued; // @[rename-stage.scala:77:29]
wire [39:0] ren2_uops_0_debug_pc; // @[rename-stage.scala:77:29]
wire ren2_uops_0_is_rvc; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_0_debug_inst; // @[rename-stage.scala:77:29]
wire [31:0] ren2_uops_0_inst; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_vec; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_wflags; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_sqrt; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_div; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_fma; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_toint; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_fromint; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29]
wire [1:0] ren2_uops_0_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_swap23; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_swap12; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_ren3; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_ren2; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_ren1; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_wen; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fp_ctrl_ldst; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_9; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_8; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_7; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_6; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_5; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_4; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_3; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_2; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_1; // @[rename-stage.scala:77:29]
wire ren2_uops_0_fu_code_0; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iq_type_3; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iq_type_2; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iq_type_1; // @[rename-stage.scala:77:29]
wire ren2_uops_0_iq_type_0; // @[rename-stage.scala:77:29]
wire _freelist_io_alloc_pregs_0_valid; // @[rename-stage.scala:417:24]
wire [4:0] _freelist_io_alloc_pregs_0_bits; // @[rename-stage.scala:417:24]
wire _freelist_io_alloc_pregs_1_valid; // @[rename-stage.scala:417:24]
wire [4:0] _freelist_io_alloc_pregs_1_bits; // @[rename-stage.scala:417:24]
wire _freelist_io_alloc_pregs_2_valid; // @[rename-stage.scala:417:24]
wire [4:0] _freelist_io_alloc_pregs_2_bits; // @[rename-stage.scala:417:24]
wire [31:0] _freelist_io_debug_freelist; // @[rename-stage.scala:417:24]
wire io_kill_0 = io_kill; // @[rename-stage.scala:414:7]
wire io_dec_fire_0_0 = io_dec_fire_0; // @[rename-stage.scala:414:7]
wire io_dec_fire_1_0 = io_dec_fire_1; // @[rename-stage.scala:414:7]
wire io_dec_fire_2_0 = io_dec_fire_2; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_0_inst_0 = io_dec_uops_0_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_0_debug_inst_0 = io_dec_uops_0_debug_inst; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_rvc_0 = io_dec_uops_0_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_dec_uops_0_debug_pc_0 = io_dec_uops_0_debug_pc; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iq_type_0_0 = io_dec_uops_0_iq_type_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iq_type_1_0 = io_dec_uops_0_iq_type_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iq_type_2_0 = io_dec_uops_0_iq_type_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iq_type_3_0 = io_dec_uops_0_iq_type_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_0_0 = io_dec_uops_0_fu_code_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_1_0 = io_dec_uops_0_fu_code_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_2_0 = io_dec_uops_0_fu_code_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_3_0 = io_dec_uops_0_fu_code_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_4_0 = io_dec_uops_0_fu_code_4; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_5_0 = io_dec_uops_0_fu_code_5; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_6_0 = io_dec_uops_0_fu_code_6; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_7_0 = io_dec_uops_0_fu_code_7; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_8_0 = io_dec_uops_0_fu_code_8; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fu_code_9_0 = io_dec_uops_0_fu_code_9; // @[rename-stage.scala:414:7]
wire [15:0] io_dec_uops_0_br_mask_0 = io_dec_uops_0_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_0_br_tag_0 = io_dec_uops_0_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_0_br_type_0 = io_dec_uops_0_br_type; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_sfb_0 = io_dec_uops_0_is_sfb; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_fence_0 = io_dec_uops_0_is_fence; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_fencei_0 = io_dec_uops_0_is_fencei; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_sfence_0 = io_dec_uops_0_is_sfence; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_amo_0 = io_dec_uops_0_is_amo; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_eret_0 = io_dec_uops_0_is_eret; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_sys_pc2epc_0 = io_dec_uops_0_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_rocc_0 = io_dec_uops_0_is_rocc; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_mov_0 = io_dec_uops_0_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_ftq_idx_0 = io_dec_uops_0_ftq_idx; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_edge_inst_0 = io_dec_uops_0_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_0_pc_lob_0 = io_dec_uops_0_pc_lob; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_taken_0 = io_dec_uops_0_taken; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_imm_rename_0 = io_dec_uops_0_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_imm_sel_0 = io_dec_uops_0_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_pimm_0 = io_dec_uops_0_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_dec_uops_0_imm_packed_0 = io_dec_uops_0_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_op1_sel_0 = io_dec_uops_0_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_op2_sel_0 = io_dec_uops_0_op2_sel; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_ldst_0 = io_dec_uops_0_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_wen_0 = io_dec_uops_0_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_ren1_0 = io_dec_uops_0_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_ren2_0 = io_dec_uops_0_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_ren3_0 = io_dec_uops_0_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_swap12_0 = io_dec_uops_0_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_swap23_0 = io_dec_uops_0_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_fp_ctrl_typeTagIn_0 = io_dec_uops_0_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_fp_ctrl_typeTagOut_0 = io_dec_uops_0_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_fromint_0 = io_dec_uops_0_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_toint_0 = io_dec_uops_0_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_fastpipe_0 = io_dec_uops_0_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_fma_0 = io_dec_uops_0_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_div_0 = io_dec_uops_0_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_sqrt_0 = io_dec_uops_0_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_wflags_0 = io_dec_uops_0_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_exception_0 = io_dec_uops_0_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_dec_uops_0_exc_cause_0 = io_dec_uops_0_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_mem_cmd_0 = io_dec_uops_0_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_mem_size_0 = io_dec_uops_0_mem_size; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_mem_signed_0 = io_dec_uops_0_mem_signed; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_uses_ldq_0 = io_dec_uops_0_uses_ldq; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_uses_stq_0 = io_dec_uops_0_uses_stq; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_is_unique_0 = io_dec_uops_0_is_unique; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_flush_on_commit_0 = io_dec_uops_0_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_csr_cmd_0 = io_dec_uops_0_csr_cmd; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_ldst_is_rs1_0 = io_dec_uops_0_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_0_ldst_0 = io_dec_uops_0_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_0_lrs1_0 = io_dec_uops_0_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_0_lrs2_0 = io_dec_uops_0_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_0_lrs3_0 = io_dec_uops_0_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_dst_rtype_0 = io_dec_uops_0_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_lrs1_rtype_0 = io_dec_uops_0_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_lrs2_rtype_0 = io_dec_uops_0_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_frs3_en_0 = io_dec_uops_0_frs3_en; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fcn_dw_0 = io_dec_uops_0_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_fcn_op_0 = io_dec_uops_0_fcn_op; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_val_0 = io_dec_uops_0_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_fp_rm_0 = io_dec_uops_0_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_0_fp_typ_0 = io_dec_uops_0_fp_typ; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_xcpt_pf_if_0 = io_dec_uops_0_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_xcpt_ae_if_0 = io_dec_uops_0_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_bp_debug_if_0 = io_dec_uops_0_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_bp_xcpt_if_0 = io_dec_uops_0_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_debug_fsrc_0 = io_dec_uops_0_debug_fsrc; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_1_inst_0 = io_dec_uops_1_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_1_debug_inst_0 = io_dec_uops_1_debug_inst; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_rvc_0 = io_dec_uops_1_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_dec_uops_1_debug_pc_0 = io_dec_uops_1_debug_pc; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iq_type_0_0 = io_dec_uops_1_iq_type_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iq_type_1_0 = io_dec_uops_1_iq_type_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iq_type_2_0 = io_dec_uops_1_iq_type_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iq_type_3_0 = io_dec_uops_1_iq_type_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_0_0 = io_dec_uops_1_fu_code_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_1_0 = io_dec_uops_1_fu_code_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_2_0 = io_dec_uops_1_fu_code_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_3_0 = io_dec_uops_1_fu_code_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_4_0 = io_dec_uops_1_fu_code_4; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_5_0 = io_dec_uops_1_fu_code_5; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_6_0 = io_dec_uops_1_fu_code_6; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_7_0 = io_dec_uops_1_fu_code_7; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_8_0 = io_dec_uops_1_fu_code_8; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fu_code_9_0 = io_dec_uops_1_fu_code_9; // @[rename-stage.scala:414:7]
wire [15:0] io_dec_uops_1_br_mask_0 = io_dec_uops_1_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_1_br_tag_0 = io_dec_uops_1_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_1_br_type_0 = io_dec_uops_1_br_type; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_sfb_0 = io_dec_uops_1_is_sfb; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_fence_0 = io_dec_uops_1_is_fence; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_fencei_0 = io_dec_uops_1_is_fencei; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_sfence_0 = io_dec_uops_1_is_sfence; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_amo_0 = io_dec_uops_1_is_amo; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_eret_0 = io_dec_uops_1_is_eret; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_sys_pc2epc_0 = io_dec_uops_1_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_rocc_0 = io_dec_uops_1_is_rocc; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_mov_0 = io_dec_uops_1_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_ftq_idx_0 = io_dec_uops_1_ftq_idx; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_edge_inst_0 = io_dec_uops_1_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_1_pc_lob_0 = io_dec_uops_1_pc_lob; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_taken_0 = io_dec_uops_1_taken; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_imm_rename_0 = io_dec_uops_1_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_imm_sel_0 = io_dec_uops_1_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_pimm_0 = io_dec_uops_1_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_dec_uops_1_imm_packed_0 = io_dec_uops_1_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_op1_sel_0 = io_dec_uops_1_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_op2_sel_0 = io_dec_uops_1_op2_sel; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_ldst_0 = io_dec_uops_1_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_wen_0 = io_dec_uops_1_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_ren1_0 = io_dec_uops_1_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_ren2_0 = io_dec_uops_1_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_ren3_0 = io_dec_uops_1_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_swap12_0 = io_dec_uops_1_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_swap23_0 = io_dec_uops_1_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_fp_ctrl_typeTagIn_0 = io_dec_uops_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_fp_ctrl_typeTagOut_0 = io_dec_uops_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_fromint_0 = io_dec_uops_1_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_toint_0 = io_dec_uops_1_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_fastpipe_0 = io_dec_uops_1_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_fma_0 = io_dec_uops_1_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_div_0 = io_dec_uops_1_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_sqrt_0 = io_dec_uops_1_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_wflags_0 = io_dec_uops_1_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_exception_0 = io_dec_uops_1_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_dec_uops_1_exc_cause_0 = io_dec_uops_1_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_mem_cmd_0 = io_dec_uops_1_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_mem_size_0 = io_dec_uops_1_mem_size; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_mem_signed_0 = io_dec_uops_1_mem_signed; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_uses_ldq_0 = io_dec_uops_1_uses_ldq; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_uses_stq_0 = io_dec_uops_1_uses_stq; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_is_unique_0 = io_dec_uops_1_is_unique; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_flush_on_commit_0 = io_dec_uops_1_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_csr_cmd_0 = io_dec_uops_1_csr_cmd; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_ldst_is_rs1_0 = io_dec_uops_1_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_1_ldst_0 = io_dec_uops_1_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_1_lrs1_0 = io_dec_uops_1_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_1_lrs2_0 = io_dec_uops_1_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_1_lrs3_0 = io_dec_uops_1_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_dst_rtype_0 = io_dec_uops_1_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_lrs1_rtype_0 = io_dec_uops_1_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_lrs2_rtype_0 = io_dec_uops_1_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_frs3_en_0 = io_dec_uops_1_frs3_en; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fcn_dw_0 = io_dec_uops_1_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_fcn_op_0 = io_dec_uops_1_fcn_op; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_val_0 = io_dec_uops_1_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_fp_rm_0 = io_dec_uops_1_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_fp_typ_0 = io_dec_uops_1_fp_typ; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_xcpt_pf_if_0 = io_dec_uops_1_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_xcpt_ae_if_0 = io_dec_uops_1_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_bp_debug_if_0 = io_dec_uops_1_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_bp_xcpt_if_0 = io_dec_uops_1_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_debug_fsrc_0 = io_dec_uops_1_debug_fsrc; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_2_inst_0 = io_dec_uops_2_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_dec_uops_2_debug_inst_0 = io_dec_uops_2_debug_inst; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_rvc_0 = io_dec_uops_2_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_dec_uops_2_debug_pc_0 = io_dec_uops_2_debug_pc; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iq_type_0_0 = io_dec_uops_2_iq_type_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iq_type_1_0 = io_dec_uops_2_iq_type_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iq_type_2_0 = io_dec_uops_2_iq_type_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iq_type_3_0 = io_dec_uops_2_iq_type_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_0_0 = io_dec_uops_2_fu_code_0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_1_0 = io_dec_uops_2_fu_code_1; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_2_0 = io_dec_uops_2_fu_code_2; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_3_0 = io_dec_uops_2_fu_code_3; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_4_0 = io_dec_uops_2_fu_code_4; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_5_0 = io_dec_uops_2_fu_code_5; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_6_0 = io_dec_uops_2_fu_code_6; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_7_0 = io_dec_uops_2_fu_code_7; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_8_0 = io_dec_uops_2_fu_code_8; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fu_code_9_0 = io_dec_uops_2_fu_code_9; // @[rename-stage.scala:414:7]
wire [15:0] io_dec_uops_2_br_mask_0 = io_dec_uops_2_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_2_br_tag_0 = io_dec_uops_2_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_dec_uops_2_br_type_0 = io_dec_uops_2_br_type; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_sfb_0 = io_dec_uops_2_is_sfb; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_fence_0 = io_dec_uops_2_is_fence; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_fencei_0 = io_dec_uops_2_is_fencei; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_sfence_0 = io_dec_uops_2_is_sfence; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_amo_0 = io_dec_uops_2_is_amo; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_eret_0 = io_dec_uops_2_is_eret; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_sys_pc2epc_0 = io_dec_uops_2_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_rocc_0 = io_dec_uops_2_is_rocc; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_mov_0 = io_dec_uops_2_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_ftq_idx_0 = io_dec_uops_2_ftq_idx; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_edge_inst_0 = io_dec_uops_2_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_2_pc_lob_0 = io_dec_uops_2_pc_lob; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_taken_0 = io_dec_uops_2_taken; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_imm_rename_0 = io_dec_uops_2_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_imm_sel_0 = io_dec_uops_2_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_pimm_0 = io_dec_uops_2_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_dec_uops_2_imm_packed_0 = io_dec_uops_2_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_op1_sel_0 = io_dec_uops_2_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_op2_sel_0 = io_dec_uops_2_op2_sel; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_ldst_0 = io_dec_uops_2_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_wen_0 = io_dec_uops_2_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_ren1_0 = io_dec_uops_2_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_ren2_0 = io_dec_uops_2_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_ren3_0 = io_dec_uops_2_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_swap12_0 = io_dec_uops_2_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_swap23_0 = io_dec_uops_2_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_fp_ctrl_typeTagIn_0 = io_dec_uops_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_fp_ctrl_typeTagOut_0 = io_dec_uops_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_fromint_0 = io_dec_uops_2_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_toint_0 = io_dec_uops_2_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_fastpipe_0 = io_dec_uops_2_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_fma_0 = io_dec_uops_2_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_div_0 = io_dec_uops_2_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_sqrt_0 = io_dec_uops_2_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_wflags_0 = io_dec_uops_2_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_exception_0 = io_dec_uops_2_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_dec_uops_2_exc_cause_0 = io_dec_uops_2_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_mem_cmd_0 = io_dec_uops_2_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_mem_size_0 = io_dec_uops_2_mem_size; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_mem_signed_0 = io_dec_uops_2_mem_signed; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_uses_ldq_0 = io_dec_uops_2_uses_ldq; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_uses_stq_0 = io_dec_uops_2_uses_stq; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_is_unique_0 = io_dec_uops_2_is_unique; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_flush_on_commit_0 = io_dec_uops_2_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_csr_cmd_0 = io_dec_uops_2_csr_cmd; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_ldst_is_rs1_0 = io_dec_uops_2_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_2_ldst_0 = io_dec_uops_2_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_2_lrs1_0 = io_dec_uops_2_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_2_lrs2_0 = io_dec_uops_2_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_dec_uops_2_lrs3_0 = io_dec_uops_2_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_dst_rtype_0 = io_dec_uops_2_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_lrs1_rtype_0 = io_dec_uops_2_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_lrs2_rtype_0 = io_dec_uops_2_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_frs3_en_0 = io_dec_uops_2_frs3_en; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fcn_dw_0 = io_dec_uops_2_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_fcn_op_0 = io_dec_uops_2_fcn_op; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_val_0 = io_dec_uops_2_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_fp_rm_0 = io_dec_uops_2_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_fp_typ_0 = io_dec_uops_2_fp_typ; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_xcpt_pf_if_0 = io_dec_uops_2_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_xcpt_ae_if_0 = io_dec_uops_2_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_bp_debug_if_0 = io_dec_uops_2_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_bp_xcpt_if_0 = io_dec_uops_2_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_debug_fsrc_0 = io_dec_uops_2_debug_fsrc; // @[rename-stage.scala:414:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-stage.scala:414:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-stage.scala:414:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-stage.scala:414:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-stage.scala:414:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-stage.scala:414:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-stage.scala:414:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-stage.scala:414:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-stage.scala:414:7]
wire io_dis_fire_0_0 = io_dis_fire_0; // @[rename-stage.scala:414:7]
wire io_dis_fire_1_0 = io_dis_fire_1; // @[rename-stage.scala:414:7]
wire io_dis_fire_2_0 = io_dis_fire_2; // @[rename-stage.scala:414:7]
wire io_dis_ready_0 = io_dis_ready; // @[rename-stage.scala:414:7]
wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iq_type_0_0 = io_wakeups_0_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iq_type_1_0 = io_wakeups_0_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iq_type_2_0 = io_wakeups_0_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iq_type_3_0 = io_wakeups_0_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_0_0 = io_wakeups_0_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_1_0 = io_wakeups_0_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_2_0 = io_wakeups_0_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_3_0 = io_wakeups_0_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_4_0 = io_wakeups_0_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_5_0 = io_wakeups_0_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_6_0 = io_wakeups_0_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_7_0 = io_wakeups_0_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_8_0 = io_wakeups_0_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fu_code_9_0 = io_wakeups_0_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_issued_0 = io_wakeups_0_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_dis_col_sel_0 = io_wakeups_0_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_0_bits_uop_br_type_0 = io_wakeups_0_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_sfence_0 = io_wakeups_0_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_eret_0 = io_wakeups_0_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_rocc_0 = io_wakeups_0_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_mov_0 = io_wakeups_0_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_imm_rename_0 = io_wakeups_0_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_imm_sel_0 = io_wakeups_0_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_pimm_0 = io_wakeups_0_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_op1_sel_0 = io_wakeups_0_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_op2_sel_0 = io_wakeups_0_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wen_0 = io_wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_toint_0 = io_wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fma_0 = io_wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_div_0 = io_wakeups_0_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_ctrl_vec_0 = io_wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0 = io_wakeups_0_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fcn_dw_0 = io_wakeups_0_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_0_bits_uop_fcn_op_0 = io_wakeups_0_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_fp_rm_0 = io_wakeups_0_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_0_bits_uop_fp_typ_0 = io_wakeups_0_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iq_type_0_0 = io_wakeups_1_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iq_type_1_0 = io_wakeups_1_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iq_type_2_0 = io_wakeups_1_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iq_type_3_0 = io_wakeups_1_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_0_0 = io_wakeups_1_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_1_0 = io_wakeups_1_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_2_0 = io_wakeups_1_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_3_0 = io_wakeups_1_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_4_0 = io_wakeups_1_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_5_0 = io_wakeups_1_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_6_0 = io_wakeups_1_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_7_0 = io_wakeups_1_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_8_0 = io_wakeups_1_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fu_code_9_0 = io_wakeups_1_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_issued_0 = io_wakeups_1_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_dis_col_sel_0 = io_wakeups_1_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_1_bits_uop_br_type_0 = io_wakeups_1_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_sfence_0 = io_wakeups_1_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_eret_0 = io_wakeups_1_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_rocc_0 = io_wakeups_1_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_mov_0 = io_wakeups_1_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_imm_rename_0 = io_wakeups_1_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_imm_sel_0 = io_wakeups_1_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_pimm_0 = io_wakeups_1_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_op1_sel_0 = io_wakeups_1_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_op2_sel_0 = io_wakeups_1_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wen_0 = io_wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_toint_0 = io_wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fma_0 = io_wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_div_0 = io_wakeups_1_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_ctrl_vec_0 = io_wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0 = io_wakeups_1_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fcn_dw_0 = io_wakeups_1_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_1_bits_uop_fcn_op_0 = io_wakeups_1_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_fp_rm_0 = io_wakeups_1_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_1_bits_uop_fp_typ_0 = io_wakeups_1_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_wakeups_2_valid_0 = io_wakeups_2_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_2_bits_uop_inst_0 = io_wakeups_2_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_2_bits_uop_debug_inst_0 = io_wakeups_2_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_rvc_0 = io_wakeups_2_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_2_bits_uop_debug_pc_0 = io_wakeups_2_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iq_type_0_0 = io_wakeups_2_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iq_type_1_0 = io_wakeups_2_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iq_type_2_0 = io_wakeups_2_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iq_type_3_0 = io_wakeups_2_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_0_0 = io_wakeups_2_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_1_0 = io_wakeups_2_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_2_0 = io_wakeups_2_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_3_0 = io_wakeups_2_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_4_0 = io_wakeups_2_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_5_0 = io_wakeups_2_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_6_0 = io_wakeups_2_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_7_0 = io_wakeups_2_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_8_0 = io_wakeups_2_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fu_code_9_0 = io_wakeups_2_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_issued_0 = io_wakeups_2_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_issued_partial_agen_0 = io_wakeups_2_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_2_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_iw_p1_speculative_child_0 = io_wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_iw_p2_speculative_child_0 = io_wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_dis_col_sel_0 = io_wakeups_2_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_2_bits_uop_br_mask_0 = io_wakeups_2_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_2_bits_uop_br_tag_0 = io_wakeups_2_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_2_bits_uop_br_type_0 = io_wakeups_2_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_sfb_0 = io_wakeups_2_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_fence_0 = io_wakeups_2_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_fencei_0 = io_wakeups_2_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_sfence_0 = io_wakeups_2_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_amo_0 = io_wakeups_2_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_eret_0 = io_wakeups_2_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_sys_pc2epc_0 = io_wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_rocc_0 = io_wakeups_2_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_mov_0 = io_wakeups_2_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_ftq_idx_0 = io_wakeups_2_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_edge_inst_0 = io_wakeups_2_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_2_bits_uop_pc_lob_0 = io_wakeups_2_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_taken_0 = io_wakeups_2_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_imm_rename_0 = io_wakeups_2_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_imm_sel_0 = io_wakeups_2_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_pimm_0 = io_wakeups_2_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_2_bits_uop_imm_packed_0 = io_wakeups_2_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_op1_sel_0 = io_wakeups_2_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_op2_sel_0 = io_wakeups_2_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ldst_0 = io_wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_wen_0 = io_wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren1_0 = io_wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren2_0 = io_wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren3_0 = io_wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_swap12_0 = io_wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_swap23_0 = io_wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fromint_0 = io_wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_toint_0 = io_wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fma_0 = io_wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_div_0 = io_wakeups_2_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_wflags_0 = io_wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_ctrl_vec_0 = io_wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_rob_idx_0 = io_wakeups_2_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_ldq_idx_0 = io_wakeups_2_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_stq_idx_0 = io_wakeups_2_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_rxq_idx_0 = io_wakeups_2_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_pdst_0 = io_wakeups_2_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_prs1_0 = io_wakeups_2_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_prs2_0 = io_wakeups_2_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_prs3_0 = io_wakeups_2_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_ppred_0 = io_wakeups_2_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_prs1_busy_0 = io_wakeups_2_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_prs2_busy_0 = io_wakeups_2_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_prs3_busy_0 = io_wakeups_2_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_ppred_busy_0 = io_wakeups_2_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_2_bits_uop_stale_pdst_0 = io_wakeups_2_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_exception_0 = io_wakeups_2_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_2_bits_uop_exc_cause_0 = io_wakeups_2_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_mem_cmd_0 = io_wakeups_2_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_mem_size_0 = io_wakeups_2_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_mem_signed_0 = io_wakeups_2_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_uses_ldq_0 = io_wakeups_2_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_uses_stq_0 = io_wakeups_2_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_is_unique_0 = io_wakeups_2_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_flush_on_commit_0 = io_wakeups_2_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_csr_cmd_0 = io_wakeups_2_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_ldst_is_rs1_0 = io_wakeups_2_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_2_bits_uop_ldst_0 = io_wakeups_2_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_2_bits_uop_lrs1_0 = io_wakeups_2_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_2_bits_uop_lrs2_0 = io_wakeups_2_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_2_bits_uop_lrs3_0 = io_wakeups_2_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_dst_rtype_0 = io_wakeups_2_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_lrs1_rtype_0 = io_wakeups_2_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_lrs2_rtype_0 = io_wakeups_2_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_frs3_en_0 = io_wakeups_2_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fcn_dw_0 = io_wakeups_2_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_2_bits_uop_fcn_op_0 = io_wakeups_2_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_fp_val_0 = io_wakeups_2_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_fp_rm_0 = io_wakeups_2_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_2_bits_uop_fp_typ_0 = io_wakeups_2_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_xcpt_pf_if_0 = io_wakeups_2_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_xcpt_ae_if_0 = io_wakeups_2_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_xcpt_ma_if_0 = io_wakeups_2_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_bp_debug_if_0 = io_wakeups_2_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_uop_bp_xcpt_if_0 = io_wakeups_2_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_debug_fsrc_0 = io_wakeups_2_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_uop_debug_tsrc_0 = io_wakeups_2_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_wakeups_3_valid_0 = io_wakeups_3_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_3_bits_uop_inst_0 = io_wakeups_3_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_3_bits_uop_debug_inst_0 = io_wakeups_3_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_rvc_0 = io_wakeups_3_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_3_bits_uop_debug_pc_0 = io_wakeups_3_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iq_type_0_0 = io_wakeups_3_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iq_type_1_0 = io_wakeups_3_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iq_type_2_0 = io_wakeups_3_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iq_type_3_0 = io_wakeups_3_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_0_0 = io_wakeups_3_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_1_0 = io_wakeups_3_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_2_0 = io_wakeups_3_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_3_0 = io_wakeups_3_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_4_0 = io_wakeups_3_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_5_0 = io_wakeups_3_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_6_0 = io_wakeups_3_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_7_0 = io_wakeups_3_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_8_0 = io_wakeups_3_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fu_code_9_0 = io_wakeups_3_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_issued_0 = io_wakeups_3_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_issued_partial_agen_0 = io_wakeups_3_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_3_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_iw_p1_speculative_child_0 = io_wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_iw_p2_speculative_child_0 = io_wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_dis_col_sel_0 = io_wakeups_3_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_3_bits_uop_br_mask_0 = io_wakeups_3_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_3_bits_uop_br_tag_0 = io_wakeups_3_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_3_bits_uop_br_type_0 = io_wakeups_3_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_sfb_0 = io_wakeups_3_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_fence_0 = io_wakeups_3_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_fencei_0 = io_wakeups_3_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_sfence_0 = io_wakeups_3_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_amo_0 = io_wakeups_3_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_eret_0 = io_wakeups_3_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_sys_pc2epc_0 = io_wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_rocc_0 = io_wakeups_3_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_mov_0 = io_wakeups_3_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_ftq_idx_0 = io_wakeups_3_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_edge_inst_0 = io_wakeups_3_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_3_bits_uop_pc_lob_0 = io_wakeups_3_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_taken_0 = io_wakeups_3_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_imm_rename_0 = io_wakeups_3_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_imm_sel_0 = io_wakeups_3_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_pimm_0 = io_wakeups_3_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_3_bits_uop_imm_packed_0 = io_wakeups_3_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_op1_sel_0 = io_wakeups_3_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_op2_sel_0 = io_wakeups_3_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ldst_0 = io_wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_wen_0 = io_wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren1_0 = io_wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren2_0 = io_wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren3_0 = io_wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_swap12_0 = io_wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_swap23_0 = io_wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fromint_0 = io_wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_toint_0 = io_wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fma_0 = io_wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_div_0 = io_wakeups_3_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_wflags_0 = io_wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_ctrl_vec_0 = io_wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_rob_idx_0 = io_wakeups_3_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_ldq_idx_0 = io_wakeups_3_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_stq_idx_0 = io_wakeups_3_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_rxq_idx_0 = io_wakeups_3_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_pdst_0 = io_wakeups_3_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_prs1_0 = io_wakeups_3_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_prs2_0 = io_wakeups_3_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_prs3_0 = io_wakeups_3_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_ppred_0 = io_wakeups_3_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_prs1_busy_0 = io_wakeups_3_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_prs2_busy_0 = io_wakeups_3_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_prs3_busy_0 = io_wakeups_3_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_ppred_busy_0 = io_wakeups_3_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_3_bits_uop_stale_pdst_0 = io_wakeups_3_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_exception_0 = io_wakeups_3_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_3_bits_uop_exc_cause_0 = io_wakeups_3_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_mem_cmd_0 = io_wakeups_3_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_mem_size_0 = io_wakeups_3_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_mem_signed_0 = io_wakeups_3_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_uses_ldq_0 = io_wakeups_3_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_uses_stq_0 = io_wakeups_3_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_is_unique_0 = io_wakeups_3_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_flush_on_commit_0 = io_wakeups_3_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_csr_cmd_0 = io_wakeups_3_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_ldst_is_rs1_0 = io_wakeups_3_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_3_bits_uop_ldst_0 = io_wakeups_3_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_3_bits_uop_lrs1_0 = io_wakeups_3_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_3_bits_uop_lrs2_0 = io_wakeups_3_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_3_bits_uop_lrs3_0 = io_wakeups_3_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_dst_rtype_0 = io_wakeups_3_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_lrs1_rtype_0 = io_wakeups_3_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_lrs2_rtype_0 = io_wakeups_3_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_frs3_en_0 = io_wakeups_3_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fcn_dw_0 = io_wakeups_3_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_3_bits_uop_fcn_op_0 = io_wakeups_3_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_fp_val_0 = io_wakeups_3_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_fp_rm_0 = io_wakeups_3_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_3_bits_uop_fp_typ_0 = io_wakeups_3_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_xcpt_pf_if_0 = io_wakeups_3_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_xcpt_ae_if_0 = io_wakeups_3_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_xcpt_ma_if_0 = io_wakeups_3_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_bp_debug_if_0 = io_wakeups_3_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_uop_bp_xcpt_if_0 = io_wakeups_3_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_debug_fsrc_0 = io_wakeups_3_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_uop_debug_tsrc_0 = io_wakeups_3_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_wakeups_4_valid_0 = io_wakeups_4_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_4_bits_uop_inst_0 = io_wakeups_4_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_4_bits_uop_debug_inst_0 = io_wakeups_4_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_rvc_0 = io_wakeups_4_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_4_bits_uop_debug_pc_0 = io_wakeups_4_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iq_type_0_0 = io_wakeups_4_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iq_type_1_0 = io_wakeups_4_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iq_type_2_0 = io_wakeups_4_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iq_type_3_0 = io_wakeups_4_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_0_0 = io_wakeups_4_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_1_0 = io_wakeups_4_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_2_0 = io_wakeups_4_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_3_0 = io_wakeups_4_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_4_0 = io_wakeups_4_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_5_0 = io_wakeups_4_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_6_0 = io_wakeups_4_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_7_0 = io_wakeups_4_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_8_0 = io_wakeups_4_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fu_code_9_0 = io_wakeups_4_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_issued_0 = io_wakeups_4_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_issued_partial_agen_0 = io_wakeups_4_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_4_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_iw_p1_speculative_child_0 = io_wakeups_4_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_iw_p2_speculative_child_0 = io_wakeups_4_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_dis_col_sel_0 = io_wakeups_4_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_4_bits_uop_br_mask_0 = io_wakeups_4_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_4_bits_uop_br_tag_0 = io_wakeups_4_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_4_bits_uop_br_type_0 = io_wakeups_4_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_sfb_0 = io_wakeups_4_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_fence_0 = io_wakeups_4_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_fencei_0 = io_wakeups_4_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_sfence_0 = io_wakeups_4_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_amo_0 = io_wakeups_4_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_eret_0 = io_wakeups_4_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_sys_pc2epc_0 = io_wakeups_4_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_rocc_0 = io_wakeups_4_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_mov_0 = io_wakeups_4_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_ftq_idx_0 = io_wakeups_4_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_edge_inst_0 = io_wakeups_4_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_4_bits_uop_pc_lob_0 = io_wakeups_4_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_taken_0 = io_wakeups_4_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_imm_rename_0 = io_wakeups_4_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_imm_sel_0 = io_wakeups_4_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_pimm_0 = io_wakeups_4_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_4_bits_uop_imm_packed_0 = io_wakeups_4_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_op1_sel_0 = io_wakeups_4_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_op2_sel_0 = io_wakeups_4_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ldst_0 = io_wakeups_4_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_wen_0 = io_wakeups_4_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren1_0 = io_wakeups_4_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren2_0 = io_wakeups_4_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren3_0 = io_wakeups_4_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_swap12_0 = io_wakeups_4_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_swap23_0 = io_wakeups_4_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_4_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_4_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fromint_0 = io_wakeups_4_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_toint_0 = io_wakeups_4_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_4_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fma_0 = io_wakeups_4_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_div_0 = io_wakeups_4_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_4_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_wflags_0 = io_wakeups_4_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_ctrl_vec_0 = io_wakeups_4_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_rob_idx_0 = io_wakeups_4_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_ldq_idx_0 = io_wakeups_4_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_stq_idx_0 = io_wakeups_4_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_rxq_idx_0 = io_wakeups_4_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_pdst_0 = io_wakeups_4_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_prs1_0 = io_wakeups_4_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_prs2_0 = io_wakeups_4_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_prs3_0 = io_wakeups_4_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_ppred_0 = io_wakeups_4_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_prs1_busy_0 = io_wakeups_4_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_prs2_busy_0 = io_wakeups_4_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_prs3_busy_0 = io_wakeups_4_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_ppred_busy_0 = io_wakeups_4_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_4_bits_uop_stale_pdst_0 = io_wakeups_4_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_exception_0 = io_wakeups_4_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_4_bits_uop_exc_cause_0 = io_wakeups_4_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_mem_cmd_0 = io_wakeups_4_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_mem_size_0 = io_wakeups_4_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_mem_signed_0 = io_wakeups_4_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_uses_ldq_0 = io_wakeups_4_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_uses_stq_0 = io_wakeups_4_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_is_unique_0 = io_wakeups_4_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_flush_on_commit_0 = io_wakeups_4_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_csr_cmd_0 = io_wakeups_4_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_ldst_is_rs1_0 = io_wakeups_4_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_4_bits_uop_ldst_0 = io_wakeups_4_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_4_bits_uop_lrs1_0 = io_wakeups_4_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_4_bits_uop_lrs2_0 = io_wakeups_4_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_4_bits_uop_lrs3_0 = io_wakeups_4_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_dst_rtype_0 = io_wakeups_4_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_lrs1_rtype_0 = io_wakeups_4_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_lrs2_rtype_0 = io_wakeups_4_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_frs3_en_0 = io_wakeups_4_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fcn_dw_0 = io_wakeups_4_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_4_bits_uop_fcn_op_0 = io_wakeups_4_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_fp_val_0 = io_wakeups_4_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_fp_rm_0 = io_wakeups_4_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_4_bits_uop_fp_typ_0 = io_wakeups_4_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_xcpt_pf_if_0 = io_wakeups_4_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_xcpt_ae_if_0 = io_wakeups_4_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_xcpt_ma_if_0 = io_wakeups_4_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_bp_debug_if_0 = io_wakeups_4_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_uop_bp_xcpt_if_0 = io_wakeups_4_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_debug_fsrc_0 = io_wakeups_4_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_uop_debug_tsrc_0 = io_wakeups_4_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_wakeups_5_valid_0 = io_wakeups_5_valid; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_5_bits_uop_inst_0 = io_wakeups_5_bits_uop_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_wakeups_5_bits_uop_debug_inst_0 = io_wakeups_5_bits_uop_debug_inst; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_rvc_0 = io_wakeups_5_bits_uop_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_wakeups_5_bits_uop_debug_pc_0 = io_wakeups_5_bits_uop_debug_pc; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iq_type_0_0 = io_wakeups_5_bits_uop_iq_type_0; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iq_type_1_0 = io_wakeups_5_bits_uop_iq_type_1; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iq_type_2_0 = io_wakeups_5_bits_uop_iq_type_2; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iq_type_3_0 = io_wakeups_5_bits_uop_iq_type_3; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_0_0 = io_wakeups_5_bits_uop_fu_code_0; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_1_0 = io_wakeups_5_bits_uop_fu_code_1; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_2_0 = io_wakeups_5_bits_uop_fu_code_2; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_3_0 = io_wakeups_5_bits_uop_fu_code_3; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_4_0 = io_wakeups_5_bits_uop_fu_code_4; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_5_0 = io_wakeups_5_bits_uop_fu_code_5; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_6_0 = io_wakeups_5_bits_uop_fu_code_6; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_7_0 = io_wakeups_5_bits_uop_fu_code_7; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_8_0 = io_wakeups_5_bits_uop_fu_code_8; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fu_code_9_0 = io_wakeups_5_bits_uop_fu_code_9; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_issued_0 = io_wakeups_5_bits_uop_iw_issued; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_issued_partial_agen_0 = io_wakeups_5_bits_uop_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_5_bits_uop_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_iw_p1_speculative_child_0 = io_wakeups_5_bits_uop_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_iw_p2_speculative_child_0 = io_wakeups_5_bits_uop_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_5_bits_uop_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_5_bits_uop_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_5_bits_uop_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_dis_col_sel_0 = io_wakeups_5_bits_uop_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_wakeups_5_bits_uop_br_mask_0 = io_wakeups_5_bits_uop_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_5_bits_uop_br_tag_0 = io_wakeups_5_bits_uop_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_wakeups_5_bits_uop_br_type_0 = io_wakeups_5_bits_uop_br_type; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_sfb_0 = io_wakeups_5_bits_uop_is_sfb; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_fence_0 = io_wakeups_5_bits_uop_is_fence; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_fencei_0 = io_wakeups_5_bits_uop_is_fencei; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_sfence_0 = io_wakeups_5_bits_uop_is_sfence; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_amo_0 = io_wakeups_5_bits_uop_is_amo; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_eret_0 = io_wakeups_5_bits_uop_is_eret; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_sys_pc2epc_0 = io_wakeups_5_bits_uop_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_rocc_0 = io_wakeups_5_bits_uop_is_rocc; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_mov_0 = io_wakeups_5_bits_uop_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_ftq_idx_0 = io_wakeups_5_bits_uop_ftq_idx; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_edge_inst_0 = io_wakeups_5_bits_uop_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_5_bits_uop_pc_lob_0 = io_wakeups_5_bits_uop_pc_lob; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_taken_0 = io_wakeups_5_bits_uop_taken; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_imm_rename_0 = io_wakeups_5_bits_uop_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_imm_sel_0 = io_wakeups_5_bits_uop_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_pimm_0 = io_wakeups_5_bits_uop_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_wakeups_5_bits_uop_imm_packed_0 = io_wakeups_5_bits_uop_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_op1_sel_0 = io_wakeups_5_bits_uop_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_op2_sel_0 = io_wakeups_5_bits_uop_op2_sel; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_ldst_0 = io_wakeups_5_bits_uop_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_wen_0 = io_wakeups_5_bits_uop_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_ren1_0 = io_wakeups_5_bits_uop_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_ren2_0 = io_wakeups_5_bits_uop_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_ren3_0 = io_wakeups_5_bits_uop_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_swap12_0 = io_wakeups_5_bits_uop_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_swap23_0 = io_wakeups_5_bits_uop_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_5_bits_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_5_bits_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_fromint_0 = io_wakeups_5_bits_uop_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_toint_0 = io_wakeups_5_bits_uop_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_5_bits_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_fma_0 = io_wakeups_5_bits_uop_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_div_0 = io_wakeups_5_bits_uop_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_5_bits_uop_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_wflags_0 = io_wakeups_5_bits_uop_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_ctrl_vec_0 = io_wakeups_5_bits_uop_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_rob_idx_0 = io_wakeups_5_bits_uop_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_ldq_idx_0 = io_wakeups_5_bits_uop_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_stq_idx_0 = io_wakeups_5_bits_uop_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_rxq_idx_0 = io_wakeups_5_bits_uop_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_pdst_0 = io_wakeups_5_bits_uop_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_prs1_0 = io_wakeups_5_bits_uop_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_prs2_0 = io_wakeups_5_bits_uop_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_prs3_0 = io_wakeups_5_bits_uop_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_ppred_0 = io_wakeups_5_bits_uop_ppred; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_prs1_busy_0 = io_wakeups_5_bits_uop_prs1_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_prs2_busy_0 = io_wakeups_5_bits_uop_prs2_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_prs3_busy_0 = io_wakeups_5_bits_uop_prs3_busy; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_ppred_busy_0 = io_wakeups_5_bits_uop_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_wakeups_5_bits_uop_stale_pdst_0 = io_wakeups_5_bits_uop_stale_pdst; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_exception_0 = io_wakeups_5_bits_uop_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_wakeups_5_bits_uop_exc_cause_0 = io_wakeups_5_bits_uop_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_mem_cmd_0 = io_wakeups_5_bits_uop_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_mem_size_0 = io_wakeups_5_bits_uop_mem_size; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_mem_signed_0 = io_wakeups_5_bits_uop_mem_signed; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_uses_ldq_0 = io_wakeups_5_bits_uop_uses_ldq; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_uses_stq_0 = io_wakeups_5_bits_uop_uses_stq; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_is_unique_0 = io_wakeups_5_bits_uop_is_unique; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_flush_on_commit_0 = io_wakeups_5_bits_uop_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_csr_cmd_0 = io_wakeups_5_bits_uop_csr_cmd; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_ldst_is_rs1_0 = io_wakeups_5_bits_uop_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_5_bits_uop_ldst_0 = io_wakeups_5_bits_uop_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_5_bits_uop_lrs1_0 = io_wakeups_5_bits_uop_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_5_bits_uop_lrs2_0 = io_wakeups_5_bits_uop_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_wakeups_5_bits_uop_lrs3_0 = io_wakeups_5_bits_uop_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_dst_rtype_0 = io_wakeups_5_bits_uop_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_lrs1_rtype_0 = io_wakeups_5_bits_uop_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_lrs2_rtype_0 = io_wakeups_5_bits_uop_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_frs3_en_0 = io_wakeups_5_bits_uop_frs3_en; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fcn_dw_0 = io_wakeups_5_bits_uop_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_wakeups_5_bits_uop_fcn_op_0 = io_wakeups_5_bits_uop_fcn_op; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_fp_val_0 = io_wakeups_5_bits_uop_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_fp_rm_0 = io_wakeups_5_bits_uop_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_wakeups_5_bits_uop_fp_typ_0 = io_wakeups_5_bits_uop_fp_typ; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_xcpt_pf_if_0 = io_wakeups_5_bits_uop_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_xcpt_ae_if_0 = io_wakeups_5_bits_uop_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_xcpt_ma_if_0 = io_wakeups_5_bits_uop_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_bp_debug_if_0 = io_wakeups_5_bits_uop_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_uop_bp_xcpt_if_0 = io_wakeups_5_bits_uop_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_debug_fsrc_0 = io_wakeups_5_bits_uop_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_uop_debug_tsrc_0 = io_wakeups_5_bits_uop_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_com_valids_0_0 = io_com_valids_0; // @[rename-stage.scala:414:7]
wire io_com_valids_1_0 = io_com_valids_1; // @[rename-stage.scala:414:7]
wire io_com_valids_2_0 = io_com_valids_2; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_0_inst_0 = io_com_uops_0_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_0_debug_inst_0 = io_com_uops_0_debug_inst; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_rvc_0 = io_com_uops_0_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_com_uops_0_debug_pc_0 = io_com_uops_0_debug_pc; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iq_type_0_0 = io_com_uops_0_iq_type_0; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iq_type_1_0 = io_com_uops_0_iq_type_1; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iq_type_2_0 = io_com_uops_0_iq_type_2; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iq_type_3_0 = io_com_uops_0_iq_type_3; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_0_0 = io_com_uops_0_fu_code_0; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_1_0 = io_com_uops_0_fu_code_1; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_2_0 = io_com_uops_0_fu_code_2; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_3_0 = io_com_uops_0_fu_code_3; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_4_0 = io_com_uops_0_fu_code_4; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_5_0 = io_com_uops_0_fu_code_5; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_6_0 = io_com_uops_0_fu_code_6; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_7_0 = io_com_uops_0_fu_code_7; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_8_0 = io_com_uops_0_fu_code_8; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fu_code_9_0 = io_com_uops_0_fu_code_9; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_issued_0 = io_com_uops_0_iw_issued; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_issued_partial_agen_0 = io_com_uops_0_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_issued_partial_dgen_0 = io_com_uops_0_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_iw_p1_speculative_child_0 = io_com_uops_0_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_iw_p2_speculative_child_0 = io_com_uops_0_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_p1_bypass_hint_0 = io_com_uops_0_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_p2_bypass_hint_0 = io_com_uops_0_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_0_iw_p3_bypass_hint_0 = io_com_uops_0_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_dis_col_sel_0 = io_com_uops_0_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_com_uops_0_br_mask_0 = io_com_uops_0_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_0_br_tag_0 = io_com_uops_0_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_0_br_type_0 = io_com_uops_0_br_type; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_sfb_0 = io_com_uops_0_is_sfb; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_fence_0 = io_com_uops_0_is_fence; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_fencei_0 = io_com_uops_0_is_fencei; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_sfence_0 = io_com_uops_0_is_sfence; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_amo_0 = io_com_uops_0_is_amo; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_eret_0 = io_com_uops_0_is_eret; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_sys_pc2epc_0 = io_com_uops_0_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_rocc_0 = io_com_uops_0_is_rocc; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_mov_0 = io_com_uops_0_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_ftq_idx_0 = io_com_uops_0_ftq_idx; // @[rename-stage.scala:414:7]
wire io_com_uops_0_edge_inst_0 = io_com_uops_0_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_0_pc_lob_0 = io_com_uops_0_pc_lob; // @[rename-stage.scala:414:7]
wire io_com_uops_0_taken_0 = io_com_uops_0_taken; // @[rename-stage.scala:414:7]
wire io_com_uops_0_imm_rename_0 = io_com_uops_0_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_imm_sel_0 = io_com_uops_0_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_pimm_0 = io_com_uops_0_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_com_uops_0_imm_packed_0 = io_com_uops_0_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_op1_sel_0 = io_com_uops_0_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_op2_sel_0 = io_com_uops_0_op2_sel; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_ldst_0 = io_com_uops_0_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_wen_0 = io_com_uops_0_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_ren1_0 = io_com_uops_0_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_ren2_0 = io_com_uops_0_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_ren3_0 = io_com_uops_0_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_swap12_0 = io_com_uops_0_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_swap23_0 = io_com_uops_0_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_fp_ctrl_typeTagIn_0 = io_com_uops_0_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_fp_ctrl_typeTagOut_0 = io_com_uops_0_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_fromint_0 = io_com_uops_0_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_toint_0 = io_com_uops_0_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_fastpipe_0 = io_com_uops_0_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_fma_0 = io_com_uops_0_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_div_0 = io_com_uops_0_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_sqrt_0 = io_com_uops_0_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_wflags_0 = io_com_uops_0_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_ctrl_vec_0 = io_com_uops_0_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_rob_idx_0 = io_com_uops_0_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_ldq_idx_0 = io_com_uops_0_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_stq_idx_0 = io_com_uops_0_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_rxq_idx_0 = io_com_uops_0_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_pdst_0 = io_com_uops_0_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_prs1_0 = io_com_uops_0_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_prs2_0 = io_com_uops_0_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_prs3_0 = io_com_uops_0_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_ppred_0 = io_com_uops_0_ppred; // @[rename-stage.scala:414:7]
wire io_com_uops_0_prs1_busy_0 = io_com_uops_0_prs1_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_0_prs2_busy_0 = io_com_uops_0_prs2_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_0_prs3_busy_0 = io_com_uops_0_prs3_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_0_ppred_busy_0 = io_com_uops_0_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_0_stale_pdst_0 = io_com_uops_0_stale_pdst; // @[rename-stage.scala:414:7]
wire io_com_uops_0_exception_0 = io_com_uops_0_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_com_uops_0_exc_cause_0 = io_com_uops_0_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_mem_cmd_0 = io_com_uops_0_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_mem_size_0 = io_com_uops_0_mem_size; // @[rename-stage.scala:414:7]
wire io_com_uops_0_mem_signed_0 = io_com_uops_0_mem_signed; // @[rename-stage.scala:414:7]
wire io_com_uops_0_uses_ldq_0 = io_com_uops_0_uses_ldq; // @[rename-stage.scala:414:7]
wire io_com_uops_0_uses_stq_0 = io_com_uops_0_uses_stq; // @[rename-stage.scala:414:7]
wire io_com_uops_0_is_unique_0 = io_com_uops_0_is_unique; // @[rename-stage.scala:414:7]
wire io_com_uops_0_flush_on_commit_0 = io_com_uops_0_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_csr_cmd_0 = io_com_uops_0_csr_cmd; // @[rename-stage.scala:414:7]
wire io_com_uops_0_ldst_is_rs1_0 = io_com_uops_0_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_0_ldst_0 = io_com_uops_0_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_0_lrs1_0 = io_com_uops_0_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_0_lrs2_0 = io_com_uops_0_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_0_lrs3_0 = io_com_uops_0_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_dst_rtype_0 = io_com_uops_0_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_lrs1_rtype_0 = io_com_uops_0_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_lrs2_rtype_0 = io_com_uops_0_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_com_uops_0_frs3_en_0 = io_com_uops_0_frs3_en; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fcn_dw_0 = io_com_uops_0_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_0_fcn_op_0 = io_com_uops_0_fcn_op; // @[rename-stage.scala:414:7]
wire io_com_uops_0_fp_val_0 = io_com_uops_0_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_fp_rm_0 = io_com_uops_0_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_0_fp_typ_0 = io_com_uops_0_fp_typ; // @[rename-stage.scala:414:7]
wire io_com_uops_0_xcpt_pf_if_0 = io_com_uops_0_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_com_uops_0_xcpt_ae_if_0 = io_com_uops_0_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_com_uops_0_xcpt_ma_if_0 = io_com_uops_0_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_com_uops_0_bp_debug_if_0 = io_com_uops_0_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_com_uops_0_bp_xcpt_if_0 = io_com_uops_0_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_debug_fsrc_0 = io_com_uops_0_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_0_debug_tsrc_0 = io_com_uops_0_debug_tsrc; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_1_inst_0 = io_com_uops_1_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_1_debug_inst_0 = io_com_uops_1_debug_inst; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_rvc_0 = io_com_uops_1_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_com_uops_1_debug_pc_0 = io_com_uops_1_debug_pc; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iq_type_0_0 = io_com_uops_1_iq_type_0; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iq_type_1_0 = io_com_uops_1_iq_type_1; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iq_type_2_0 = io_com_uops_1_iq_type_2; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iq_type_3_0 = io_com_uops_1_iq_type_3; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_0_0 = io_com_uops_1_fu_code_0; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_1_0 = io_com_uops_1_fu_code_1; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_2_0 = io_com_uops_1_fu_code_2; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_3_0 = io_com_uops_1_fu_code_3; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_4_0 = io_com_uops_1_fu_code_4; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_5_0 = io_com_uops_1_fu_code_5; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_6_0 = io_com_uops_1_fu_code_6; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_7_0 = io_com_uops_1_fu_code_7; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_8_0 = io_com_uops_1_fu_code_8; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fu_code_9_0 = io_com_uops_1_fu_code_9; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_issued_0 = io_com_uops_1_iw_issued; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_issued_partial_agen_0 = io_com_uops_1_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_issued_partial_dgen_0 = io_com_uops_1_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_iw_p1_speculative_child_0 = io_com_uops_1_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_iw_p2_speculative_child_0 = io_com_uops_1_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_p1_bypass_hint_0 = io_com_uops_1_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_p2_bypass_hint_0 = io_com_uops_1_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_1_iw_p3_bypass_hint_0 = io_com_uops_1_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_dis_col_sel_0 = io_com_uops_1_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_com_uops_1_br_mask_0 = io_com_uops_1_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_1_br_tag_0 = io_com_uops_1_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_1_br_type_0 = io_com_uops_1_br_type; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_sfb_0 = io_com_uops_1_is_sfb; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_fence_0 = io_com_uops_1_is_fence; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_fencei_0 = io_com_uops_1_is_fencei; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_sfence_0 = io_com_uops_1_is_sfence; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_amo_0 = io_com_uops_1_is_amo; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_eret_0 = io_com_uops_1_is_eret; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_sys_pc2epc_0 = io_com_uops_1_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_rocc_0 = io_com_uops_1_is_rocc; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_mov_0 = io_com_uops_1_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_ftq_idx_0 = io_com_uops_1_ftq_idx; // @[rename-stage.scala:414:7]
wire io_com_uops_1_edge_inst_0 = io_com_uops_1_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_1_pc_lob_0 = io_com_uops_1_pc_lob; // @[rename-stage.scala:414:7]
wire io_com_uops_1_taken_0 = io_com_uops_1_taken; // @[rename-stage.scala:414:7]
wire io_com_uops_1_imm_rename_0 = io_com_uops_1_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_imm_sel_0 = io_com_uops_1_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_pimm_0 = io_com_uops_1_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_com_uops_1_imm_packed_0 = io_com_uops_1_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_op1_sel_0 = io_com_uops_1_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_op2_sel_0 = io_com_uops_1_op2_sel; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_ldst_0 = io_com_uops_1_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_wen_0 = io_com_uops_1_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_ren1_0 = io_com_uops_1_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_ren2_0 = io_com_uops_1_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_ren3_0 = io_com_uops_1_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_swap12_0 = io_com_uops_1_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_swap23_0 = io_com_uops_1_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_fp_ctrl_typeTagIn_0 = io_com_uops_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_fp_ctrl_typeTagOut_0 = io_com_uops_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_fromint_0 = io_com_uops_1_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_toint_0 = io_com_uops_1_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_fastpipe_0 = io_com_uops_1_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_fma_0 = io_com_uops_1_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_div_0 = io_com_uops_1_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_sqrt_0 = io_com_uops_1_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_wflags_0 = io_com_uops_1_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_ctrl_vec_0 = io_com_uops_1_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_rob_idx_0 = io_com_uops_1_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_ldq_idx_0 = io_com_uops_1_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_stq_idx_0 = io_com_uops_1_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_rxq_idx_0 = io_com_uops_1_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_pdst_0 = io_com_uops_1_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_prs1_0 = io_com_uops_1_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_prs2_0 = io_com_uops_1_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_prs3_0 = io_com_uops_1_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_ppred_0 = io_com_uops_1_ppred; // @[rename-stage.scala:414:7]
wire io_com_uops_1_prs1_busy_0 = io_com_uops_1_prs1_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_1_prs2_busy_0 = io_com_uops_1_prs2_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_1_prs3_busy_0 = io_com_uops_1_prs3_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_1_ppred_busy_0 = io_com_uops_1_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_1_stale_pdst_0 = io_com_uops_1_stale_pdst; // @[rename-stage.scala:414:7]
wire io_com_uops_1_exception_0 = io_com_uops_1_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_com_uops_1_exc_cause_0 = io_com_uops_1_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_mem_cmd_0 = io_com_uops_1_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_mem_size_0 = io_com_uops_1_mem_size; // @[rename-stage.scala:414:7]
wire io_com_uops_1_mem_signed_0 = io_com_uops_1_mem_signed; // @[rename-stage.scala:414:7]
wire io_com_uops_1_uses_ldq_0 = io_com_uops_1_uses_ldq; // @[rename-stage.scala:414:7]
wire io_com_uops_1_uses_stq_0 = io_com_uops_1_uses_stq; // @[rename-stage.scala:414:7]
wire io_com_uops_1_is_unique_0 = io_com_uops_1_is_unique; // @[rename-stage.scala:414:7]
wire io_com_uops_1_flush_on_commit_0 = io_com_uops_1_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_csr_cmd_0 = io_com_uops_1_csr_cmd; // @[rename-stage.scala:414:7]
wire io_com_uops_1_ldst_is_rs1_0 = io_com_uops_1_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_1_ldst_0 = io_com_uops_1_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_1_lrs1_0 = io_com_uops_1_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_1_lrs2_0 = io_com_uops_1_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_1_lrs3_0 = io_com_uops_1_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_dst_rtype_0 = io_com_uops_1_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_lrs1_rtype_0 = io_com_uops_1_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_lrs2_rtype_0 = io_com_uops_1_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_com_uops_1_frs3_en_0 = io_com_uops_1_frs3_en; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fcn_dw_0 = io_com_uops_1_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_1_fcn_op_0 = io_com_uops_1_fcn_op; // @[rename-stage.scala:414:7]
wire io_com_uops_1_fp_val_0 = io_com_uops_1_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_fp_rm_0 = io_com_uops_1_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_1_fp_typ_0 = io_com_uops_1_fp_typ; // @[rename-stage.scala:414:7]
wire io_com_uops_1_xcpt_pf_if_0 = io_com_uops_1_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_com_uops_1_xcpt_ae_if_0 = io_com_uops_1_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_com_uops_1_xcpt_ma_if_0 = io_com_uops_1_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_com_uops_1_bp_debug_if_0 = io_com_uops_1_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_com_uops_1_bp_xcpt_if_0 = io_com_uops_1_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_debug_fsrc_0 = io_com_uops_1_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_1_debug_tsrc_0 = io_com_uops_1_debug_tsrc; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_2_inst_0 = io_com_uops_2_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_com_uops_2_debug_inst_0 = io_com_uops_2_debug_inst; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_rvc_0 = io_com_uops_2_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_com_uops_2_debug_pc_0 = io_com_uops_2_debug_pc; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iq_type_0_0 = io_com_uops_2_iq_type_0; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iq_type_1_0 = io_com_uops_2_iq_type_1; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iq_type_2_0 = io_com_uops_2_iq_type_2; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iq_type_3_0 = io_com_uops_2_iq_type_3; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_0_0 = io_com_uops_2_fu_code_0; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_1_0 = io_com_uops_2_fu_code_1; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_2_0 = io_com_uops_2_fu_code_2; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_3_0 = io_com_uops_2_fu_code_3; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_4_0 = io_com_uops_2_fu_code_4; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_5_0 = io_com_uops_2_fu_code_5; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_6_0 = io_com_uops_2_fu_code_6; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_7_0 = io_com_uops_2_fu_code_7; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_8_0 = io_com_uops_2_fu_code_8; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fu_code_9_0 = io_com_uops_2_fu_code_9; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_issued_0 = io_com_uops_2_iw_issued; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_issued_partial_agen_0 = io_com_uops_2_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_issued_partial_dgen_0 = io_com_uops_2_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_iw_p1_speculative_child_0 = io_com_uops_2_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_iw_p2_speculative_child_0 = io_com_uops_2_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_p1_bypass_hint_0 = io_com_uops_2_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_p2_bypass_hint_0 = io_com_uops_2_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_com_uops_2_iw_p3_bypass_hint_0 = io_com_uops_2_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_dis_col_sel_0 = io_com_uops_2_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_com_uops_2_br_mask_0 = io_com_uops_2_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_2_br_tag_0 = io_com_uops_2_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_com_uops_2_br_type_0 = io_com_uops_2_br_type; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_sfb_0 = io_com_uops_2_is_sfb; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_fence_0 = io_com_uops_2_is_fence; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_fencei_0 = io_com_uops_2_is_fencei; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_sfence_0 = io_com_uops_2_is_sfence; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_amo_0 = io_com_uops_2_is_amo; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_eret_0 = io_com_uops_2_is_eret; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_sys_pc2epc_0 = io_com_uops_2_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_rocc_0 = io_com_uops_2_is_rocc; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_mov_0 = io_com_uops_2_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_ftq_idx_0 = io_com_uops_2_ftq_idx; // @[rename-stage.scala:414:7]
wire io_com_uops_2_edge_inst_0 = io_com_uops_2_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_2_pc_lob_0 = io_com_uops_2_pc_lob; // @[rename-stage.scala:414:7]
wire io_com_uops_2_taken_0 = io_com_uops_2_taken; // @[rename-stage.scala:414:7]
wire io_com_uops_2_imm_rename_0 = io_com_uops_2_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_imm_sel_0 = io_com_uops_2_imm_sel; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_pimm_0 = io_com_uops_2_pimm; // @[rename-stage.scala:414:7]
wire [19:0] io_com_uops_2_imm_packed_0 = io_com_uops_2_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_op1_sel_0 = io_com_uops_2_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_op2_sel_0 = io_com_uops_2_op2_sel; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_ldst_0 = io_com_uops_2_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_wen_0 = io_com_uops_2_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_ren1_0 = io_com_uops_2_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_ren2_0 = io_com_uops_2_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_ren3_0 = io_com_uops_2_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_swap12_0 = io_com_uops_2_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_swap23_0 = io_com_uops_2_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_fp_ctrl_typeTagIn_0 = io_com_uops_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_fp_ctrl_typeTagOut_0 = io_com_uops_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_fromint_0 = io_com_uops_2_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_toint_0 = io_com_uops_2_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_fastpipe_0 = io_com_uops_2_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_fma_0 = io_com_uops_2_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_div_0 = io_com_uops_2_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_sqrt_0 = io_com_uops_2_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_wflags_0 = io_com_uops_2_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_ctrl_vec_0 = io_com_uops_2_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_rob_idx_0 = io_com_uops_2_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_ldq_idx_0 = io_com_uops_2_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_stq_idx_0 = io_com_uops_2_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_rxq_idx_0 = io_com_uops_2_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_pdst_0 = io_com_uops_2_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_prs1_0 = io_com_uops_2_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_prs2_0 = io_com_uops_2_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_prs3_0 = io_com_uops_2_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_ppred_0 = io_com_uops_2_ppred; // @[rename-stage.scala:414:7]
wire io_com_uops_2_prs1_busy_0 = io_com_uops_2_prs1_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_2_prs2_busy_0 = io_com_uops_2_prs2_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_2_prs3_busy_0 = io_com_uops_2_prs3_busy; // @[rename-stage.scala:414:7]
wire io_com_uops_2_ppred_busy_0 = io_com_uops_2_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_com_uops_2_stale_pdst_0 = io_com_uops_2_stale_pdst; // @[rename-stage.scala:414:7]
wire io_com_uops_2_exception_0 = io_com_uops_2_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_com_uops_2_exc_cause_0 = io_com_uops_2_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_mem_cmd_0 = io_com_uops_2_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_mem_size_0 = io_com_uops_2_mem_size; // @[rename-stage.scala:414:7]
wire io_com_uops_2_mem_signed_0 = io_com_uops_2_mem_signed; // @[rename-stage.scala:414:7]
wire io_com_uops_2_uses_ldq_0 = io_com_uops_2_uses_ldq; // @[rename-stage.scala:414:7]
wire io_com_uops_2_uses_stq_0 = io_com_uops_2_uses_stq; // @[rename-stage.scala:414:7]
wire io_com_uops_2_is_unique_0 = io_com_uops_2_is_unique; // @[rename-stage.scala:414:7]
wire io_com_uops_2_flush_on_commit_0 = io_com_uops_2_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_csr_cmd_0 = io_com_uops_2_csr_cmd; // @[rename-stage.scala:414:7]
wire io_com_uops_2_ldst_is_rs1_0 = io_com_uops_2_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_2_ldst_0 = io_com_uops_2_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_2_lrs1_0 = io_com_uops_2_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_2_lrs2_0 = io_com_uops_2_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_com_uops_2_lrs3_0 = io_com_uops_2_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_dst_rtype_0 = io_com_uops_2_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_lrs1_rtype_0 = io_com_uops_2_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_lrs2_rtype_0 = io_com_uops_2_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_com_uops_2_frs3_en_0 = io_com_uops_2_frs3_en; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fcn_dw_0 = io_com_uops_2_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_com_uops_2_fcn_op_0 = io_com_uops_2_fcn_op; // @[rename-stage.scala:414:7]
wire io_com_uops_2_fp_val_0 = io_com_uops_2_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_fp_rm_0 = io_com_uops_2_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_com_uops_2_fp_typ_0 = io_com_uops_2_fp_typ; // @[rename-stage.scala:414:7]
wire io_com_uops_2_xcpt_pf_if_0 = io_com_uops_2_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_com_uops_2_xcpt_ae_if_0 = io_com_uops_2_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_com_uops_2_xcpt_ma_if_0 = io_com_uops_2_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_com_uops_2_bp_debug_if_0 = io_com_uops_2_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_com_uops_2_bp_xcpt_if_0 = io_com_uops_2_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_debug_fsrc_0 = io_com_uops_2_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_com_uops_2_debug_tsrc_0 = io_com_uops_2_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_rollback_0 = io_rollback; // @[rename-stage.scala:414:7]
wire io_debug_rob_empty_0 = io_debug_rob_empty; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_issued = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_issued = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_issued = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:414:7]
wire io_dec_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_0_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_1_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_2_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_3_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_4_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_bypassable = 1'h0; // @[rename-stage.scala:414:7]
wire io_wakeups_5_bits_rebusy = 1'h0; // @[rename-stage.scala:414:7]
wire ren1_uops_0_iw_issued = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_prs1_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_prs2_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_prs3_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_ppred_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_0_xcpt_ma_if = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_issued = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_prs1_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_prs2_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_prs3_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_ppred_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_1_xcpt_ma_if = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_issued = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_issued_partial_agen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_issued_partial_dgen = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_p1_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_p2_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_iw_p3_bypass_hint = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_fp_ctrl_vec = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_prs1_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_prs2_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_prs3_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_ppred_busy = 1'h0; // @[rename-stage.scala:70:29]
wire ren1_uops_2_xcpt_ma_if = 1'h0; // @[rename-stage.scala:70:29]
wire ren2_br_tags_0_valid = 1'h0; // @[rename-stage.scala:80:29]
wire [2:0] io_dec_uops_0_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_dis_col_sel = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_0_debug_tsrc = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_dis_col_sel = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_1_debug_tsrc = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_dis_col_sel = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_dec_uops_2_debug_tsrc = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_0_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_1_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_2_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_3_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_4_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_wakeups_5_bits_speculative_mask = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] io_child_rebusys = 3'h0; // @[rename-stage.scala:414:7]
wire [2:0] ren1_uops_0_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_0_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_0_dis_col_sel = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_0_debug_tsrc = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_1_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_1_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_1_dis_col_sel = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_1_debug_tsrc = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_2_iw_p1_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_2_iw_p2_speculative_child = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_2_dis_col_sel = 3'h0; // @[rename-stage.scala:70:29]
wire [2:0] ren1_uops_2_debug_tsrc = 3'h0; // @[rename-stage.scala:70:29]
wire [6:0] io_dec_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_0_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_0_prs1 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_0_prs2 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_0_prs3 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_0_stale_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_prs1 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_prs2 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_prs3 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_1_stale_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_prs1 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_prs2 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_prs3 = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] io_dec_uops_2_stale_pdst = 7'h0; // @[rename-stage.scala:414:7]
wire [6:0] ren1_uops_0_rob_idx = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_0_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_0_prs1 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_0_prs2 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_0_prs3 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_0_stale_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_rob_idx = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_prs1 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_prs2 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_prs3 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_1_stale_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_rob_idx = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_prs1 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_prs2 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_prs3 = 7'h0; // @[rename-stage.scala:70:29]
wire [6:0] ren1_uops_2_stale_pdst = 7'h0; // @[rename-stage.scala:70:29]
wire [4:0] io_dec_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_0_ppred = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_1_ppred = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] io_dec_uops_2_ppred = 5'h0; // @[rename-stage.scala:414:7]
wire [4:0] ren1_uops_0_ldq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_0_stq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_0_ppred = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_1_ldq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_1_stq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_1_ppred = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_2_ldq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_2_stq_idx = 5'h0; // @[rename-stage.scala:70:29]
wire [4:0] ren1_uops_2_ppred = 5'h0; // @[rename-stage.scala:70:29]
wire [1:0] io_dec_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:414:7]
wire [1:0] io_dec_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:414:7]
wire [1:0] ren1_uops_0_rxq_idx = 2'h0; // @[rename-stage.scala:70:29]
wire [1:0] ren1_uops_1_rxq_idx = 2'h0; // @[rename-stage.scala:70:29]
wire [1:0] ren1_uops_2_rxq_idx = 2'h0; // @[rename-stage.scala:70:29]
wire [3:0] ren2_br_tags_0_bits = 4'h0; // @[rename-stage.scala:80:29]
wire [31:0] _freelist_io_initial_allocation_T = 32'hFFFFFFFF; // @[rename-stage.scala:446:37]
wire _io_ren_stalls_0_T_1; // @[rename-stage.scala:437:49]
wire _io_ren_stalls_1_T_1; // @[rename-stage.scala:437:49]
wire _io_ren_stalls_2_T_1; // @[rename-stage.scala:437:49]
wire ren1_fire_0 = io_dec_fire_0_0; // @[rename-stage.scala:69:29, :414:7]
wire ren1_fire_1 = io_dec_fire_1_0; // @[rename-stage.scala:69:29, :414:7]
wire ren1_fire_2 = io_dec_fire_2_0; // @[rename-stage.scala:69:29, :414:7]
wire [31:0] ren1_uops_0_inst = io_dec_uops_0_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [31:0] ren1_uops_0_debug_inst = io_dec_uops_0_debug_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_rvc = io_dec_uops_0_is_rvc_0; // @[rename-stage.scala:70:29, :414:7]
wire [39:0] ren1_uops_0_debug_pc = io_dec_uops_0_debug_pc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_iq_type_0 = io_dec_uops_0_iq_type_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_iq_type_1 = io_dec_uops_0_iq_type_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_iq_type_2 = io_dec_uops_0_iq_type_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_iq_type_3 = io_dec_uops_0_iq_type_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_0 = io_dec_uops_0_fu_code_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_1 = io_dec_uops_0_fu_code_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_2 = io_dec_uops_0_fu_code_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_3 = io_dec_uops_0_fu_code_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_4 = io_dec_uops_0_fu_code_4_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_5 = io_dec_uops_0_fu_code_5_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_6 = io_dec_uops_0_fu_code_6_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_7 = io_dec_uops_0_fu_code_7_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_8 = io_dec_uops_0_fu_code_8_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fu_code_9 = io_dec_uops_0_fu_code_9_0; // @[rename-stage.scala:70:29, :414:7]
wire [15:0] ren1_uops_0_br_mask = io_dec_uops_0_br_mask_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_0_br_tag = io_dec_uops_0_br_tag_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_0_br_type = io_dec_uops_0_br_type_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_sfb = io_dec_uops_0_is_sfb_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_fence = io_dec_uops_0_is_fence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_fencei = io_dec_uops_0_is_fencei_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_sfence = io_dec_uops_0_is_sfence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_amo = io_dec_uops_0_is_amo_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_eret = io_dec_uops_0_is_eret_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_sys_pc2epc = io_dec_uops_0_is_sys_pc2epc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_rocc = io_dec_uops_0_is_rocc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_mov = io_dec_uops_0_is_mov_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_0_ftq_idx = io_dec_uops_0_ftq_idx_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_edge_inst = io_dec_uops_0_edge_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_0_pc_lob = io_dec_uops_0_pc_lob_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_taken = io_dec_uops_0_taken_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_imm_rename = io_dec_uops_0_imm_rename_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_0_imm_sel = io_dec_uops_0_imm_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_0_pimm = io_dec_uops_0_pimm_0; // @[rename-stage.scala:70:29, :414:7]
wire [19:0] ren1_uops_0_imm_packed = io_dec_uops_0_imm_packed_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_op1_sel = io_dec_uops_0_op1_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_0_op2_sel = io_dec_uops_0_op2_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_ldst = io_dec_uops_0_fp_ctrl_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_wen = io_dec_uops_0_fp_ctrl_wen_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_ren1 = io_dec_uops_0_fp_ctrl_ren1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_ren2 = io_dec_uops_0_fp_ctrl_ren2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_ren3 = io_dec_uops_0_fp_ctrl_ren3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_swap12 = io_dec_uops_0_fp_ctrl_swap12_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_swap23 = io_dec_uops_0_fp_ctrl_swap23_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_fp_ctrl_typeTagIn = io_dec_uops_0_fp_ctrl_typeTagIn_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_fp_ctrl_typeTagOut = io_dec_uops_0_fp_ctrl_typeTagOut_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_fromint = io_dec_uops_0_fp_ctrl_fromint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_toint = io_dec_uops_0_fp_ctrl_toint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_fastpipe = io_dec_uops_0_fp_ctrl_fastpipe_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_fma = io_dec_uops_0_fp_ctrl_fma_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_div = io_dec_uops_0_fp_ctrl_div_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_sqrt = io_dec_uops_0_fp_ctrl_sqrt_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_ctrl_wflags = io_dec_uops_0_fp_ctrl_wflags_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_exception = io_dec_uops_0_exception_0; // @[rename-stage.scala:70:29, :414:7]
wire [63:0] ren1_uops_0_exc_cause = io_dec_uops_0_exc_cause_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_0_mem_cmd = io_dec_uops_0_mem_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_mem_size = io_dec_uops_0_mem_size_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_mem_signed = io_dec_uops_0_mem_signed_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_uses_ldq = io_dec_uops_0_uses_ldq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_uses_stq = io_dec_uops_0_uses_stq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_is_unique = io_dec_uops_0_is_unique_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_flush_on_commit = io_dec_uops_0_flush_on_commit_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_0_csr_cmd = io_dec_uops_0_csr_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_ldst_is_rs1 = io_dec_uops_0_ldst_is_rs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_0_ldst = io_dec_uops_0_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_0_lrs1 = io_dec_uops_0_lrs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_0_lrs2 = io_dec_uops_0_lrs2_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_0_lrs3 = io_dec_uops_0_lrs3_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_dst_rtype = io_dec_uops_0_dst_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_lrs1_rtype = io_dec_uops_0_lrs1_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_lrs2_rtype = io_dec_uops_0_lrs2_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_frs3_en = io_dec_uops_0_frs3_en_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fcn_dw = io_dec_uops_0_fcn_dw_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_0_fcn_op = io_dec_uops_0_fcn_op_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_fp_val = io_dec_uops_0_fp_val_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_0_fp_rm = io_dec_uops_0_fp_rm_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_0_fp_typ = io_dec_uops_0_fp_typ_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_xcpt_pf_if = io_dec_uops_0_xcpt_pf_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_xcpt_ae_if = io_dec_uops_0_xcpt_ae_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_bp_debug_if = io_dec_uops_0_bp_debug_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_0_bp_xcpt_if = io_dec_uops_0_bp_xcpt_if_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_0_debug_fsrc = io_dec_uops_0_debug_fsrc_0; // @[rename-stage.scala:70:29, :414:7]
wire [31:0] ren1_uops_1_inst = io_dec_uops_1_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [31:0] ren1_uops_1_debug_inst = io_dec_uops_1_debug_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_rvc = io_dec_uops_1_is_rvc_0; // @[rename-stage.scala:70:29, :414:7]
wire [39:0] ren1_uops_1_debug_pc = io_dec_uops_1_debug_pc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_iq_type_0 = io_dec_uops_1_iq_type_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_iq_type_1 = io_dec_uops_1_iq_type_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_iq_type_2 = io_dec_uops_1_iq_type_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_iq_type_3 = io_dec_uops_1_iq_type_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_0 = io_dec_uops_1_fu_code_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_1 = io_dec_uops_1_fu_code_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_2 = io_dec_uops_1_fu_code_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_3 = io_dec_uops_1_fu_code_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_4 = io_dec_uops_1_fu_code_4_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_5 = io_dec_uops_1_fu_code_5_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_6 = io_dec_uops_1_fu_code_6_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_7 = io_dec_uops_1_fu_code_7_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_8 = io_dec_uops_1_fu_code_8_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fu_code_9 = io_dec_uops_1_fu_code_9_0; // @[rename-stage.scala:70:29, :414:7]
wire [15:0] ren1_uops_1_br_mask = io_dec_uops_1_br_mask_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_1_br_tag = io_dec_uops_1_br_tag_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_1_br_type = io_dec_uops_1_br_type_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_sfb = io_dec_uops_1_is_sfb_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_fence = io_dec_uops_1_is_fence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_fencei = io_dec_uops_1_is_fencei_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_sfence = io_dec_uops_1_is_sfence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_amo = io_dec_uops_1_is_amo_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_eret = io_dec_uops_1_is_eret_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_sys_pc2epc = io_dec_uops_1_is_sys_pc2epc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_rocc = io_dec_uops_1_is_rocc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_mov = io_dec_uops_1_is_mov_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_1_ftq_idx = io_dec_uops_1_ftq_idx_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_edge_inst = io_dec_uops_1_edge_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_1_pc_lob = io_dec_uops_1_pc_lob_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_taken = io_dec_uops_1_taken_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_imm_rename = io_dec_uops_1_imm_rename_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_1_imm_sel = io_dec_uops_1_imm_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_1_pimm = io_dec_uops_1_pimm_0; // @[rename-stage.scala:70:29, :414:7]
wire [19:0] ren1_uops_1_imm_packed = io_dec_uops_1_imm_packed_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_op1_sel = io_dec_uops_1_op1_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_1_op2_sel = io_dec_uops_1_op2_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_ldst = io_dec_uops_1_fp_ctrl_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_wen = io_dec_uops_1_fp_ctrl_wen_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_ren1 = io_dec_uops_1_fp_ctrl_ren1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_ren2 = io_dec_uops_1_fp_ctrl_ren2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_ren3 = io_dec_uops_1_fp_ctrl_ren3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_swap12 = io_dec_uops_1_fp_ctrl_swap12_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_swap23 = io_dec_uops_1_fp_ctrl_swap23_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_fp_ctrl_typeTagIn = io_dec_uops_1_fp_ctrl_typeTagIn_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_fp_ctrl_typeTagOut = io_dec_uops_1_fp_ctrl_typeTagOut_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_fromint = io_dec_uops_1_fp_ctrl_fromint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_toint = io_dec_uops_1_fp_ctrl_toint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_fastpipe = io_dec_uops_1_fp_ctrl_fastpipe_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_fma = io_dec_uops_1_fp_ctrl_fma_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_div = io_dec_uops_1_fp_ctrl_div_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_sqrt = io_dec_uops_1_fp_ctrl_sqrt_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_ctrl_wflags = io_dec_uops_1_fp_ctrl_wflags_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_exception = io_dec_uops_1_exception_0; // @[rename-stage.scala:70:29, :414:7]
wire [63:0] ren1_uops_1_exc_cause = io_dec_uops_1_exc_cause_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_1_mem_cmd = io_dec_uops_1_mem_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_mem_size = io_dec_uops_1_mem_size_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_mem_signed = io_dec_uops_1_mem_signed_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_uses_ldq = io_dec_uops_1_uses_ldq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_uses_stq = io_dec_uops_1_uses_stq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_is_unique = io_dec_uops_1_is_unique_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_flush_on_commit = io_dec_uops_1_flush_on_commit_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_1_csr_cmd = io_dec_uops_1_csr_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_ldst_is_rs1 = io_dec_uops_1_ldst_is_rs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_1_ldst = io_dec_uops_1_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_1_lrs1 = io_dec_uops_1_lrs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_1_lrs2 = io_dec_uops_1_lrs2_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_1_lrs3 = io_dec_uops_1_lrs3_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_dst_rtype = io_dec_uops_1_dst_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_lrs1_rtype = io_dec_uops_1_lrs1_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_lrs2_rtype = io_dec_uops_1_lrs2_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_frs3_en = io_dec_uops_1_frs3_en_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fcn_dw = io_dec_uops_1_fcn_dw_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_1_fcn_op = io_dec_uops_1_fcn_op_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_fp_val = io_dec_uops_1_fp_val_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_1_fp_rm = io_dec_uops_1_fp_rm_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_1_fp_typ = io_dec_uops_1_fp_typ_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_xcpt_pf_if = io_dec_uops_1_xcpt_pf_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_xcpt_ae_if = io_dec_uops_1_xcpt_ae_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_bp_debug_if = io_dec_uops_1_bp_debug_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_1_bp_xcpt_if = io_dec_uops_1_bp_xcpt_if_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_1_debug_fsrc = io_dec_uops_1_debug_fsrc_0; // @[rename-stage.scala:70:29, :414:7]
wire [31:0] ren1_uops_2_inst = io_dec_uops_2_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [31:0] ren1_uops_2_debug_inst = io_dec_uops_2_debug_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_rvc = io_dec_uops_2_is_rvc_0; // @[rename-stage.scala:70:29, :414:7]
wire [39:0] ren1_uops_2_debug_pc = io_dec_uops_2_debug_pc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_iq_type_0 = io_dec_uops_2_iq_type_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_iq_type_1 = io_dec_uops_2_iq_type_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_iq_type_2 = io_dec_uops_2_iq_type_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_iq_type_3 = io_dec_uops_2_iq_type_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_0 = io_dec_uops_2_fu_code_0_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_1 = io_dec_uops_2_fu_code_1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_2 = io_dec_uops_2_fu_code_2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_3 = io_dec_uops_2_fu_code_3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_4 = io_dec_uops_2_fu_code_4_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_5 = io_dec_uops_2_fu_code_5_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_6 = io_dec_uops_2_fu_code_6_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_7 = io_dec_uops_2_fu_code_7_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_8 = io_dec_uops_2_fu_code_8_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fu_code_9 = io_dec_uops_2_fu_code_9_0; // @[rename-stage.scala:70:29, :414:7]
wire [15:0] ren1_uops_2_br_mask = io_dec_uops_2_br_mask_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_2_br_tag = io_dec_uops_2_br_tag_0; // @[rename-stage.scala:70:29, :414:7]
wire [3:0] ren1_uops_2_br_type = io_dec_uops_2_br_type_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_sfb = io_dec_uops_2_is_sfb_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_fence = io_dec_uops_2_is_fence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_fencei = io_dec_uops_2_is_fencei_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_sfence = io_dec_uops_2_is_sfence_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_amo = io_dec_uops_2_is_amo_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_eret = io_dec_uops_2_is_eret_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_sys_pc2epc = io_dec_uops_2_is_sys_pc2epc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_rocc = io_dec_uops_2_is_rocc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_mov = io_dec_uops_2_is_mov_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_2_ftq_idx = io_dec_uops_2_ftq_idx_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_edge_inst = io_dec_uops_2_edge_inst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_2_pc_lob = io_dec_uops_2_pc_lob_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_taken = io_dec_uops_2_taken_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_imm_rename = io_dec_uops_2_imm_rename_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_2_imm_sel = io_dec_uops_2_imm_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_2_pimm = io_dec_uops_2_pimm_0; // @[rename-stage.scala:70:29, :414:7]
wire [19:0] ren1_uops_2_imm_packed = io_dec_uops_2_imm_packed_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_op1_sel = io_dec_uops_2_op1_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_2_op2_sel = io_dec_uops_2_op2_sel_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_ldst = io_dec_uops_2_fp_ctrl_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_wen = io_dec_uops_2_fp_ctrl_wen_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_ren1 = io_dec_uops_2_fp_ctrl_ren1_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_ren2 = io_dec_uops_2_fp_ctrl_ren2_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_ren3 = io_dec_uops_2_fp_ctrl_ren3_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_swap12 = io_dec_uops_2_fp_ctrl_swap12_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_swap23 = io_dec_uops_2_fp_ctrl_swap23_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_fp_ctrl_typeTagIn = io_dec_uops_2_fp_ctrl_typeTagIn_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_fp_ctrl_typeTagOut = io_dec_uops_2_fp_ctrl_typeTagOut_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_fromint = io_dec_uops_2_fp_ctrl_fromint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_toint = io_dec_uops_2_fp_ctrl_toint_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_fastpipe = io_dec_uops_2_fp_ctrl_fastpipe_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_fma = io_dec_uops_2_fp_ctrl_fma_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_div = io_dec_uops_2_fp_ctrl_div_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_sqrt = io_dec_uops_2_fp_ctrl_sqrt_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_ctrl_wflags = io_dec_uops_2_fp_ctrl_wflags_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_exception = io_dec_uops_2_exception_0; // @[rename-stage.scala:70:29, :414:7]
wire [63:0] ren1_uops_2_exc_cause = io_dec_uops_2_exc_cause_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_2_mem_cmd = io_dec_uops_2_mem_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_mem_size = io_dec_uops_2_mem_size_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_mem_signed = io_dec_uops_2_mem_signed_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_uses_ldq = io_dec_uops_2_uses_ldq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_uses_stq = io_dec_uops_2_uses_stq_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_is_unique = io_dec_uops_2_is_unique_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_flush_on_commit = io_dec_uops_2_flush_on_commit_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_2_csr_cmd = io_dec_uops_2_csr_cmd_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_ldst_is_rs1 = io_dec_uops_2_ldst_is_rs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_2_ldst = io_dec_uops_2_ldst_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_2_lrs1 = io_dec_uops_2_lrs1_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_2_lrs2 = io_dec_uops_2_lrs2_0; // @[rename-stage.scala:70:29, :414:7]
wire [5:0] ren1_uops_2_lrs3 = io_dec_uops_2_lrs3_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_dst_rtype = io_dec_uops_2_dst_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_lrs1_rtype = io_dec_uops_2_lrs1_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_lrs2_rtype = io_dec_uops_2_lrs2_rtype_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_frs3_en = io_dec_uops_2_frs3_en_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fcn_dw = io_dec_uops_2_fcn_dw_0; // @[rename-stage.scala:70:29, :414:7]
wire [4:0] ren1_uops_2_fcn_op = io_dec_uops_2_fcn_op_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_fp_val = io_dec_uops_2_fp_val_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_2_fp_rm = io_dec_uops_2_fp_rm_0; // @[rename-stage.scala:70:29, :414:7]
wire [1:0] ren1_uops_2_fp_typ = io_dec_uops_2_fp_typ_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_xcpt_pf_if = io_dec_uops_2_xcpt_pf_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_xcpt_ae_if = io_dec_uops_2_xcpt_ae_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_bp_debug_if = io_dec_uops_2_bp_debug_if_0; // @[rename-stage.scala:70:29, :414:7]
wire ren1_uops_2_bp_xcpt_if = io_dec_uops_2_bp_xcpt_if_0; // @[rename-stage.scala:70:29, :414:7]
wire [2:0] ren1_uops_2_debug_fsrc = io_dec_uops_2_debug_fsrc_0; // @[rename-stage.scala:70:29, :414:7]
wire ren2_valids_0; // @[rename-stage.scala:76:29]
wire ren2_valids_1; // @[rename-stage.scala:76:29]
wire ren2_valids_2; // @[rename-stage.scala:76:29]
wire [31:0] io_ren2_uops_0_newuop_inst; // @[util.scala:81:26]
wire [31:0] io_ren2_uops_0_newuop_debug_inst; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_rvc; // @[util.scala:81:26]
wire [39:0] io_ren2_uops_0_newuop_debug_pc; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iq_type_0; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iq_type_1; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iq_type_2; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iq_type_3; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_0; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_1; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_2; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_3; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_4; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_5; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_6; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_7; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_8; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fu_code_9; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_issued; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] io_ren2_uops_0_newuop_br_mask; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_0_newuop_br_tag; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_0_newuop_br_type; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_sfb; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_fence; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_fencei; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_sfence; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_amo; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_eret; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_sys_pc2epc; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_rocc; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_mov; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_ftq_idx; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_edge_inst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_0_newuop_pc_lob; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_taken; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_imm_rename; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_imm_sel; // @[util.scala:81:26]
wire [19:0] io_ren2_uops_0_newuop_imm_packed; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_op1_sel; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_op2_sel; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_wen; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_toint; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_fma; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_div; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_rob_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_ldq_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_stq_idx; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_rxq_idx; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_pdst; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_prs1; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_prs2; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_prs3; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_ppred; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_prs1_busy; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_prs2_busy; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_prs3_busy; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_ppred_busy; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_0_newuop_stale_pdst; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_exception; // @[util.scala:81:26]
wire [63:0] io_ren2_uops_0_newuop_exc_cause; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_mem_cmd; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_mem_size; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_mem_signed; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_uses_ldq; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_uses_stq; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_is_unique; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_flush_on_commit; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_csr_cmd; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_0_newuop_ldst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_0_newuop_lrs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_0_newuop_lrs2; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_0_newuop_lrs3; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_dst_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_lrs2_rtype; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_frs3_en; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fcn_dw; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_fcn_op; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_fp_val; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_fp_rm; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_0_newuop_fp_typ; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_xcpt_pf_if; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_xcpt_ae_if; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_xcpt_ma_if; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_bp_debug_if; // @[util.scala:81:26]
wire io_ren2_uops_0_newuop_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_debug_fsrc; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_0_newuop_debug_tsrc; // @[util.scala:81:26]
wire [31:0] io_ren2_uops_1_newuop_inst; // @[util.scala:81:26]
wire [31:0] io_ren2_uops_1_newuop_debug_inst; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_rvc; // @[util.scala:81:26]
wire [39:0] io_ren2_uops_1_newuop_debug_pc; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iq_type_0; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iq_type_1; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iq_type_2; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iq_type_3; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_0; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_1; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_2; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_3; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_4; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_5; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_6; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_7; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_8; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fu_code_9; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_issued; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] io_ren2_uops_1_newuop_br_mask; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_1_newuop_br_tag; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_1_newuop_br_type; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_sfb; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_fence; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_fencei; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_sfence; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_amo; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_eret; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_sys_pc2epc; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_rocc; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_mov; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_ftq_idx; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_edge_inst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_1_newuop_pc_lob; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_taken; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_imm_rename; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_imm_sel; // @[util.scala:81:26]
wire [19:0] io_ren2_uops_1_newuop_imm_packed; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_op1_sel; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_op2_sel; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_wen; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_toint; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_fma; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_div; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_rob_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_ldq_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_stq_idx; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_rxq_idx; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_pdst; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_prs1; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_prs2; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_prs3; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_ppred; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_prs1_busy; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_prs2_busy; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_prs3_busy; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_ppred_busy; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_1_newuop_stale_pdst; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_exception; // @[util.scala:81:26]
wire [63:0] io_ren2_uops_1_newuop_exc_cause; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_mem_cmd; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_mem_size; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_mem_signed; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_uses_ldq; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_uses_stq; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_is_unique; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_flush_on_commit; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_csr_cmd; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_1_newuop_ldst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_1_newuop_lrs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_1_newuop_lrs2; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_1_newuop_lrs3; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_dst_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_lrs2_rtype; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_frs3_en; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fcn_dw; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_fcn_op; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_fp_val; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_fp_rm; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_1_newuop_fp_typ; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_xcpt_pf_if; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_xcpt_ae_if; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_xcpt_ma_if; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_bp_debug_if; // @[util.scala:81:26]
wire io_ren2_uops_1_newuop_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_debug_fsrc; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_1_newuop_debug_tsrc; // @[util.scala:81:26]
wire [31:0] io_ren2_uops_2_newuop_inst; // @[util.scala:81:26]
wire [31:0] io_ren2_uops_2_newuop_debug_inst; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_rvc; // @[util.scala:81:26]
wire [39:0] io_ren2_uops_2_newuop_debug_pc; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iq_type_0; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iq_type_1; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iq_type_2; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iq_type_3; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_0; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_1; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_2; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_3; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_4; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_5; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_6; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_7; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_8; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fu_code_9; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_issued; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] io_ren2_uops_2_newuop_br_mask; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_2_newuop_br_tag; // @[util.scala:81:26]
wire [3:0] io_ren2_uops_2_newuop_br_type; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_sfb; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_fence; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_fencei; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_sfence; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_amo; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_eret; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_sys_pc2epc; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_rocc; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_mov; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_ftq_idx; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_edge_inst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_2_newuop_pc_lob; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_taken; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_imm_rename; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_imm_sel; // @[util.scala:81:26]
wire [19:0] io_ren2_uops_2_newuop_imm_packed; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_op1_sel; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_op2_sel; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_wen; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_toint; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_fma; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_div; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_rob_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_ldq_idx; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_stq_idx; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_rxq_idx; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_pdst; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_prs1; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_prs2; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_prs3; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_ppred; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_prs1_busy; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_prs2_busy; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_prs3_busy; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_ppred_busy; // @[util.scala:81:26]
wire [6:0] io_ren2_uops_2_newuop_stale_pdst; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_exception; // @[util.scala:81:26]
wire [63:0] io_ren2_uops_2_newuop_exc_cause; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_mem_cmd; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_mem_size; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_mem_signed; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_uses_ldq; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_uses_stq; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_is_unique; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_flush_on_commit; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_csr_cmd; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_2_newuop_ldst; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_2_newuop_lrs1; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_2_newuop_lrs2; // @[util.scala:81:26]
wire [5:0] io_ren2_uops_2_newuop_lrs3; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_dst_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_lrs2_rtype; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_frs3_en; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fcn_dw; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_fcn_op; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_fp_val; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_fp_rm; // @[util.scala:81:26]
wire [1:0] io_ren2_uops_2_newuop_fp_typ; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_xcpt_pf_if; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_xcpt_ae_if; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_xcpt_ma_if; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_bp_debug_if; // @[util.scala:81:26]
wire io_ren2_uops_2_newuop_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_debug_fsrc; // @[util.scala:81:26]
wire [2:0] io_ren2_uops_2_newuop_debug_tsrc; // @[util.scala:81:26]
wire io_ren_stalls_0_0; // @[rename-stage.scala:414:7]
wire io_ren_stalls_1_0; // @[rename-stage.scala:414:7]
wire io_ren_stalls_2_0; // @[rename-stage.scala:414:7]
wire io_ren2_mask_0; // @[rename-stage.scala:414:7]
wire io_ren2_mask_1; // @[rename-stage.scala:414:7]
wire io_ren2_mask_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iq_type_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iq_type_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iq_type_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iq_type_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_4; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_5; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_6; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_7; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_8; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fu_code_9; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_0_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_0_debug_inst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_ren2_uops_0_debug_pc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_issued; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_ren2_uops_0_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_0_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_0_br_type; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_sfb; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_fence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_fencei; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_sfence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_amo; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_eret; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_rocc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_ftq_idx; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_0_pc_lob; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_taken; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_imm_sel_0; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_pimm_0; // @[rename-stage.scala:414:7]
wire [19:0] io_ren2_uops_0_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_op2_sel; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_ppred; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_prs1_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_prs2_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_prs3_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_0_stale_pdst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_ren2_uops_0_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_mem_size; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_mem_signed; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_uses_ldq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_uses_stq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_is_unique; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_csr_cmd; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_0_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_0_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_0_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_0_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_frs3_en; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_0_fcn_op; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_0_fp_typ; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_0_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_0_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iq_type_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iq_type_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iq_type_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iq_type_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_4; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_5; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_6; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_7; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_8; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fu_code_9; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_1_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_1_debug_inst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_ren2_uops_1_debug_pc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_issued; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_ren2_uops_1_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_1_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_1_br_type; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_sfb; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_fence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_fencei; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_sfence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_amo; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_eret; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_rocc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_ftq_idx; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_1_pc_lob; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_taken; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_imm_sel_0; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_pimm_0; // @[rename-stage.scala:414:7]
wire [19:0] io_ren2_uops_1_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_op2_sel; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_ppred; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_prs1_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_prs2_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_prs3_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_1_stale_pdst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_ren2_uops_1_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_mem_size; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_mem_signed; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_uses_ldq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_uses_stq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_is_unique; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_csr_cmd; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_1_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_1_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_1_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_1_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_frs3_en; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_1_fcn_op; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_1_fp_typ; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_1_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_1_debug_tsrc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iq_type_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iq_type_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iq_type_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iq_type_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_0; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_4; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_5; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_6; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_7; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_8; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fu_code_9; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_ldst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_wen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_ren1; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_ren2; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_ren3; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_swap12; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_swap23; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_fromint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_toint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_fastpipe; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_fma; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_div; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_sqrt; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_wflags; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_ctrl_vec; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_2_inst; // @[rename-stage.scala:414:7]
wire [31:0] io_ren2_uops_2_debug_inst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_rvc; // @[rename-stage.scala:414:7]
wire [39:0] io_ren2_uops_2_debug_pc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_issued; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_issued_partial_agen; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_issued_partial_dgen; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_iw_p1_speculative_child; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_iw_p2_speculative_child; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_p1_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_p2_bypass_hint; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_iw_p3_bypass_hint; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_dis_col_sel; // @[rename-stage.scala:414:7]
wire [15:0] io_ren2_uops_2_br_mask; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_2_br_tag; // @[rename-stage.scala:414:7]
wire [3:0] io_ren2_uops_2_br_type; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_sfb; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_fence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_fencei; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_sfence; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_amo; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_eret; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_sys_pc2epc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_rocc; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_mov; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_ftq_idx; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_edge_inst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_2_pc_lob; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_taken; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_imm_rename; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_imm_sel_0; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_pimm_0; // @[rename-stage.scala:414:7]
wire [19:0] io_ren2_uops_2_imm_packed; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_op1_sel; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_op2_sel; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_rob_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_ldq_idx; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_stq_idx; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_rxq_idx; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_pdst; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_prs1; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_prs2; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_prs3; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_ppred; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_prs1_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_prs2_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_prs3_busy; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_ppred_busy; // @[rename-stage.scala:414:7]
wire [6:0] io_ren2_uops_2_stale_pdst; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_exception; // @[rename-stage.scala:414:7]
wire [63:0] io_ren2_uops_2_exc_cause; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_mem_cmd; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_mem_size; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_mem_signed; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_uses_ldq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_uses_stq; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_is_unique; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_flush_on_commit; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_csr_cmd; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_ldst_is_rs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_2_ldst; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_2_lrs1; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_2_lrs2; // @[rename-stage.scala:414:7]
wire [5:0] io_ren2_uops_2_lrs3; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_dst_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_lrs1_rtype; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_lrs2_rtype; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_frs3_en; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fcn_dw; // @[rename-stage.scala:414:7]
wire [4:0] io_ren2_uops_2_fcn_op; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_fp_val; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_fp_rm; // @[rename-stage.scala:414:7]
wire [1:0] io_ren2_uops_2_fp_typ; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_xcpt_pf_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_xcpt_ae_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_xcpt_ma_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_bp_debug_if; // @[rename-stage.scala:414:7]
wire io_ren2_uops_2_bp_xcpt_if; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_debug_fsrc; // @[rename-stage.scala:414:7]
wire [2:0] io_ren2_uops_2_debug_tsrc; // @[rename-stage.scala:414:7]
assign io_ren2_mask_0 = ren2_valids_0; // @[rename-stage.scala:76:29, :414:7]
assign io_ren2_mask_1 = ren2_valids_1; // @[rename-stage.scala:76:29, :414:7]
assign io_ren2_mask_2 = ren2_valids_2; // @[rename-stage.scala:76:29, :414:7]
assign io_ren2_uops_0_newuop_inst = ren2_uops_0_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_debug_inst = ren2_uops_0_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_rvc = ren2_uops_0_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_debug_pc = ren2_uops_0_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iq_type_0 = ren2_uops_0_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iq_type_1 = ren2_uops_0_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iq_type_2 = ren2_uops_0_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iq_type_3 = ren2_uops_0_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_0 = ren2_uops_0_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_1 = ren2_uops_0_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_2 = ren2_uops_0_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_3 = ren2_uops_0_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_4 = ren2_uops_0_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_5 = ren2_uops_0_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_6 = ren2_uops_0_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_7 = ren2_uops_0_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_8 = ren2_uops_0_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fu_code_9 = ren2_uops_0_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_issued = ren2_uops_0_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_issued_partial_agen = ren2_uops_0_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_issued_partial_dgen = ren2_uops_0_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_p1_speculative_child = ren2_uops_0_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_p2_speculative_child = ren2_uops_0_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_p1_bypass_hint = ren2_uops_0_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_p2_bypass_hint = ren2_uops_0_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_iw_p3_bypass_hint = ren2_uops_0_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_dis_col_sel = ren2_uops_0_dis_col_sel; // @[util.scala:81:26]
wire [3:0] ren2_br_tags_1_bits = ren2_uops_0_br_tag; // @[rename-stage.scala:77:29, :80:29]
assign io_ren2_uops_0_newuop_br_tag = ren2_uops_0_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_br_type = ren2_uops_0_br_type; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_sfb = ren2_uops_0_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_fence = ren2_uops_0_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_fencei = ren2_uops_0_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_sfence = ren2_uops_0_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_amo = ren2_uops_0_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_eret = ren2_uops_0_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_sys_pc2epc = ren2_uops_0_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_rocc = ren2_uops_0_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_mov = ren2_uops_0_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ftq_idx = ren2_uops_0_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_edge_inst = ren2_uops_0_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_pc_lob = ren2_uops_0_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_taken = ren2_uops_0_taken; // @[util.scala:81:26]
wire ren2_alloc_reqs_0 = ren2_uops_0_imm_rename; // @[rename-stage.scala:77:29, :78:29]
assign io_ren2_uops_0_newuop_imm_rename = ren2_uops_0_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_imm_sel = ren2_uops_0_imm_sel; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_0_newuop_pimm = ren2_uops_0_pimm; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_imm_packed = ren2_uops_0_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_op1_sel = ren2_uops_0_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_op2_sel = ren2_uops_0_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_ldst = ren2_uops_0_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_wen = ren2_uops_0_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_ren1 = ren2_uops_0_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_ren2 = ren2_uops_0_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_ren3 = ren2_uops_0_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_swap12 = ren2_uops_0_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_swap23 = ren2_uops_0_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_typeTagIn = ren2_uops_0_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_typeTagOut = ren2_uops_0_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_fromint = ren2_uops_0_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_toint = ren2_uops_0_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_fastpipe = ren2_uops_0_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_fma = ren2_uops_0_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_div = ren2_uops_0_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_sqrt = ren2_uops_0_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_wflags = ren2_uops_0_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_ctrl_vec = ren2_uops_0_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_rob_idx = ren2_uops_0_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ldq_idx = ren2_uops_0_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_stq_idx = ren2_uops_0_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_rxq_idx = ren2_uops_0_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_pdst = ren2_uops_0_pdst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs1 = ren2_uops_0_prs1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs2 = ren2_uops_0_prs2; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs3 = ren2_uops_0_prs3; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ppred = ren2_uops_0_ppred; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs1_busy = ren2_uops_0_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs2_busy = ren2_uops_0_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_prs3_busy = ren2_uops_0_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ppred_busy = ren2_uops_0_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_stale_pdst = ren2_uops_0_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_exception = ren2_uops_0_exception; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_exc_cause = ren2_uops_0_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_mem_cmd = ren2_uops_0_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_mem_size = ren2_uops_0_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_mem_signed = ren2_uops_0_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_uses_ldq = ren2_uops_0_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_uses_stq = ren2_uops_0_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_is_unique = ren2_uops_0_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_flush_on_commit = ren2_uops_0_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_csr_cmd = ren2_uops_0_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ldst_is_rs1 = ren2_uops_0_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_ldst = ren2_uops_0_ldst; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_lrs1 = ren2_uops_0_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_lrs2 = ren2_uops_0_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_lrs3 = ren2_uops_0_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_dst_rtype = ren2_uops_0_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_lrs1_rtype = ren2_uops_0_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_lrs2_rtype = ren2_uops_0_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_frs3_en = ren2_uops_0_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fcn_dw = ren2_uops_0_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fcn_op = ren2_uops_0_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_val = ren2_uops_0_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_rm = ren2_uops_0_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_fp_typ = ren2_uops_0_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_xcpt_pf_if = ren2_uops_0_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_xcpt_ae_if = ren2_uops_0_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_xcpt_ma_if = ren2_uops_0_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_bp_debug_if = ren2_uops_0_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_bp_xcpt_if = ren2_uops_0_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_debug_fsrc = ren2_uops_0_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_0_newuop_debug_tsrc = ren2_uops_0_debug_tsrc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_inst = ren2_uops_1_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_debug_inst = ren2_uops_1_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_rvc = ren2_uops_1_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_debug_pc = ren2_uops_1_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iq_type_0 = ren2_uops_1_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iq_type_1 = ren2_uops_1_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iq_type_2 = ren2_uops_1_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iq_type_3 = ren2_uops_1_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_0 = ren2_uops_1_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_1 = ren2_uops_1_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_2 = ren2_uops_1_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_3 = ren2_uops_1_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_4 = ren2_uops_1_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_5 = ren2_uops_1_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_6 = ren2_uops_1_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_7 = ren2_uops_1_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_8 = ren2_uops_1_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fu_code_9 = ren2_uops_1_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_issued = ren2_uops_1_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_issued_partial_agen = ren2_uops_1_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_issued_partial_dgen = ren2_uops_1_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_p1_speculative_child = ren2_uops_1_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_p2_speculative_child = ren2_uops_1_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_p1_bypass_hint = ren2_uops_1_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_p2_bypass_hint = ren2_uops_1_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_iw_p3_bypass_hint = ren2_uops_1_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_dis_col_sel = ren2_uops_1_dis_col_sel; // @[util.scala:81:26]
wire [3:0] ren2_br_tags_2_bits = ren2_uops_1_br_tag; // @[rename-stage.scala:77:29, :80:29]
assign io_ren2_uops_1_newuop_br_tag = ren2_uops_1_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_br_type = ren2_uops_1_br_type; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_sfb = ren2_uops_1_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_fence = ren2_uops_1_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_fencei = ren2_uops_1_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_sfence = ren2_uops_1_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_amo = ren2_uops_1_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_eret = ren2_uops_1_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_sys_pc2epc = ren2_uops_1_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_rocc = ren2_uops_1_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_mov = ren2_uops_1_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ftq_idx = ren2_uops_1_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_edge_inst = ren2_uops_1_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_pc_lob = ren2_uops_1_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_taken = ren2_uops_1_taken; // @[util.scala:81:26]
wire ren2_alloc_reqs_1 = ren2_uops_1_imm_rename; // @[rename-stage.scala:77:29, :78:29]
assign io_ren2_uops_1_newuop_imm_rename = ren2_uops_1_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_imm_sel = ren2_uops_1_imm_sel; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_1_newuop_pimm = ren2_uops_1_pimm; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_imm_packed = ren2_uops_1_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_op1_sel = ren2_uops_1_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_op2_sel = ren2_uops_1_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_ldst = ren2_uops_1_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_wen = ren2_uops_1_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_ren1 = ren2_uops_1_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_ren2 = ren2_uops_1_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_ren3 = ren2_uops_1_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_swap12 = ren2_uops_1_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_swap23 = ren2_uops_1_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_typeTagIn = ren2_uops_1_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_typeTagOut = ren2_uops_1_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_fromint = ren2_uops_1_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_toint = ren2_uops_1_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_fastpipe = ren2_uops_1_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_fma = ren2_uops_1_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_div = ren2_uops_1_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_sqrt = ren2_uops_1_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_wflags = ren2_uops_1_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_ctrl_vec = ren2_uops_1_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_rob_idx = ren2_uops_1_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ldq_idx = ren2_uops_1_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_stq_idx = ren2_uops_1_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_rxq_idx = ren2_uops_1_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_pdst = ren2_uops_1_pdst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs1 = ren2_uops_1_prs1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs2 = ren2_uops_1_prs2; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs3 = ren2_uops_1_prs3; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ppred = ren2_uops_1_ppred; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs1_busy = ren2_uops_1_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs2_busy = ren2_uops_1_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_prs3_busy = ren2_uops_1_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ppred_busy = ren2_uops_1_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_stale_pdst = ren2_uops_1_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_exception = ren2_uops_1_exception; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_exc_cause = ren2_uops_1_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_mem_cmd = ren2_uops_1_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_mem_size = ren2_uops_1_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_mem_signed = ren2_uops_1_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_uses_ldq = ren2_uops_1_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_uses_stq = ren2_uops_1_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_is_unique = ren2_uops_1_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_flush_on_commit = ren2_uops_1_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_csr_cmd = ren2_uops_1_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ldst_is_rs1 = ren2_uops_1_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_ldst = ren2_uops_1_ldst; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_lrs1 = ren2_uops_1_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_lrs2 = ren2_uops_1_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_lrs3 = ren2_uops_1_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_dst_rtype = ren2_uops_1_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_lrs1_rtype = ren2_uops_1_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_lrs2_rtype = ren2_uops_1_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_frs3_en = ren2_uops_1_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fcn_dw = ren2_uops_1_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fcn_op = ren2_uops_1_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_val = ren2_uops_1_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_rm = ren2_uops_1_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_fp_typ = ren2_uops_1_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_xcpt_pf_if = ren2_uops_1_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_xcpt_ae_if = ren2_uops_1_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_xcpt_ma_if = ren2_uops_1_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_bp_debug_if = ren2_uops_1_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_bp_xcpt_if = ren2_uops_1_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_debug_fsrc = ren2_uops_1_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_1_newuop_debug_tsrc = ren2_uops_1_debug_tsrc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_inst = ren2_uops_2_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_debug_inst = ren2_uops_2_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_rvc = ren2_uops_2_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_debug_pc = ren2_uops_2_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iq_type_0 = ren2_uops_2_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iq_type_1 = ren2_uops_2_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iq_type_2 = ren2_uops_2_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iq_type_3 = ren2_uops_2_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_0 = ren2_uops_2_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_1 = ren2_uops_2_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_2 = ren2_uops_2_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_3 = ren2_uops_2_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_4 = ren2_uops_2_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_5 = ren2_uops_2_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_6 = ren2_uops_2_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_7 = ren2_uops_2_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_8 = ren2_uops_2_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fu_code_9 = ren2_uops_2_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_issued = ren2_uops_2_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_issued_partial_agen = ren2_uops_2_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_issued_partial_dgen = ren2_uops_2_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_p1_speculative_child = ren2_uops_2_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_p2_speculative_child = ren2_uops_2_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_p1_bypass_hint = ren2_uops_2_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_p2_bypass_hint = ren2_uops_2_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_iw_p3_bypass_hint = ren2_uops_2_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_dis_col_sel = ren2_uops_2_dis_col_sel; // @[util.scala:81:26]
wire [3:0] ren2_br_tags_3_bits = ren2_uops_2_br_tag; // @[rename-stage.scala:77:29, :80:29]
assign io_ren2_uops_2_newuop_br_tag = ren2_uops_2_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_br_type = ren2_uops_2_br_type; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_sfb = ren2_uops_2_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_fence = ren2_uops_2_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_fencei = ren2_uops_2_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_sfence = ren2_uops_2_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_amo = ren2_uops_2_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_eret = ren2_uops_2_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_sys_pc2epc = ren2_uops_2_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_rocc = ren2_uops_2_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_mov = ren2_uops_2_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ftq_idx = ren2_uops_2_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_edge_inst = ren2_uops_2_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_pc_lob = ren2_uops_2_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_taken = ren2_uops_2_taken; // @[util.scala:81:26]
wire ren2_alloc_reqs_2 = ren2_uops_2_imm_rename; // @[rename-stage.scala:77:29, :78:29]
assign io_ren2_uops_2_newuop_imm_rename = ren2_uops_2_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_imm_sel = ren2_uops_2_imm_sel; // @[util.scala:81:26]
wire [4:0] io_ren2_uops_2_newuop_pimm = ren2_uops_2_pimm; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_imm_packed = ren2_uops_2_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_op1_sel = ren2_uops_2_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_op2_sel = ren2_uops_2_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_ldst = ren2_uops_2_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_wen = ren2_uops_2_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_ren1 = ren2_uops_2_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_ren2 = ren2_uops_2_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_ren3 = ren2_uops_2_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_swap12 = ren2_uops_2_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_swap23 = ren2_uops_2_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_typeTagIn = ren2_uops_2_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_typeTagOut = ren2_uops_2_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_fromint = ren2_uops_2_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_toint = ren2_uops_2_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_fastpipe = ren2_uops_2_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_fma = ren2_uops_2_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_div = ren2_uops_2_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_sqrt = ren2_uops_2_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_wflags = ren2_uops_2_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_ctrl_vec = ren2_uops_2_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_rob_idx = ren2_uops_2_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ldq_idx = ren2_uops_2_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_stq_idx = ren2_uops_2_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_rxq_idx = ren2_uops_2_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_pdst = ren2_uops_2_pdst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs1 = ren2_uops_2_prs1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs2 = ren2_uops_2_prs2; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs3 = ren2_uops_2_prs3; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ppred = ren2_uops_2_ppred; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs1_busy = ren2_uops_2_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs2_busy = ren2_uops_2_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_prs3_busy = ren2_uops_2_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ppred_busy = ren2_uops_2_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_stale_pdst = ren2_uops_2_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_exception = ren2_uops_2_exception; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_exc_cause = ren2_uops_2_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_mem_cmd = ren2_uops_2_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_mem_size = ren2_uops_2_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_mem_signed = ren2_uops_2_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_uses_ldq = ren2_uops_2_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_uses_stq = ren2_uops_2_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_is_unique = ren2_uops_2_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_flush_on_commit = ren2_uops_2_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_csr_cmd = ren2_uops_2_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ldst_is_rs1 = ren2_uops_2_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_ldst = ren2_uops_2_ldst; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_lrs1 = ren2_uops_2_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_lrs2 = ren2_uops_2_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_lrs3 = ren2_uops_2_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_dst_rtype = ren2_uops_2_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_lrs1_rtype = ren2_uops_2_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_lrs2_rtype = ren2_uops_2_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_frs3_en = ren2_uops_2_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fcn_dw = ren2_uops_2_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fcn_op = ren2_uops_2_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_val = ren2_uops_2_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_rm = ren2_uops_2_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_fp_typ = ren2_uops_2_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_xcpt_pf_if = ren2_uops_2_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_xcpt_ae_if = ren2_uops_2_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_xcpt_ma_if = ren2_uops_2_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_bp_debug_if = ren2_uops_2_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_bp_xcpt_if = ren2_uops_2_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_debug_fsrc = ren2_uops_2_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_2_newuop_debug_tsrc = ren2_uops_2_debug_tsrc; // @[util.scala:81:26]
wire [15:0] ren2_uops_0_br_mask; // @[rename-stage.scala:77:29]
wire [15:0] ren2_uops_1_br_mask; // @[rename-stage.scala:77:29]
wire [15:0] ren2_uops_2_br_mask; // @[rename-stage.scala:77:29]
wire ren2_alloc_fire_0 = io_dis_fire_0_0 & ren2_alloc_reqs_0; // @[rename-stage.scala:78:29, :79:79, :414:7]
wire ren2_alloc_fire_1 = io_dis_fire_1_0 & ren2_alloc_reqs_1; // @[rename-stage.scala:78:29, :79:79, :414:7]
wire ren2_alloc_fire_2 = io_dis_fire_2_0 & ren2_alloc_reqs_2; // @[rename-stage.scala:78:29, :79:79, :414:7]
wire _ren2_br_tags_1_valid_T_15; // @[rename-stage.scala:117:45]
wire _ren2_br_tags_2_valid_T_15; // @[rename-stage.scala:117:45]
wire _ren2_br_tags_3_valid_T_15; // @[rename-stage.scala:117:45]
wire ren2_br_tags_1_valid; // @[rename-stage.scala:80:29]
wire ren2_br_tags_2_valid; // @[rename-stage.scala:80:29]
wire ren2_br_tags_3_valid; // @[rename-stage.scala:80:29]
reg r_valid; // @[rename-stage.scala:93:27]
assign ren2_valids_0 = r_valid; // @[rename-stage.scala:76:29, :93:27]
reg [31:0] r_uop_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_inst = r_uop_inst; // @[rename-stage.scala:77:29, :94:23]
reg [31:0] r_uop_debug_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_debug_inst = r_uop_debug_inst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_rvc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_rvc = r_uop_is_rvc; // @[rename-stage.scala:77:29, :94:23]
reg [39:0] r_uop_debug_pc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_debug_pc = r_uop_debug_pc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iq_type_0; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iq_type_0 = r_uop_iq_type_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iq_type_1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iq_type_1 = r_uop_iq_type_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iq_type_2; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iq_type_2 = r_uop_iq_type_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iq_type_3; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iq_type_3 = r_uop_iq_type_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_0; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_0 = r_uop_fu_code_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_1 = r_uop_fu_code_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_2; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_2 = r_uop_fu_code_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_3; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_3 = r_uop_fu_code_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_4; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_4 = r_uop_fu_code_4; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_5; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_5 = r_uop_fu_code_5; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_6; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_6 = r_uop_fu_code_6; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_7; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_7 = r_uop_fu_code_7; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_8; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_8 = r_uop_fu_code_8; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fu_code_9; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fu_code_9 = r_uop_fu_code_9; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_issued; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_issued = r_uop_iw_issued; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_issued_partial_agen; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_issued_partial_agen = r_uop_iw_issued_partial_agen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_issued_partial_dgen; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_issued_partial_dgen = r_uop_iw_issued_partial_dgen; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_iw_p1_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_p1_speculative_child = r_uop_iw_p1_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_iw_p2_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_p2_speculative_child = r_uop_iw_p2_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_p1_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_p1_bypass_hint = r_uop_iw_p1_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_p2_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_p2_bypass_hint = r_uop_iw_p2_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_iw_p3_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_0_iw_p3_bypass_hint = r_uop_iw_p3_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_dis_col_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_0_dis_col_sel = r_uop_dis_col_sel; // @[rename-stage.scala:77:29, :94:23]
reg [15:0] r_uop_br_mask; // @[rename-stage.scala:94:23]
assign ren2_uops_0_br_mask = r_uop_br_mask; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_br_tag; // @[rename-stage.scala:94:23]
assign ren2_uops_0_br_tag = r_uop_br_tag; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_br_type; // @[rename-stage.scala:94:23]
assign ren2_uops_0_br_type = r_uop_br_type; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_sfb; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_sfb = r_uop_is_sfb; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_fence; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_fence = r_uop_is_fence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_fencei; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_fencei = r_uop_is_fencei; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_sfence; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_sfence = r_uop_is_sfence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_amo; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_amo = r_uop_is_amo; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_eret; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_eret = r_uop_is_eret; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_sys_pc2epc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_rocc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_rocc = r_uop_is_rocc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_mov; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_mov = r_uop_is_mov; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_ftq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ftq_idx = r_uop_ftq_idx; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_edge_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_edge_inst = r_uop_edge_inst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_pc_lob; // @[rename-stage.scala:94:23]
assign ren2_uops_0_pc_lob = r_uop_pc_lob; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_taken; // @[rename-stage.scala:94:23]
assign ren2_uops_0_taken = r_uop_taken; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_imm_rename; // @[rename-stage.scala:94:23]
assign ren2_uops_0_imm_rename = r_uop_imm_rename; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_imm_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_0_imm_sel = r_uop_imm_sel; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_pimm; // @[rename-stage.scala:94:23]
assign ren2_uops_0_pimm = r_uop_pimm; // @[rename-stage.scala:77:29, :94:23]
reg [19:0] r_uop_imm_packed; // @[rename-stage.scala:94:23]
assign ren2_uops_0_imm_packed = r_uop_imm_packed; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_op1_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_0_op1_sel = r_uop_op1_sel; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_op2_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_0_op2_sel = r_uop_op2_sel; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_ldst = r_uop_fp_ctrl_ldst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_wen; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_wen = r_uop_fp_ctrl_wen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_ren1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_ren1 = r_uop_fp_ctrl_ren1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_ren2; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_ren2 = r_uop_fp_ctrl_ren2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_ren3; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_ren3 = r_uop_fp_ctrl_ren3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_swap12; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_swap12 = r_uop_fp_ctrl_swap12; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_swap23; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_swap23 = r_uop_fp_ctrl_swap23; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_typeTagIn = r_uop_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_typeTagOut = r_uop_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_fromint; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_fromint = r_uop_fp_ctrl_fromint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_toint; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_toint = r_uop_fp_ctrl_toint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_fastpipe = r_uop_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_fma; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_fma = r_uop_fp_ctrl_fma; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_div; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_div = r_uop_fp_ctrl_div; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_sqrt; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_sqrt = r_uop_fp_ctrl_sqrt; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_wflags; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_wflags = r_uop_fp_ctrl_wflags; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_ctrl_vec; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_ctrl_vec = r_uop_fp_ctrl_vec; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_rob_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_0_rob_idx = r_uop_rob_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_ldq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ldq_idx = r_uop_ldq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_stq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_0_stq_idx = r_uop_stq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_rxq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_0_rxq_idx = r_uop_rxq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_pdst = r_uop_pdst; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_prs1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs1 = r_uop_prs1; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_prs2; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs2 = r_uop_prs2; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_prs3; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs3 = r_uop_prs3; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_ppred; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ppred = r_uop_ppred; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_prs1_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs1_busy = r_uop_prs1_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_prs2_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs2_busy = r_uop_prs2_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_prs3_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_0_prs3_busy = r_uop_prs3_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_ppred_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ppred_busy = r_uop_ppred_busy; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_stale_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_stale_pdst = r_uop_stale_pdst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_exception; // @[rename-stage.scala:94:23]
assign ren2_uops_0_exception = r_uop_exception; // @[rename-stage.scala:77:29, :94:23]
reg [63:0] r_uop_exc_cause; // @[rename-stage.scala:94:23]
assign ren2_uops_0_exc_cause = r_uop_exc_cause; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_mem_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_0_mem_cmd = r_uop_mem_cmd; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_mem_size; // @[rename-stage.scala:94:23]
assign ren2_uops_0_mem_size = r_uop_mem_size; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_mem_signed; // @[rename-stage.scala:94:23]
assign ren2_uops_0_mem_signed = r_uop_mem_signed; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_uses_ldq; // @[rename-stage.scala:94:23]
assign ren2_uops_0_uses_ldq = r_uop_uses_ldq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_uses_stq; // @[rename-stage.scala:94:23]
assign ren2_uops_0_uses_stq = r_uop_uses_stq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_is_unique; // @[rename-stage.scala:94:23]
assign ren2_uops_0_is_unique = r_uop_is_unique; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_flush_on_commit; // @[rename-stage.scala:94:23]
assign ren2_uops_0_flush_on_commit = r_uop_flush_on_commit; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_csr_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_0_csr_cmd = r_uop_csr_cmd; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_ldst_is_rs1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_0_ldst = r_uop_ldst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_lrs1; // @[rename-stage.scala:94:23]
assign ren2_uops_0_lrs1 = r_uop_lrs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_lrs2; // @[rename-stage.scala:94:23]
assign ren2_uops_0_lrs2 = r_uop_lrs2; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_lrs3; // @[rename-stage.scala:94:23]
assign ren2_uops_0_lrs3 = r_uop_lrs3; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_dst_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_0_dst_rtype = r_uop_dst_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_lrs1_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_lrs2_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_frs3_en; // @[rename-stage.scala:94:23]
assign ren2_uops_0_frs3_en = r_uop_frs3_en; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fcn_dw; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fcn_dw = r_uop_fcn_dw; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_fcn_op; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fcn_op = r_uop_fcn_op; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_fp_val; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_val = r_uop_fp_val; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_fp_rm; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_rm = r_uop_fp_rm; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_fp_typ; // @[rename-stage.scala:94:23]
assign ren2_uops_0_fp_typ = r_uop_fp_typ; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_xcpt_pf_if; // @[rename-stage.scala:94:23]
assign ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_xcpt_ae_if; // @[rename-stage.scala:94:23]
assign ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_xcpt_ma_if; // @[rename-stage.scala:94:23]
assign ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_bp_debug_if; // @[rename-stage.scala:94:23]
assign ren2_uops_0_bp_debug_if = r_uop_bp_debug_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_bp_xcpt_if; // @[rename-stage.scala:94:23]
assign ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_debug_fsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_debug_fsrc = r_uop_debug_fsrc; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_debug_tsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_0_debug_tsrc = r_uop_debug_tsrc; // @[rename-stage.scala:77:29, :94:23]
wire [31:0] r_uop_newuop_inst = next_uop_inst; // @[util.scala:81:26]
wire [31:0] r_uop_newuop_debug_inst = next_uop_debug_inst; // @[util.scala:81:26]
wire r_uop_newuop_is_rvc = next_uop_is_rvc; // @[util.scala:81:26]
wire [39:0] r_uop_newuop_debug_pc = next_uop_debug_pc; // @[util.scala:81:26]
wire r_uop_newuop_iq_type_0 = next_uop_iq_type_0; // @[util.scala:81:26]
wire r_uop_newuop_iq_type_1 = next_uop_iq_type_1; // @[util.scala:81:26]
wire r_uop_newuop_iq_type_2 = next_uop_iq_type_2; // @[util.scala:81:26]
wire r_uop_newuop_iq_type_3 = next_uop_iq_type_3; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_0 = next_uop_fu_code_0; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_1 = next_uop_fu_code_1; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_2 = next_uop_fu_code_2; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_3 = next_uop_fu_code_3; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_4 = next_uop_fu_code_4; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_5 = next_uop_fu_code_5; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_6 = next_uop_fu_code_6; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_7 = next_uop_fu_code_7; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_8 = next_uop_fu_code_8; // @[util.scala:81:26]
wire r_uop_newuop_fu_code_9 = next_uop_fu_code_9; // @[util.scala:81:26]
wire r_uop_newuop_iw_issued = next_uop_iw_issued; // @[util.scala:81:26]
wire r_uop_newuop_iw_issued_partial_agen = next_uop_iw_issued_partial_agen; // @[util.scala:81:26]
wire r_uop_newuop_iw_issued_partial_dgen = next_uop_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_iw_p1_speculative_child = next_uop_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_iw_p2_speculative_child = next_uop_iw_p2_speculative_child; // @[util.scala:81:26]
wire r_uop_newuop_iw_p1_bypass_hint = next_uop_iw_p1_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_iw_p2_bypass_hint = next_uop_iw_p2_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_iw_p3_bypass_hint = next_uop_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_dis_col_sel = next_uop_dis_col_sel; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_br_tag = next_uop_br_tag; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_br_type = next_uop_br_type; // @[util.scala:81:26]
wire r_uop_newuop_is_sfb = next_uop_is_sfb; // @[util.scala:81:26]
wire r_uop_newuop_is_fence = next_uop_is_fence; // @[util.scala:81:26]
wire r_uop_newuop_is_fencei = next_uop_is_fencei; // @[util.scala:81:26]
wire r_uop_newuop_is_sfence = next_uop_is_sfence; // @[util.scala:81:26]
wire r_uop_newuop_is_amo = next_uop_is_amo; // @[util.scala:81:26]
wire r_uop_newuop_is_eret = next_uop_is_eret; // @[util.scala:81:26]
wire r_uop_newuop_is_sys_pc2epc = next_uop_is_sys_pc2epc; // @[util.scala:81:26]
wire r_uop_newuop_is_rocc = next_uop_is_rocc; // @[util.scala:81:26]
wire r_uop_newuop_is_mov = next_uop_is_mov; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_ftq_idx = next_uop_ftq_idx; // @[util.scala:81:26]
wire r_uop_newuop_edge_inst = next_uop_edge_inst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_pc_lob = next_uop_pc_lob; // @[util.scala:81:26]
wire r_uop_newuop_taken = next_uop_taken; // @[util.scala:81:26]
wire r_uop_newuop_imm_rename = next_uop_imm_rename; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_imm_sel = next_uop_imm_sel; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_pimm = next_uop_pimm; // @[util.scala:81:26]
wire [19:0] r_uop_newuop_imm_packed = next_uop_imm_packed; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_op1_sel = next_uop_op1_sel; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_op2_sel = next_uop_op2_sel; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_ldst = next_uop_fp_ctrl_ldst; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_wen = next_uop_fp_ctrl_wen; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_ren1 = next_uop_fp_ctrl_ren1; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_ren2 = next_uop_fp_ctrl_ren2; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_ren3 = next_uop_fp_ctrl_ren3; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_swap12 = next_uop_fp_ctrl_swap12; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_swap23 = next_uop_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_fp_ctrl_typeTagIn = next_uop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_fp_ctrl_typeTagOut = next_uop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_fromint = next_uop_fp_ctrl_fromint; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_toint = next_uop_fp_ctrl_toint; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_fastpipe = next_uop_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_fma = next_uop_fp_ctrl_fma; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_div = next_uop_fp_ctrl_div; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_sqrt = next_uop_fp_ctrl_sqrt; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_wflags = next_uop_fp_ctrl_wflags; // @[util.scala:81:26]
wire r_uop_newuop_fp_ctrl_vec = next_uop_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_rob_idx = next_uop_rob_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_ldq_idx = next_uop_ldq_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_stq_idx = next_uop_stq_idx; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_rxq_idx = next_uop_rxq_idx; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_pdst = next_uop_pdst; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_prs1 = next_uop_prs1; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_prs2 = next_uop_prs2; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_prs3 = next_uop_prs3; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_ppred = next_uop_ppred; // @[util.scala:81:26]
wire r_uop_newuop_prs1_busy = next_uop_prs1_busy; // @[util.scala:81:26]
wire r_uop_newuop_prs2_busy = next_uop_prs2_busy; // @[util.scala:81:26]
wire r_uop_newuop_prs3_busy = next_uop_prs3_busy; // @[util.scala:81:26]
wire r_uop_newuop_ppred_busy = next_uop_ppred_busy; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_stale_pdst = next_uop_stale_pdst; // @[util.scala:81:26]
wire r_uop_newuop_exception = next_uop_exception; // @[util.scala:81:26]
wire [63:0] r_uop_newuop_exc_cause = next_uop_exc_cause; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_mem_cmd = next_uop_mem_cmd; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_mem_size = next_uop_mem_size; // @[util.scala:81:26]
wire r_uop_newuop_mem_signed = next_uop_mem_signed; // @[util.scala:81:26]
wire r_uop_newuop_uses_ldq = next_uop_uses_ldq; // @[util.scala:81:26]
wire r_uop_newuop_uses_stq = next_uop_uses_stq; // @[util.scala:81:26]
wire r_uop_newuop_is_unique = next_uop_is_unique; // @[util.scala:81:26]
wire r_uop_newuop_flush_on_commit = next_uop_flush_on_commit; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_csr_cmd = next_uop_csr_cmd; // @[util.scala:81:26]
wire r_uop_newuop_ldst_is_rs1 = next_uop_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_ldst = next_uop_ldst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_lrs1 = next_uop_lrs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_lrs2 = next_uop_lrs2; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_lrs3 = next_uop_lrs3; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_dst_rtype = next_uop_dst_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_lrs1_rtype = next_uop_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_lrs2_rtype = next_uop_lrs2_rtype; // @[util.scala:81:26]
wire r_uop_newuop_frs3_en = next_uop_frs3_en; // @[util.scala:81:26]
wire r_uop_newuop_fcn_dw = next_uop_fcn_dw; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_fcn_op = next_uop_fcn_op; // @[util.scala:81:26]
wire r_uop_newuop_fp_val = next_uop_fp_val; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_fp_rm = next_uop_fp_rm; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_fp_typ = next_uop_fp_typ; // @[util.scala:81:26]
wire r_uop_newuop_xcpt_pf_if = next_uop_xcpt_pf_if; // @[util.scala:81:26]
wire r_uop_newuop_xcpt_ae_if = next_uop_xcpt_ae_if; // @[util.scala:81:26]
wire r_uop_newuop_xcpt_ma_if = next_uop_xcpt_ma_if; // @[util.scala:81:26]
wire r_uop_newuop_bp_debug_if = next_uop_bp_debug_if; // @[util.scala:81:26]
wire r_uop_newuop_bp_xcpt_if = next_uop_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_debug_fsrc = next_uop_debug_fsrc; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_debug_tsrc = next_uop_debug_tsrc; // @[util.scala:81:26]
wire [15:0] next_uop_br_mask; // @[rename-stage.scala:95:24]
wire _r_valid_T = ~io_dis_fire_0_0; // @[rename-stage.scala:105:29, :414:7]
wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-stage.scala:93:27, :105:{26,29}]
wire _GEN = io_kill_0 | ~io_dis_ready_0; // @[rename-stage.scala:97:14, :99:20, :101:30, :414:7]
assign next_uop_inst = _GEN ? r_uop_inst : ren1_uops_0_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_debug_inst = _GEN ? r_uop_debug_inst : ren1_uops_0_debug_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_rvc = _GEN ? r_uop_is_rvc : ren1_uops_0_is_rvc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_debug_pc = _GEN ? r_uop_debug_pc : ren1_uops_0_debug_pc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iq_type_0 = _GEN ? r_uop_iq_type_0 : ren1_uops_0_iq_type_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iq_type_1 = _GEN ? r_uop_iq_type_1 : ren1_uops_0_iq_type_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iq_type_2 = _GEN ? r_uop_iq_type_2 : ren1_uops_0_iq_type_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iq_type_3 = _GEN ? r_uop_iq_type_3 : ren1_uops_0_iq_type_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_0 = _GEN ? r_uop_fu_code_0 : ren1_uops_0_fu_code_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_1 = _GEN ? r_uop_fu_code_1 : ren1_uops_0_fu_code_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_2 = _GEN ? r_uop_fu_code_2 : ren1_uops_0_fu_code_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_3 = _GEN ? r_uop_fu_code_3 : ren1_uops_0_fu_code_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_4 = _GEN ? r_uop_fu_code_4 : ren1_uops_0_fu_code_4; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_5 = _GEN ? r_uop_fu_code_5 : ren1_uops_0_fu_code_5; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_6 = _GEN ? r_uop_fu_code_6 : ren1_uops_0_fu_code_6; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_7 = _GEN ? r_uop_fu_code_7 : ren1_uops_0_fu_code_7; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_8 = _GEN ? r_uop_fu_code_8 : ren1_uops_0_fu_code_8; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fu_code_9 = _GEN ? r_uop_fu_code_9 : ren1_uops_0_fu_code_9; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_issued = _GEN & r_uop_iw_issued; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_issued_partial_agen = _GEN & r_uop_iw_issued_partial_agen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_issued_partial_dgen = _GEN & r_uop_iw_issued_partial_dgen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_p1_speculative_child = _GEN ? r_uop_iw_p1_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_p2_speculative_child = _GEN ? r_uop_iw_p2_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_p1_bypass_hint = _GEN & r_uop_iw_p1_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_p2_bypass_hint = _GEN & r_uop_iw_p2_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_iw_p3_bypass_hint = _GEN & r_uop_iw_p3_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_dis_col_sel = _GEN ? r_uop_dis_col_sel : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_br_mask = _GEN ? r_uop_br_mask : ren1_uops_0_br_mask; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_br_tag = _GEN ? r_uop_br_tag : ren1_uops_0_br_tag; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_br_type = _GEN ? r_uop_br_type : ren1_uops_0_br_type; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_sfb = _GEN ? r_uop_is_sfb : ren1_uops_0_is_sfb; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_fence = _GEN ? r_uop_is_fence : ren1_uops_0_is_fence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_fencei = _GEN ? r_uop_is_fencei : ren1_uops_0_is_fencei; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_sfence = _GEN ? r_uop_is_sfence : ren1_uops_0_is_sfence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_amo = _GEN ? r_uop_is_amo : ren1_uops_0_is_amo; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_eret = _GEN ? r_uop_is_eret : ren1_uops_0_is_eret; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_sys_pc2epc = _GEN ? r_uop_is_sys_pc2epc : ren1_uops_0_is_sys_pc2epc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_rocc = _GEN ? r_uop_is_rocc : ren1_uops_0_is_rocc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_mov = _GEN ? r_uop_is_mov : ren1_uops_0_is_mov; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ftq_idx = _GEN ? r_uop_ftq_idx : ren1_uops_0_ftq_idx; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_edge_inst = _GEN ? r_uop_edge_inst : ren1_uops_0_edge_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_pc_lob = _GEN ? r_uop_pc_lob : ren1_uops_0_pc_lob; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_taken = _GEN ? r_uop_taken : ren1_uops_0_taken; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_imm_rename = _GEN ? r_uop_imm_rename : ren1_uops_0_imm_rename; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_imm_sel = _GEN ? r_uop_imm_sel : ren1_uops_0_imm_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_pimm = _GEN ? r_uop_pimm : ren1_uops_0_pimm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_imm_packed = _GEN ? r_uop_imm_packed : ren1_uops_0_imm_packed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_op1_sel = _GEN ? r_uop_op1_sel : ren1_uops_0_op1_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_op2_sel = _GEN ? r_uop_op2_sel : ren1_uops_0_op2_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_ldst = _GEN ? r_uop_fp_ctrl_ldst : ren1_uops_0_fp_ctrl_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_wen = _GEN ? r_uop_fp_ctrl_wen : ren1_uops_0_fp_ctrl_wen; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_ren1 = _GEN ? r_uop_fp_ctrl_ren1 : ren1_uops_0_fp_ctrl_ren1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_ren2 = _GEN ? r_uop_fp_ctrl_ren2 : ren1_uops_0_fp_ctrl_ren2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_ren3 = _GEN ? r_uop_fp_ctrl_ren3 : ren1_uops_0_fp_ctrl_ren3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_swap12 = _GEN ? r_uop_fp_ctrl_swap12 : ren1_uops_0_fp_ctrl_swap12; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_swap23 = _GEN ? r_uop_fp_ctrl_swap23 : ren1_uops_0_fp_ctrl_swap23; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_typeTagIn = _GEN ? r_uop_fp_ctrl_typeTagIn : ren1_uops_0_fp_ctrl_typeTagIn; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_typeTagOut = _GEN ? r_uop_fp_ctrl_typeTagOut : ren1_uops_0_fp_ctrl_typeTagOut; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_fromint = _GEN ? r_uop_fp_ctrl_fromint : ren1_uops_0_fp_ctrl_fromint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_toint = _GEN ? r_uop_fp_ctrl_toint : ren1_uops_0_fp_ctrl_toint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_fastpipe = _GEN ? r_uop_fp_ctrl_fastpipe : ren1_uops_0_fp_ctrl_fastpipe; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_fma = _GEN ? r_uop_fp_ctrl_fma : ren1_uops_0_fp_ctrl_fma; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_div = _GEN ? r_uop_fp_ctrl_div : ren1_uops_0_fp_ctrl_div; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_sqrt = _GEN ? r_uop_fp_ctrl_sqrt : ren1_uops_0_fp_ctrl_sqrt; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_wflags = _GEN ? r_uop_fp_ctrl_wflags : ren1_uops_0_fp_ctrl_wflags; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_ctrl_vec = _GEN & r_uop_fp_ctrl_vec; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_rob_idx = _GEN ? r_uop_rob_idx : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ldq_idx = _GEN ? r_uop_ldq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_stq_idx = _GEN ? r_uop_stq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_rxq_idx = _GEN ? r_uop_rxq_idx : 2'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_pdst = _GEN ? r_uop_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs1 = _GEN ? r_uop_prs1 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs2 = _GEN ? r_uop_prs2 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs3 = _GEN ? r_uop_prs3 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ppred = _GEN ? r_uop_ppred : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs1_busy = _GEN & r_uop_prs1_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs2_busy = _GEN & r_uop_prs2_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_prs3_busy = _GEN & r_uop_prs3_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ppred_busy = _GEN & r_uop_ppred_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_stale_pdst = _GEN ? r_uop_stale_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_exception = _GEN ? r_uop_exception : ren1_uops_0_exception; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_exc_cause = _GEN ? r_uop_exc_cause : ren1_uops_0_exc_cause; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_mem_cmd = _GEN ? r_uop_mem_cmd : ren1_uops_0_mem_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_mem_size = _GEN ? r_uop_mem_size : ren1_uops_0_mem_size; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_mem_signed = _GEN ? r_uop_mem_signed : ren1_uops_0_mem_signed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_uses_ldq = _GEN ? r_uop_uses_ldq : ren1_uops_0_uses_ldq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_uses_stq = _GEN ? r_uop_uses_stq : ren1_uops_0_uses_stq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_is_unique = _GEN ? r_uop_is_unique : ren1_uops_0_is_unique; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_flush_on_commit = _GEN ? r_uop_flush_on_commit : ren1_uops_0_flush_on_commit; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_csr_cmd = _GEN ? r_uop_csr_cmd : ren1_uops_0_csr_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ldst_is_rs1 = _GEN ? r_uop_ldst_is_rs1 : ren1_uops_0_ldst_is_rs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_ldst = _GEN ? r_uop_ldst : ren1_uops_0_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_lrs1 = _GEN ? r_uop_lrs1 : ren1_uops_0_lrs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_lrs2 = _GEN ? r_uop_lrs2 : ren1_uops_0_lrs2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_lrs3 = _GEN ? r_uop_lrs3 : ren1_uops_0_lrs3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_dst_rtype = _GEN ? r_uop_dst_rtype : ren1_uops_0_dst_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_lrs1_rtype = _GEN ? r_uop_lrs1_rtype : ren1_uops_0_lrs1_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_lrs2_rtype = _GEN ? r_uop_lrs2_rtype : ren1_uops_0_lrs2_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_frs3_en = _GEN ? r_uop_frs3_en : ren1_uops_0_frs3_en; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fcn_dw = _GEN ? r_uop_fcn_dw : ren1_uops_0_fcn_dw; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fcn_op = _GEN ? r_uop_fcn_op : ren1_uops_0_fcn_op; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_val = _GEN ? r_uop_fp_val : ren1_uops_0_fp_val; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_rm = _GEN ? r_uop_fp_rm : ren1_uops_0_fp_rm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_fp_typ = _GEN ? r_uop_fp_typ : ren1_uops_0_fp_typ; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_xcpt_pf_if = _GEN ? r_uop_xcpt_pf_if : ren1_uops_0_xcpt_pf_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_xcpt_ae_if = _GEN ? r_uop_xcpt_ae_if : ren1_uops_0_xcpt_ae_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_xcpt_ma_if = _GEN & r_uop_xcpt_ma_if; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_bp_debug_if = _GEN ? r_uop_bp_debug_if : ren1_uops_0_bp_debug_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_bp_xcpt_if = _GEN ? r_uop_bp_xcpt_if : ren1_uops_0_bp_xcpt_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_debug_fsrc = _GEN ? r_uop_debug_fsrc : ren1_uops_0_debug_fsrc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_debug_tsrc = _GEN ? r_uop_debug_tsrc : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
wire [15:0] _r_uop_newuop_br_mask_T_1; // @[util.scala:82:35]
wire [15:0] r_uop_newuop_br_mask; // @[util.scala:81:26]
wire [15:0] _r_uop_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _r_uop_newuop_br_mask_T_1 = next_uop_br_mask & _r_uop_newuop_br_mask_T; // @[util.scala:82:{35,37}]
assign r_uop_newuop_br_mask = _r_uop_newuop_br_mask_T_1; // @[util.scala:81:26, :82:35]
wire _ren2_br_tags_1_valid_T = ren2_uops_0_br_type == 4'h1; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_1 = ren2_uops_0_br_type == 4'h2; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_2 = ren2_uops_0_br_type == 4'h3; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_3 = ren2_uops_0_br_type == 4'h4; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_4 = ren2_uops_0_br_type == 4'h5; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_5 = ren2_uops_0_br_type == 4'h6; // @[package.scala:16:47]
wire _ren2_br_tags_1_valid_T_6 = _ren2_br_tags_1_valid_T | _ren2_br_tags_1_valid_T_1; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_1_valid_T_7 = _ren2_br_tags_1_valid_T_6 | _ren2_br_tags_1_valid_T_2; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_1_valid_T_8 = _ren2_br_tags_1_valid_T_7 | _ren2_br_tags_1_valid_T_3; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_1_valid_T_9 = _ren2_br_tags_1_valid_T_8 | _ren2_br_tags_1_valid_T_4; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_1_valid_T_10 = _ren2_br_tags_1_valid_T_9 | _ren2_br_tags_1_valid_T_5; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_1_valid_T_11 = ~ren2_uops_0_is_sfb; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_1_valid_T_12 = _ren2_br_tags_1_valid_T_10 & _ren2_br_tags_1_valid_T_11; // @[package.scala:81:59]
wire _ren2_br_tags_1_valid_T_13 = ren2_uops_0_br_type == 4'h8; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_1_valid_T_14 = _ren2_br_tags_1_valid_T_12 | _ren2_br_tags_1_valid_T_13; // @[micro-op.scala:119:34, :160:{33,45}]
assign _ren2_br_tags_1_valid_T_15 = io_dis_fire_0_0 & _ren2_br_tags_1_valid_T_14; // @[rename-stage.scala:117:45, :414:7]
assign ren2_br_tags_1_valid = _ren2_br_tags_1_valid_T_15; // @[rename-stage.scala:80:29, :117:45]
reg r_valid_1; // @[rename-stage.scala:93:27]
assign ren2_valids_1 = r_valid_1; // @[rename-stage.scala:76:29, :93:27]
reg [31:0] r_uop_1_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_inst = r_uop_1_inst; // @[rename-stage.scala:77:29, :94:23]
reg [31:0] r_uop_1_debug_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_debug_inst = r_uop_1_debug_inst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_rvc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_rvc = r_uop_1_is_rvc; // @[rename-stage.scala:77:29, :94:23]
reg [39:0] r_uop_1_debug_pc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_debug_pc = r_uop_1_debug_pc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iq_type_0; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iq_type_0 = r_uop_1_iq_type_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iq_type_1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iq_type_1 = r_uop_1_iq_type_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iq_type_2; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iq_type_2 = r_uop_1_iq_type_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iq_type_3; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iq_type_3 = r_uop_1_iq_type_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_0; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_0 = r_uop_1_fu_code_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_1 = r_uop_1_fu_code_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_2; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_2 = r_uop_1_fu_code_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_3; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_3 = r_uop_1_fu_code_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_4; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_4 = r_uop_1_fu_code_4; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_5; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_5 = r_uop_1_fu_code_5; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_6; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_6 = r_uop_1_fu_code_6; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_7; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_7 = r_uop_1_fu_code_7; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_8; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_8 = r_uop_1_fu_code_8; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fu_code_9; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fu_code_9 = r_uop_1_fu_code_9; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_issued; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_issued = r_uop_1_iw_issued; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_issued_partial_agen; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_issued_partial_agen = r_uop_1_iw_issued_partial_agen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_issued_partial_dgen; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_issued_partial_dgen = r_uop_1_iw_issued_partial_dgen; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_iw_p1_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_p1_speculative_child = r_uop_1_iw_p1_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_iw_p2_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_p2_speculative_child = r_uop_1_iw_p2_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_p1_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_p1_bypass_hint = r_uop_1_iw_p1_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_p2_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_p2_bypass_hint = r_uop_1_iw_p2_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_iw_p3_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_1_iw_p3_bypass_hint = r_uop_1_iw_p3_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_dis_col_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_1_dis_col_sel = r_uop_1_dis_col_sel; // @[rename-stage.scala:77:29, :94:23]
reg [15:0] r_uop_1_br_mask; // @[rename-stage.scala:94:23]
assign ren2_uops_1_br_mask = r_uop_1_br_mask; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_1_br_tag; // @[rename-stage.scala:94:23]
assign ren2_uops_1_br_tag = r_uop_1_br_tag; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_1_br_type; // @[rename-stage.scala:94:23]
assign ren2_uops_1_br_type = r_uop_1_br_type; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_sfb; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_sfb = r_uop_1_is_sfb; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_fence; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_fence = r_uop_1_is_fence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_fencei; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_fencei = r_uop_1_is_fencei; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_sfence; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_sfence = r_uop_1_is_sfence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_amo; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_amo = r_uop_1_is_amo; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_eret; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_eret = r_uop_1_is_eret; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_sys_pc2epc = r_uop_1_is_sys_pc2epc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_rocc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_rocc = r_uop_1_is_rocc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_mov; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_mov = r_uop_1_is_mov; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_ftq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ftq_idx = r_uop_1_ftq_idx; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_edge_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_edge_inst = r_uop_1_edge_inst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_1_pc_lob; // @[rename-stage.scala:94:23]
assign ren2_uops_1_pc_lob = r_uop_1_pc_lob; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_taken; // @[rename-stage.scala:94:23]
assign ren2_uops_1_taken = r_uop_1_taken; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_imm_rename; // @[rename-stage.scala:94:23]
assign ren2_uops_1_imm_rename = r_uop_1_imm_rename; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_imm_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_1_imm_sel = r_uop_1_imm_sel; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_pimm; // @[rename-stage.scala:94:23]
assign ren2_uops_1_pimm = r_uop_1_pimm; // @[rename-stage.scala:77:29, :94:23]
reg [19:0] r_uop_1_imm_packed; // @[rename-stage.scala:94:23]
assign ren2_uops_1_imm_packed = r_uop_1_imm_packed; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_op1_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_1_op1_sel = r_uop_1_op1_sel; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_op2_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_1_op2_sel = r_uop_1_op2_sel; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_ldst = r_uop_1_fp_ctrl_ldst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_wen; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_wen = r_uop_1_fp_ctrl_wen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_ren1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_ren1 = r_uop_1_fp_ctrl_ren1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_ren2; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_ren2 = r_uop_1_fp_ctrl_ren2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_ren3; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_ren3 = r_uop_1_fp_ctrl_ren3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_swap12; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_swap12 = r_uop_1_fp_ctrl_swap12; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_swap23; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_swap23 = r_uop_1_fp_ctrl_swap23; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_typeTagIn = r_uop_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_typeTagOut = r_uop_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_fromint; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_fromint = r_uop_1_fp_ctrl_fromint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_toint; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_toint = r_uop_1_fp_ctrl_toint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_fastpipe; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_fastpipe = r_uop_1_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_fma; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_fma = r_uop_1_fp_ctrl_fma; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_div; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_div = r_uop_1_fp_ctrl_div; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_sqrt; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_sqrt = r_uop_1_fp_ctrl_sqrt; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_wflags; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_wflags = r_uop_1_fp_ctrl_wflags; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_ctrl_vec; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_ctrl_vec = r_uop_1_fp_ctrl_vec; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_rob_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_1_rob_idx = r_uop_1_rob_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_ldq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ldq_idx = r_uop_1_ldq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_stq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_1_stq_idx = r_uop_1_stq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_rxq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_1_rxq_idx = r_uop_1_rxq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_pdst = r_uop_1_pdst; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_prs1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs1 = r_uop_1_prs1; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_prs2; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs2 = r_uop_1_prs2; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_prs3; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs3 = r_uop_1_prs3; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_ppred; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ppred = r_uop_1_ppred; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_prs1_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs1_busy = r_uop_1_prs1_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_prs2_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs2_busy = r_uop_1_prs2_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_prs3_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_1_prs3_busy = r_uop_1_prs3_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_ppred_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ppred_busy = r_uop_1_ppred_busy; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_1_stale_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_stale_pdst = r_uop_1_stale_pdst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_exception; // @[rename-stage.scala:94:23]
assign ren2_uops_1_exception = r_uop_1_exception; // @[rename-stage.scala:77:29, :94:23]
reg [63:0] r_uop_1_exc_cause; // @[rename-stage.scala:94:23]
assign ren2_uops_1_exc_cause = r_uop_1_exc_cause; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_mem_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_1_mem_cmd = r_uop_1_mem_cmd; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_mem_size; // @[rename-stage.scala:94:23]
assign ren2_uops_1_mem_size = r_uop_1_mem_size; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_mem_signed; // @[rename-stage.scala:94:23]
assign ren2_uops_1_mem_signed = r_uop_1_mem_signed; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_uses_ldq; // @[rename-stage.scala:94:23]
assign ren2_uops_1_uses_ldq = r_uop_1_uses_ldq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_uses_stq; // @[rename-stage.scala:94:23]
assign ren2_uops_1_uses_stq = r_uop_1_uses_stq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_is_unique; // @[rename-stage.scala:94:23]
assign ren2_uops_1_is_unique = r_uop_1_is_unique; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_flush_on_commit; // @[rename-stage.scala:94:23]
assign ren2_uops_1_flush_on_commit = r_uop_1_flush_on_commit; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_csr_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_1_csr_cmd = r_uop_1_csr_cmd; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_ldst_is_rs1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ldst_is_rs1 = r_uop_1_ldst_is_rs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_1_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_1_ldst = r_uop_1_ldst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_1_lrs1; // @[rename-stage.scala:94:23]
assign ren2_uops_1_lrs1 = r_uop_1_lrs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_1_lrs2; // @[rename-stage.scala:94:23]
assign ren2_uops_1_lrs2 = r_uop_1_lrs2; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_1_lrs3; // @[rename-stage.scala:94:23]
assign ren2_uops_1_lrs3 = r_uop_1_lrs3; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_dst_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_1_dst_rtype = r_uop_1_dst_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_lrs1_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_1_lrs1_rtype = r_uop_1_lrs1_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_lrs2_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_1_lrs2_rtype = r_uop_1_lrs2_rtype; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_frs3_en; // @[rename-stage.scala:94:23]
assign ren2_uops_1_frs3_en = r_uop_1_frs3_en; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fcn_dw; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fcn_dw = r_uop_1_fcn_dw; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_1_fcn_op; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fcn_op = r_uop_1_fcn_op; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_fp_val; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_val = r_uop_1_fp_val; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_fp_rm; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_rm = r_uop_1_fp_rm; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_1_fp_typ; // @[rename-stage.scala:94:23]
assign ren2_uops_1_fp_typ = r_uop_1_fp_typ; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_xcpt_pf_if; // @[rename-stage.scala:94:23]
assign ren2_uops_1_xcpt_pf_if = r_uop_1_xcpt_pf_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_xcpt_ae_if; // @[rename-stage.scala:94:23]
assign ren2_uops_1_xcpt_ae_if = r_uop_1_xcpt_ae_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_xcpt_ma_if; // @[rename-stage.scala:94:23]
assign ren2_uops_1_xcpt_ma_if = r_uop_1_xcpt_ma_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_bp_debug_if; // @[rename-stage.scala:94:23]
assign ren2_uops_1_bp_debug_if = r_uop_1_bp_debug_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_1_bp_xcpt_if; // @[rename-stage.scala:94:23]
assign ren2_uops_1_bp_xcpt_if = r_uop_1_bp_xcpt_if; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_debug_fsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_debug_fsrc = r_uop_1_debug_fsrc; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_1_debug_tsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_1_debug_tsrc = r_uop_1_debug_tsrc; // @[rename-stage.scala:77:29, :94:23]
wire [31:0] r_uop_newuop_1_inst = next_uop_1_inst; // @[util.scala:81:26]
wire [31:0] r_uop_newuop_1_debug_inst = next_uop_1_debug_inst; // @[util.scala:81:26]
wire r_uop_newuop_1_is_rvc = next_uop_1_is_rvc; // @[util.scala:81:26]
wire [39:0] r_uop_newuop_1_debug_pc = next_uop_1_debug_pc; // @[util.scala:81:26]
wire r_uop_newuop_1_iq_type_0 = next_uop_1_iq_type_0; // @[util.scala:81:26]
wire r_uop_newuop_1_iq_type_1 = next_uop_1_iq_type_1; // @[util.scala:81:26]
wire r_uop_newuop_1_iq_type_2 = next_uop_1_iq_type_2; // @[util.scala:81:26]
wire r_uop_newuop_1_iq_type_3 = next_uop_1_iq_type_3; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_0 = next_uop_1_fu_code_0; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_1 = next_uop_1_fu_code_1; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_2 = next_uop_1_fu_code_2; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_3 = next_uop_1_fu_code_3; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_4 = next_uop_1_fu_code_4; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_5 = next_uop_1_fu_code_5; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_6 = next_uop_1_fu_code_6; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_7 = next_uop_1_fu_code_7; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_8 = next_uop_1_fu_code_8; // @[util.scala:81:26]
wire r_uop_newuop_1_fu_code_9 = next_uop_1_fu_code_9; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_issued = next_uop_1_iw_issued; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_issued_partial_agen = next_uop_1_iw_issued_partial_agen; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_issued_partial_dgen = next_uop_1_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_iw_p1_speculative_child = next_uop_1_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_iw_p2_speculative_child = next_uop_1_iw_p2_speculative_child; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_p1_bypass_hint = next_uop_1_iw_p1_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_p2_bypass_hint = next_uop_1_iw_p2_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_1_iw_p3_bypass_hint = next_uop_1_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_dis_col_sel = next_uop_1_dis_col_sel; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_1_br_tag = next_uop_1_br_tag; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_1_br_type = next_uop_1_br_type; // @[util.scala:81:26]
wire r_uop_newuop_1_is_sfb = next_uop_1_is_sfb; // @[util.scala:81:26]
wire r_uop_newuop_1_is_fence = next_uop_1_is_fence; // @[util.scala:81:26]
wire r_uop_newuop_1_is_fencei = next_uop_1_is_fencei; // @[util.scala:81:26]
wire r_uop_newuop_1_is_sfence = next_uop_1_is_sfence; // @[util.scala:81:26]
wire r_uop_newuop_1_is_amo = next_uop_1_is_amo; // @[util.scala:81:26]
wire r_uop_newuop_1_is_eret = next_uop_1_is_eret; // @[util.scala:81:26]
wire r_uop_newuop_1_is_sys_pc2epc = next_uop_1_is_sys_pc2epc; // @[util.scala:81:26]
wire r_uop_newuop_1_is_rocc = next_uop_1_is_rocc; // @[util.scala:81:26]
wire r_uop_newuop_1_is_mov = next_uop_1_is_mov; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_ftq_idx = next_uop_1_ftq_idx; // @[util.scala:81:26]
wire r_uop_newuop_1_edge_inst = next_uop_1_edge_inst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_1_pc_lob = next_uop_1_pc_lob; // @[util.scala:81:26]
wire r_uop_newuop_1_taken = next_uop_1_taken; // @[util.scala:81:26]
wire r_uop_newuop_1_imm_rename = next_uop_1_imm_rename; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_imm_sel = next_uop_1_imm_sel; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_pimm = next_uop_1_pimm; // @[util.scala:81:26]
wire [19:0] r_uop_newuop_1_imm_packed = next_uop_1_imm_packed; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_op1_sel = next_uop_1_op1_sel; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_op2_sel = next_uop_1_op2_sel; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_ldst = next_uop_1_fp_ctrl_ldst; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_wen = next_uop_1_fp_ctrl_wen; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_ren1 = next_uop_1_fp_ctrl_ren1; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_ren2 = next_uop_1_fp_ctrl_ren2; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_ren3 = next_uop_1_fp_ctrl_ren3; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_swap12 = next_uop_1_fp_ctrl_swap12; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_swap23 = next_uop_1_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_fp_ctrl_typeTagIn = next_uop_1_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_fp_ctrl_typeTagOut = next_uop_1_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_fromint = next_uop_1_fp_ctrl_fromint; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_toint = next_uop_1_fp_ctrl_toint; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_fastpipe = next_uop_1_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_fma = next_uop_1_fp_ctrl_fma; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_div = next_uop_1_fp_ctrl_div; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_sqrt = next_uop_1_fp_ctrl_sqrt; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_wflags = next_uop_1_fp_ctrl_wflags; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_ctrl_vec = next_uop_1_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_rob_idx = next_uop_1_rob_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_ldq_idx = next_uop_1_ldq_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_stq_idx = next_uop_1_stq_idx; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_rxq_idx = next_uop_1_rxq_idx; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_pdst = next_uop_1_pdst; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_prs1 = next_uop_1_prs1; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_prs2 = next_uop_1_prs2; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_prs3 = next_uop_1_prs3; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_ppred = next_uop_1_ppred; // @[util.scala:81:26]
wire r_uop_newuop_1_prs1_busy = next_uop_1_prs1_busy; // @[util.scala:81:26]
wire r_uop_newuop_1_prs2_busy = next_uop_1_prs2_busy; // @[util.scala:81:26]
wire r_uop_newuop_1_prs3_busy = next_uop_1_prs3_busy; // @[util.scala:81:26]
wire r_uop_newuop_1_ppred_busy = next_uop_1_ppred_busy; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_1_stale_pdst = next_uop_1_stale_pdst; // @[util.scala:81:26]
wire r_uop_newuop_1_exception = next_uop_1_exception; // @[util.scala:81:26]
wire [63:0] r_uop_newuop_1_exc_cause = next_uop_1_exc_cause; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_mem_cmd = next_uop_1_mem_cmd; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_mem_size = next_uop_1_mem_size; // @[util.scala:81:26]
wire r_uop_newuop_1_mem_signed = next_uop_1_mem_signed; // @[util.scala:81:26]
wire r_uop_newuop_1_uses_ldq = next_uop_1_uses_ldq; // @[util.scala:81:26]
wire r_uop_newuop_1_uses_stq = next_uop_1_uses_stq; // @[util.scala:81:26]
wire r_uop_newuop_1_is_unique = next_uop_1_is_unique; // @[util.scala:81:26]
wire r_uop_newuop_1_flush_on_commit = next_uop_1_flush_on_commit; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_csr_cmd = next_uop_1_csr_cmd; // @[util.scala:81:26]
wire r_uop_newuop_1_ldst_is_rs1 = next_uop_1_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_1_ldst = next_uop_1_ldst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_1_lrs1 = next_uop_1_lrs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_1_lrs2 = next_uop_1_lrs2; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_1_lrs3 = next_uop_1_lrs3; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_dst_rtype = next_uop_1_dst_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_lrs1_rtype = next_uop_1_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_lrs2_rtype = next_uop_1_lrs2_rtype; // @[util.scala:81:26]
wire r_uop_newuop_1_frs3_en = next_uop_1_frs3_en; // @[util.scala:81:26]
wire r_uop_newuop_1_fcn_dw = next_uop_1_fcn_dw; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_1_fcn_op = next_uop_1_fcn_op; // @[util.scala:81:26]
wire r_uop_newuop_1_fp_val = next_uop_1_fp_val; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_fp_rm = next_uop_1_fp_rm; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_1_fp_typ = next_uop_1_fp_typ; // @[util.scala:81:26]
wire r_uop_newuop_1_xcpt_pf_if = next_uop_1_xcpt_pf_if; // @[util.scala:81:26]
wire r_uop_newuop_1_xcpt_ae_if = next_uop_1_xcpt_ae_if; // @[util.scala:81:26]
wire r_uop_newuop_1_xcpt_ma_if = next_uop_1_xcpt_ma_if; // @[util.scala:81:26]
wire r_uop_newuop_1_bp_debug_if = next_uop_1_bp_debug_if; // @[util.scala:81:26]
wire r_uop_newuop_1_bp_xcpt_if = next_uop_1_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_debug_fsrc = next_uop_1_debug_fsrc; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_1_debug_tsrc = next_uop_1_debug_tsrc; // @[util.scala:81:26]
wire [15:0] next_uop_1_br_mask; // @[rename-stage.scala:95:24]
wire _r_valid_T_2 = ~io_dis_fire_1_0; // @[rename-stage.scala:105:29, :414:7]
wire _r_valid_T_3 = r_valid_1 & _r_valid_T_2; // @[rename-stage.scala:93:27, :105:{26,29}]
assign next_uop_1_inst = _GEN ? r_uop_1_inst : ren1_uops_1_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_debug_inst = _GEN ? r_uop_1_debug_inst : ren1_uops_1_debug_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_rvc = _GEN ? r_uop_1_is_rvc : ren1_uops_1_is_rvc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_debug_pc = _GEN ? r_uop_1_debug_pc : ren1_uops_1_debug_pc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iq_type_0 = _GEN ? r_uop_1_iq_type_0 : ren1_uops_1_iq_type_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iq_type_1 = _GEN ? r_uop_1_iq_type_1 : ren1_uops_1_iq_type_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iq_type_2 = _GEN ? r_uop_1_iq_type_2 : ren1_uops_1_iq_type_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iq_type_3 = _GEN ? r_uop_1_iq_type_3 : ren1_uops_1_iq_type_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_0 = _GEN ? r_uop_1_fu_code_0 : ren1_uops_1_fu_code_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_1 = _GEN ? r_uop_1_fu_code_1 : ren1_uops_1_fu_code_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_2 = _GEN ? r_uop_1_fu_code_2 : ren1_uops_1_fu_code_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_3 = _GEN ? r_uop_1_fu_code_3 : ren1_uops_1_fu_code_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_4 = _GEN ? r_uop_1_fu_code_4 : ren1_uops_1_fu_code_4; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_5 = _GEN ? r_uop_1_fu_code_5 : ren1_uops_1_fu_code_5; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_6 = _GEN ? r_uop_1_fu_code_6 : ren1_uops_1_fu_code_6; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_7 = _GEN ? r_uop_1_fu_code_7 : ren1_uops_1_fu_code_7; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_8 = _GEN ? r_uop_1_fu_code_8 : ren1_uops_1_fu_code_8; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fu_code_9 = _GEN ? r_uop_1_fu_code_9 : ren1_uops_1_fu_code_9; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_issued = _GEN & r_uop_1_iw_issued; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_issued_partial_agen = _GEN & r_uop_1_iw_issued_partial_agen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_issued_partial_dgen = _GEN & r_uop_1_iw_issued_partial_dgen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_p1_speculative_child = _GEN ? r_uop_1_iw_p1_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_p2_speculative_child = _GEN ? r_uop_1_iw_p2_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_p1_bypass_hint = _GEN & r_uop_1_iw_p1_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_p2_bypass_hint = _GEN & r_uop_1_iw_p2_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_iw_p3_bypass_hint = _GEN & r_uop_1_iw_p3_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_dis_col_sel = _GEN ? r_uop_1_dis_col_sel : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_br_mask = _GEN ? r_uop_1_br_mask : ren1_uops_1_br_mask; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_br_tag = _GEN ? r_uop_1_br_tag : ren1_uops_1_br_tag; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_br_type = _GEN ? r_uop_1_br_type : ren1_uops_1_br_type; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_sfb = _GEN ? r_uop_1_is_sfb : ren1_uops_1_is_sfb; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_fence = _GEN ? r_uop_1_is_fence : ren1_uops_1_is_fence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_fencei = _GEN ? r_uop_1_is_fencei : ren1_uops_1_is_fencei; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_sfence = _GEN ? r_uop_1_is_sfence : ren1_uops_1_is_sfence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_amo = _GEN ? r_uop_1_is_amo : ren1_uops_1_is_amo; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_eret = _GEN ? r_uop_1_is_eret : ren1_uops_1_is_eret; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_sys_pc2epc = _GEN ? r_uop_1_is_sys_pc2epc : ren1_uops_1_is_sys_pc2epc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_rocc = _GEN ? r_uop_1_is_rocc : ren1_uops_1_is_rocc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_mov = _GEN ? r_uop_1_is_mov : ren1_uops_1_is_mov; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ftq_idx = _GEN ? r_uop_1_ftq_idx : ren1_uops_1_ftq_idx; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_edge_inst = _GEN ? r_uop_1_edge_inst : ren1_uops_1_edge_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_pc_lob = _GEN ? r_uop_1_pc_lob : ren1_uops_1_pc_lob; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_taken = _GEN ? r_uop_1_taken : ren1_uops_1_taken; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_imm_rename = _GEN ? r_uop_1_imm_rename : ren1_uops_1_imm_rename; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_imm_sel = _GEN ? r_uop_1_imm_sel : ren1_uops_1_imm_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_pimm = _GEN ? r_uop_1_pimm : ren1_uops_1_pimm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_imm_packed = _GEN ? r_uop_1_imm_packed : ren1_uops_1_imm_packed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_op1_sel = _GEN ? r_uop_1_op1_sel : ren1_uops_1_op1_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_op2_sel = _GEN ? r_uop_1_op2_sel : ren1_uops_1_op2_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_ldst = _GEN ? r_uop_1_fp_ctrl_ldst : ren1_uops_1_fp_ctrl_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_wen = _GEN ? r_uop_1_fp_ctrl_wen : ren1_uops_1_fp_ctrl_wen; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_ren1 = _GEN ? r_uop_1_fp_ctrl_ren1 : ren1_uops_1_fp_ctrl_ren1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_ren2 = _GEN ? r_uop_1_fp_ctrl_ren2 : ren1_uops_1_fp_ctrl_ren2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_ren3 = _GEN ? r_uop_1_fp_ctrl_ren3 : ren1_uops_1_fp_ctrl_ren3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_swap12 = _GEN ? r_uop_1_fp_ctrl_swap12 : ren1_uops_1_fp_ctrl_swap12; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_swap23 = _GEN ? r_uop_1_fp_ctrl_swap23 : ren1_uops_1_fp_ctrl_swap23; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_typeTagIn = _GEN ? r_uop_1_fp_ctrl_typeTagIn : ren1_uops_1_fp_ctrl_typeTagIn; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_typeTagOut = _GEN ? r_uop_1_fp_ctrl_typeTagOut : ren1_uops_1_fp_ctrl_typeTagOut; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_fromint = _GEN ? r_uop_1_fp_ctrl_fromint : ren1_uops_1_fp_ctrl_fromint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_toint = _GEN ? r_uop_1_fp_ctrl_toint : ren1_uops_1_fp_ctrl_toint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_fastpipe = _GEN ? r_uop_1_fp_ctrl_fastpipe : ren1_uops_1_fp_ctrl_fastpipe; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_fma = _GEN ? r_uop_1_fp_ctrl_fma : ren1_uops_1_fp_ctrl_fma; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_div = _GEN ? r_uop_1_fp_ctrl_div : ren1_uops_1_fp_ctrl_div; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_sqrt = _GEN ? r_uop_1_fp_ctrl_sqrt : ren1_uops_1_fp_ctrl_sqrt; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_wflags = _GEN ? r_uop_1_fp_ctrl_wflags : ren1_uops_1_fp_ctrl_wflags; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_ctrl_vec = _GEN & r_uop_1_fp_ctrl_vec; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_rob_idx = _GEN ? r_uop_1_rob_idx : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ldq_idx = _GEN ? r_uop_1_ldq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_stq_idx = _GEN ? r_uop_1_stq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_rxq_idx = _GEN ? r_uop_1_rxq_idx : 2'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_pdst = _GEN ? r_uop_1_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs1 = _GEN ? r_uop_1_prs1 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs2 = _GEN ? r_uop_1_prs2 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs3 = _GEN ? r_uop_1_prs3 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ppred = _GEN ? r_uop_1_ppred : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs1_busy = _GEN & r_uop_1_prs1_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs2_busy = _GEN & r_uop_1_prs2_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_prs3_busy = _GEN & r_uop_1_prs3_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ppred_busy = _GEN & r_uop_1_ppred_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_stale_pdst = _GEN ? r_uop_1_stale_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_exception = _GEN ? r_uop_1_exception : ren1_uops_1_exception; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_exc_cause = _GEN ? r_uop_1_exc_cause : ren1_uops_1_exc_cause; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_mem_cmd = _GEN ? r_uop_1_mem_cmd : ren1_uops_1_mem_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_mem_size = _GEN ? r_uop_1_mem_size : ren1_uops_1_mem_size; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_mem_signed = _GEN ? r_uop_1_mem_signed : ren1_uops_1_mem_signed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_uses_ldq = _GEN ? r_uop_1_uses_ldq : ren1_uops_1_uses_ldq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_uses_stq = _GEN ? r_uop_1_uses_stq : ren1_uops_1_uses_stq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_is_unique = _GEN ? r_uop_1_is_unique : ren1_uops_1_is_unique; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_flush_on_commit = _GEN ? r_uop_1_flush_on_commit : ren1_uops_1_flush_on_commit; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_csr_cmd = _GEN ? r_uop_1_csr_cmd : ren1_uops_1_csr_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ldst_is_rs1 = _GEN ? r_uop_1_ldst_is_rs1 : ren1_uops_1_ldst_is_rs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_ldst = _GEN ? r_uop_1_ldst : ren1_uops_1_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_lrs1 = _GEN ? r_uop_1_lrs1 : ren1_uops_1_lrs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_lrs2 = _GEN ? r_uop_1_lrs2 : ren1_uops_1_lrs2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_lrs3 = _GEN ? r_uop_1_lrs3 : ren1_uops_1_lrs3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_dst_rtype = _GEN ? r_uop_1_dst_rtype : ren1_uops_1_dst_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_lrs1_rtype = _GEN ? r_uop_1_lrs1_rtype : ren1_uops_1_lrs1_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_lrs2_rtype = _GEN ? r_uop_1_lrs2_rtype : ren1_uops_1_lrs2_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_frs3_en = _GEN ? r_uop_1_frs3_en : ren1_uops_1_frs3_en; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fcn_dw = _GEN ? r_uop_1_fcn_dw : ren1_uops_1_fcn_dw; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fcn_op = _GEN ? r_uop_1_fcn_op : ren1_uops_1_fcn_op; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_val = _GEN ? r_uop_1_fp_val : ren1_uops_1_fp_val; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_rm = _GEN ? r_uop_1_fp_rm : ren1_uops_1_fp_rm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_fp_typ = _GEN ? r_uop_1_fp_typ : ren1_uops_1_fp_typ; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_xcpt_pf_if = _GEN ? r_uop_1_xcpt_pf_if : ren1_uops_1_xcpt_pf_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_xcpt_ae_if = _GEN ? r_uop_1_xcpt_ae_if : ren1_uops_1_xcpt_ae_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_xcpt_ma_if = _GEN & r_uop_1_xcpt_ma_if; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_bp_debug_if = _GEN ? r_uop_1_bp_debug_if : ren1_uops_1_bp_debug_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_bp_xcpt_if = _GEN ? r_uop_1_bp_xcpt_if : ren1_uops_1_bp_xcpt_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_debug_fsrc = _GEN ? r_uop_1_debug_fsrc : ren1_uops_1_debug_fsrc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_1_debug_tsrc = _GEN ? r_uop_1_debug_tsrc : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
wire [15:0] _r_uop_newuop_br_mask_T_3; // @[util.scala:82:35]
wire [15:0] r_uop_newuop_1_br_mask; // @[util.scala:81:26]
wire [15:0] _r_uop_newuop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _r_uop_newuop_br_mask_T_3 = next_uop_1_br_mask & _r_uop_newuop_br_mask_T_2; // @[util.scala:82:{35,37}]
assign r_uop_newuop_1_br_mask = _r_uop_newuop_br_mask_T_3; // @[util.scala:81:26, :82:35]
wire _ren2_br_tags_2_valid_T = ren2_uops_1_br_type == 4'h1; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_1 = ren2_uops_1_br_type == 4'h2; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_2 = ren2_uops_1_br_type == 4'h3; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_3 = ren2_uops_1_br_type == 4'h4; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_4 = ren2_uops_1_br_type == 4'h5; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_5 = ren2_uops_1_br_type == 4'h6; // @[package.scala:16:47]
wire _ren2_br_tags_2_valid_T_6 = _ren2_br_tags_2_valid_T | _ren2_br_tags_2_valid_T_1; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_2_valid_T_7 = _ren2_br_tags_2_valid_T_6 | _ren2_br_tags_2_valid_T_2; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_2_valid_T_8 = _ren2_br_tags_2_valid_T_7 | _ren2_br_tags_2_valid_T_3; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_2_valid_T_9 = _ren2_br_tags_2_valid_T_8 | _ren2_br_tags_2_valid_T_4; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_2_valid_T_10 = _ren2_br_tags_2_valid_T_9 | _ren2_br_tags_2_valid_T_5; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_2_valid_T_11 = ~ren2_uops_1_is_sfb; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_2_valid_T_12 = _ren2_br_tags_2_valid_T_10 & _ren2_br_tags_2_valid_T_11; // @[package.scala:81:59]
wire _ren2_br_tags_2_valid_T_13 = ren2_uops_1_br_type == 4'h8; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_2_valid_T_14 = _ren2_br_tags_2_valid_T_12 | _ren2_br_tags_2_valid_T_13; // @[micro-op.scala:119:34, :160:{33,45}]
assign _ren2_br_tags_2_valid_T_15 = io_dis_fire_1_0 & _ren2_br_tags_2_valid_T_14; // @[rename-stage.scala:117:45, :414:7]
assign ren2_br_tags_2_valid = _ren2_br_tags_2_valid_T_15; // @[rename-stage.scala:80:29, :117:45]
reg r_valid_2; // @[rename-stage.scala:93:27]
assign ren2_valids_2 = r_valid_2; // @[rename-stage.scala:76:29, :93:27]
reg [31:0] r_uop_2_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_inst = r_uop_2_inst; // @[rename-stage.scala:77:29, :94:23]
reg [31:0] r_uop_2_debug_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_debug_inst = r_uop_2_debug_inst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_rvc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_rvc = r_uop_2_is_rvc; // @[rename-stage.scala:77:29, :94:23]
reg [39:0] r_uop_2_debug_pc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_debug_pc = r_uop_2_debug_pc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iq_type_0; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iq_type_0 = r_uop_2_iq_type_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iq_type_1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iq_type_1 = r_uop_2_iq_type_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iq_type_2; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iq_type_2 = r_uop_2_iq_type_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iq_type_3; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iq_type_3 = r_uop_2_iq_type_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_0; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_0 = r_uop_2_fu_code_0; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_1 = r_uop_2_fu_code_1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_2; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_2 = r_uop_2_fu_code_2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_3; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_3 = r_uop_2_fu_code_3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_4; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_4 = r_uop_2_fu_code_4; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_5; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_5 = r_uop_2_fu_code_5; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_6; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_6 = r_uop_2_fu_code_6; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_7; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_7 = r_uop_2_fu_code_7; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_8; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_8 = r_uop_2_fu_code_8; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fu_code_9; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fu_code_9 = r_uop_2_fu_code_9; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_issued; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_issued = r_uop_2_iw_issued; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_issued_partial_agen; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_issued_partial_agen = r_uop_2_iw_issued_partial_agen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_issued_partial_dgen; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_issued_partial_dgen = r_uop_2_iw_issued_partial_dgen; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_iw_p1_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_p1_speculative_child = r_uop_2_iw_p1_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_iw_p2_speculative_child; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_p2_speculative_child = r_uop_2_iw_p2_speculative_child; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_p1_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_p1_bypass_hint = r_uop_2_iw_p1_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_p2_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_p2_bypass_hint = r_uop_2_iw_p2_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_iw_p3_bypass_hint; // @[rename-stage.scala:94:23]
assign ren2_uops_2_iw_p3_bypass_hint = r_uop_2_iw_p3_bypass_hint; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_dis_col_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_2_dis_col_sel = r_uop_2_dis_col_sel; // @[rename-stage.scala:77:29, :94:23]
reg [15:0] r_uop_2_br_mask; // @[rename-stage.scala:94:23]
assign ren2_uops_2_br_mask = r_uop_2_br_mask; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_2_br_tag; // @[rename-stage.scala:94:23]
assign ren2_uops_2_br_tag = r_uop_2_br_tag; // @[rename-stage.scala:77:29, :94:23]
reg [3:0] r_uop_2_br_type; // @[rename-stage.scala:94:23]
assign ren2_uops_2_br_type = r_uop_2_br_type; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_sfb; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_sfb = r_uop_2_is_sfb; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_fence; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_fence = r_uop_2_is_fence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_fencei; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_fencei = r_uop_2_is_fencei; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_sfence; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_sfence = r_uop_2_is_sfence; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_amo; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_amo = r_uop_2_is_amo; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_eret; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_eret = r_uop_2_is_eret; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_sys_pc2epc = r_uop_2_is_sys_pc2epc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_rocc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_rocc = r_uop_2_is_rocc; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_mov; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_mov = r_uop_2_is_mov; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_ftq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ftq_idx = r_uop_2_ftq_idx; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_edge_inst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_edge_inst = r_uop_2_edge_inst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_2_pc_lob; // @[rename-stage.scala:94:23]
assign ren2_uops_2_pc_lob = r_uop_2_pc_lob; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_taken; // @[rename-stage.scala:94:23]
assign ren2_uops_2_taken = r_uop_2_taken; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_imm_rename; // @[rename-stage.scala:94:23]
assign ren2_uops_2_imm_rename = r_uop_2_imm_rename; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_imm_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_2_imm_sel = r_uop_2_imm_sel; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_pimm; // @[rename-stage.scala:94:23]
assign ren2_uops_2_pimm = r_uop_2_pimm; // @[rename-stage.scala:77:29, :94:23]
reg [19:0] r_uop_2_imm_packed; // @[rename-stage.scala:94:23]
assign ren2_uops_2_imm_packed = r_uop_2_imm_packed; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_op1_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_2_op1_sel = r_uop_2_op1_sel; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_op2_sel; // @[rename-stage.scala:94:23]
assign ren2_uops_2_op2_sel = r_uop_2_op2_sel; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_ldst = r_uop_2_fp_ctrl_ldst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_wen; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_wen = r_uop_2_fp_ctrl_wen; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_ren1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_ren1 = r_uop_2_fp_ctrl_ren1; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_ren2; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_ren2 = r_uop_2_fp_ctrl_ren2; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_ren3; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_ren3 = r_uop_2_fp_ctrl_ren3; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_swap12; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_swap12 = r_uop_2_fp_ctrl_swap12; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_swap23; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_swap23 = r_uop_2_fp_ctrl_swap23; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_typeTagIn = r_uop_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_typeTagOut = r_uop_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_fromint; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_fromint = r_uop_2_fp_ctrl_fromint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_toint; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_toint = r_uop_2_fp_ctrl_toint; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_fastpipe; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_fastpipe = r_uop_2_fp_ctrl_fastpipe; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_fma; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_fma = r_uop_2_fp_ctrl_fma; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_div; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_div = r_uop_2_fp_ctrl_div; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_sqrt; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_sqrt = r_uop_2_fp_ctrl_sqrt; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_wflags; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_wflags = r_uop_2_fp_ctrl_wflags; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_ctrl_vec; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_ctrl_vec = r_uop_2_fp_ctrl_vec; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_rob_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_2_rob_idx = r_uop_2_rob_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_ldq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ldq_idx = r_uop_2_ldq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_stq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_2_stq_idx = r_uop_2_stq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_rxq_idx; // @[rename-stage.scala:94:23]
assign ren2_uops_2_rxq_idx = r_uop_2_rxq_idx; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_pdst = r_uop_2_pdst; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_prs1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs1 = r_uop_2_prs1; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_prs2; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs2 = r_uop_2_prs2; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_prs3; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs3 = r_uop_2_prs3; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_ppred; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ppred = r_uop_2_ppred; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_prs1_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs1_busy = r_uop_2_prs1_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_prs2_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs2_busy = r_uop_2_prs2_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_prs3_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_2_prs3_busy = r_uop_2_prs3_busy; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_ppred_busy; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ppred_busy = r_uop_2_ppred_busy; // @[rename-stage.scala:77:29, :94:23]
reg [6:0] r_uop_2_stale_pdst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_stale_pdst = r_uop_2_stale_pdst; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_exception; // @[rename-stage.scala:94:23]
assign ren2_uops_2_exception = r_uop_2_exception; // @[rename-stage.scala:77:29, :94:23]
reg [63:0] r_uop_2_exc_cause; // @[rename-stage.scala:94:23]
assign ren2_uops_2_exc_cause = r_uop_2_exc_cause; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_mem_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_2_mem_cmd = r_uop_2_mem_cmd; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_mem_size; // @[rename-stage.scala:94:23]
assign ren2_uops_2_mem_size = r_uop_2_mem_size; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_mem_signed; // @[rename-stage.scala:94:23]
assign ren2_uops_2_mem_signed = r_uop_2_mem_signed; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_uses_ldq; // @[rename-stage.scala:94:23]
assign ren2_uops_2_uses_ldq = r_uop_2_uses_ldq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_uses_stq; // @[rename-stage.scala:94:23]
assign ren2_uops_2_uses_stq = r_uop_2_uses_stq; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_is_unique; // @[rename-stage.scala:94:23]
assign ren2_uops_2_is_unique = r_uop_2_is_unique; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_flush_on_commit; // @[rename-stage.scala:94:23]
assign ren2_uops_2_flush_on_commit = r_uop_2_flush_on_commit; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_csr_cmd; // @[rename-stage.scala:94:23]
assign ren2_uops_2_csr_cmd = r_uop_2_csr_cmd; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_ldst_is_rs1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ldst_is_rs1 = r_uop_2_ldst_is_rs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_2_ldst; // @[rename-stage.scala:94:23]
assign ren2_uops_2_ldst = r_uop_2_ldst; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_2_lrs1; // @[rename-stage.scala:94:23]
assign ren2_uops_2_lrs1 = r_uop_2_lrs1; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_2_lrs2; // @[rename-stage.scala:94:23]
assign ren2_uops_2_lrs2 = r_uop_2_lrs2; // @[rename-stage.scala:77:29, :94:23]
reg [5:0] r_uop_2_lrs3; // @[rename-stage.scala:94:23]
assign ren2_uops_2_lrs3 = r_uop_2_lrs3; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_dst_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_2_dst_rtype = r_uop_2_dst_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_lrs1_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_2_lrs1_rtype = r_uop_2_lrs1_rtype; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_lrs2_rtype; // @[rename-stage.scala:94:23]
assign ren2_uops_2_lrs2_rtype = r_uop_2_lrs2_rtype; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_frs3_en; // @[rename-stage.scala:94:23]
assign ren2_uops_2_frs3_en = r_uop_2_frs3_en; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fcn_dw; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fcn_dw = r_uop_2_fcn_dw; // @[rename-stage.scala:77:29, :94:23]
reg [4:0] r_uop_2_fcn_op; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fcn_op = r_uop_2_fcn_op; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_fp_val; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_val = r_uop_2_fp_val; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_fp_rm; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_rm = r_uop_2_fp_rm; // @[rename-stage.scala:77:29, :94:23]
reg [1:0] r_uop_2_fp_typ; // @[rename-stage.scala:94:23]
assign ren2_uops_2_fp_typ = r_uop_2_fp_typ; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_xcpt_pf_if; // @[rename-stage.scala:94:23]
assign ren2_uops_2_xcpt_pf_if = r_uop_2_xcpt_pf_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_xcpt_ae_if; // @[rename-stage.scala:94:23]
assign ren2_uops_2_xcpt_ae_if = r_uop_2_xcpt_ae_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_xcpt_ma_if; // @[rename-stage.scala:94:23]
assign ren2_uops_2_xcpt_ma_if = r_uop_2_xcpt_ma_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_bp_debug_if; // @[rename-stage.scala:94:23]
assign ren2_uops_2_bp_debug_if = r_uop_2_bp_debug_if; // @[rename-stage.scala:77:29, :94:23]
reg r_uop_2_bp_xcpt_if; // @[rename-stage.scala:94:23]
assign ren2_uops_2_bp_xcpt_if = r_uop_2_bp_xcpt_if; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_debug_fsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_debug_fsrc = r_uop_2_debug_fsrc; // @[rename-stage.scala:77:29, :94:23]
reg [2:0] r_uop_2_debug_tsrc; // @[rename-stage.scala:94:23]
assign ren2_uops_2_debug_tsrc = r_uop_2_debug_tsrc; // @[rename-stage.scala:77:29, :94:23]
wire [31:0] r_uop_newuop_2_inst = next_uop_2_inst; // @[util.scala:81:26]
wire [31:0] r_uop_newuop_2_debug_inst = next_uop_2_debug_inst; // @[util.scala:81:26]
wire r_uop_newuop_2_is_rvc = next_uop_2_is_rvc; // @[util.scala:81:26]
wire [39:0] r_uop_newuop_2_debug_pc = next_uop_2_debug_pc; // @[util.scala:81:26]
wire r_uop_newuop_2_iq_type_0 = next_uop_2_iq_type_0; // @[util.scala:81:26]
wire r_uop_newuop_2_iq_type_1 = next_uop_2_iq_type_1; // @[util.scala:81:26]
wire r_uop_newuop_2_iq_type_2 = next_uop_2_iq_type_2; // @[util.scala:81:26]
wire r_uop_newuop_2_iq_type_3 = next_uop_2_iq_type_3; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_0 = next_uop_2_fu_code_0; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_1 = next_uop_2_fu_code_1; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_2 = next_uop_2_fu_code_2; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_3 = next_uop_2_fu_code_3; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_4 = next_uop_2_fu_code_4; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_5 = next_uop_2_fu_code_5; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_6 = next_uop_2_fu_code_6; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_7 = next_uop_2_fu_code_7; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_8 = next_uop_2_fu_code_8; // @[util.scala:81:26]
wire r_uop_newuop_2_fu_code_9 = next_uop_2_fu_code_9; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_issued = next_uop_2_iw_issued; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_issued_partial_agen = next_uop_2_iw_issued_partial_agen; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_issued_partial_dgen = next_uop_2_iw_issued_partial_dgen; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_iw_p1_speculative_child = next_uop_2_iw_p1_speculative_child; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_iw_p2_speculative_child = next_uop_2_iw_p2_speculative_child; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_p1_bypass_hint = next_uop_2_iw_p1_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_p2_bypass_hint = next_uop_2_iw_p2_bypass_hint; // @[util.scala:81:26]
wire r_uop_newuop_2_iw_p3_bypass_hint = next_uop_2_iw_p3_bypass_hint; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_dis_col_sel = next_uop_2_dis_col_sel; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_2_br_tag = next_uop_2_br_tag; // @[util.scala:81:26]
wire [3:0] r_uop_newuop_2_br_type = next_uop_2_br_type; // @[util.scala:81:26]
wire r_uop_newuop_2_is_sfb = next_uop_2_is_sfb; // @[util.scala:81:26]
wire r_uop_newuop_2_is_fence = next_uop_2_is_fence; // @[util.scala:81:26]
wire r_uop_newuop_2_is_fencei = next_uop_2_is_fencei; // @[util.scala:81:26]
wire r_uop_newuop_2_is_sfence = next_uop_2_is_sfence; // @[util.scala:81:26]
wire r_uop_newuop_2_is_amo = next_uop_2_is_amo; // @[util.scala:81:26]
wire r_uop_newuop_2_is_eret = next_uop_2_is_eret; // @[util.scala:81:26]
wire r_uop_newuop_2_is_sys_pc2epc = next_uop_2_is_sys_pc2epc; // @[util.scala:81:26]
wire r_uop_newuop_2_is_rocc = next_uop_2_is_rocc; // @[util.scala:81:26]
wire r_uop_newuop_2_is_mov = next_uop_2_is_mov; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_ftq_idx = next_uop_2_ftq_idx; // @[util.scala:81:26]
wire r_uop_newuop_2_edge_inst = next_uop_2_edge_inst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_2_pc_lob = next_uop_2_pc_lob; // @[util.scala:81:26]
wire r_uop_newuop_2_taken = next_uop_2_taken; // @[util.scala:81:26]
wire r_uop_newuop_2_imm_rename = next_uop_2_imm_rename; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_imm_sel = next_uop_2_imm_sel; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_pimm = next_uop_2_pimm; // @[util.scala:81:26]
wire [19:0] r_uop_newuop_2_imm_packed = next_uop_2_imm_packed; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_op1_sel = next_uop_2_op1_sel; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_op2_sel = next_uop_2_op2_sel; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_ldst = next_uop_2_fp_ctrl_ldst; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_wen = next_uop_2_fp_ctrl_wen; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_ren1 = next_uop_2_fp_ctrl_ren1; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_ren2 = next_uop_2_fp_ctrl_ren2; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_ren3 = next_uop_2_fp_ctrl_ren3; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_swap12 = next_uop_2_fp_ctrl_swap12; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_swap23 = next_uop_2_fp_ctrl_swap23; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_fp_ctrl_typeTagIn = next_uop_2_fp_ctrl_typeTagIn; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_fp_ctrl_typeTagOut = next_uop_2_fp_ctrl_typeTagOut; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_fromint = next_uop_2_fp_ctrl_fromint; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_toint = next_uop_2_fp_ctrl_toint; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_fastpipe = next_uop_2_fp_ctrl_fastpipe; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_fma = next_uop_2_fp_ctrl_fma; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_div = next_uop_2_fp_ctrl_div; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_sqrt = next_uop_2_fp_ctrl_sqrt; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_wflags = next_uop_2_fp_ctrl_wflags; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_ctrl_vec = next_uop_2_fp_ctrl_vec; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_rob_idx = next_uop_2_rob_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_ldq_idx = next_uop_2_ldq_idx; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_stq_idx = next_uop_2_stq_idx; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_rxq_idx = next_uop_2_rxq_idx; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_pdst = next_uop_2_pdst; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_prs1 = next_uop_2_prs1; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_prs2 = next_uop_2_prs2; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_prs3 = next_uop_2_prs3; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_ppred = next_uop_2_ppred; // @[util.scala:81:26]
wire r_uop_newuop_2_prs1_busy = next_uop_2_prs1_busy; // @[util.scala:81:26]
wire r_uop_newuop_2_prs2_busy = next_uop_2_prs2_busy; // @[util.scala:81:26]
wire r_uop_newuop_2_prs3_busy = next_uop_2_prs3_busy; // @[util.scala:81:26]
wire r_uop_newuop_2_ppred_busy = next_uop_2_ppred_busy; // @[util.scala:81:26]
wire [6:0] r_uop_newuop_2_stale_pdst = next_uop_2_stale_pdst; // @[util.scala:81:26]
wire r_uop_newuop_2_exception = next_uop_2_exception; // @[util.scala:81:26]
wire [63:0] r_uop_newuop_2_exc_cause = next_uop_2_exc_cause; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_mem_cmd = next_uop_2_mem_cmd; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_mem_size = next_uop_2_mem_size; // @[util.scala:81:26]
wire r_uop_newuop_2_mem_signed = next_uop_2_mem_signed; // @[util.scala:81:26]
wire r_uop_newuop_2_uses_ldq = next_uop_2_uses_ldq; // @[util.scala:81:26]
wire r_uop_newuop_2_uses_stq = next_uop_2_uses_stq; // @[util.scala:81:26]
wire r_uop_newuop_2_is_unique = next_uop_2_is_unique; // @[util.scala:81:26]
wire r_uop_newuop_2_flush_on_commit = next_uop_2_flush_on_commit; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_csr_cmd = next_uop_2_csr_cmd; // @[util.scala:81:26]
wire r_uop_newuop_2_ldst_is_rs1 = next_uop_2_ldst_is_rs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_2_ldst = next_uop_2_ldst; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_2_lrs1 = next_uop_2_lrs1; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_2_lrs2 = next_uop_2_lrs2; // @[util.scala:81:26]
wire [5:0] r_uop_newuop_2_lrs3 = next_uop_2_lrs3; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_dst_rtype = next_uop_2_dst_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_lrs1_rtype = next_uop_2_lrs1_rtype; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_lrs2_rtype = next_uop_2_lrs2_rtype; // @[util.scala:81:26]
wire r_uop_newuop_2_frs3_en = next_uop_2_frs3_en; // @[util.scala:81:26]
wire r_uop_newuop_2_fcn_dw = next_uop_2_fcn_dw; // @[util.scala:81:26]
wire [4:0] r_uop_newuop_2_fcn_op = next_uop_2_fcn_op; // @[util.scala:81:26]
wire r_uop_newuop_2_fp_val = next_uop_2_fp_val; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_fp_rm = next_uop_2_fp_rm; // @[util.scala:81:26]
wire [1:0] r_uop_newuop_2_fp_typ = next_uop_2_fp_typ; // @[util.scala:81:26]
wire r_uop_newuop_2_xcpt_pf_if = next_uop_2_xcpt_pf_if; // @[util.scala:81:26]
wire r_uop_newuop_2_xcpt_ae_if = next_uop_2_xcpt_ae_if; // @[util.scala:81:26]
wire r_uop_newuop_2_xcpt_ma_if = next_uop_2_xcpt_ma_if; // @[util.scala:81:26]
wire r_uop_newuop_2_bp_debug_if = next_uop_2_bp_debug_if; // @[util.scala:81:26]
wire r_uop_newuop_2_bp_xcpt_if = next_uop_2_bp_xcpt_if; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_debug_fsrc = next_uop_2_debug_fsrc; // @[util.scala:81:26]
wire [2:0] r_uop_newuop_2_debug_tsrc = next_uop_2_debug_tsrc; // @[util.scala:81:26]
wire [15:0] next_uop_2_br_mask; // @[rename-stage.scala:95:24]
wire _r_valid_T_4 = ~io_dis_fire_2_0; // @[rename-stage.scala:105:29, :414:7]
wire _r_valid_T_5 = r_valid_2 & _r_valid_T_4; // @[rename-stage.scala:93:27, :105:{26,29}]
assign next_uop_2_inst = _GEN ? r_uop_2_inst : ren1_uops_2_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_debug_inst = _GEN ? r_uop_2_debug_inst : ren1_uops_2_debug_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_rvc = _GEN ? r_uop_2_is_rvc : ren1_uops_2_is_rvc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_debug_pc = _GEN ? r_uop_2_debug_pc : ren1_uops_2_debug_pc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iq_type_0 = _GEN ? r_uop_2_iq_type_0 : ren1_uops_2_iq_type_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iq_type_1 = _GEN ? r_uop_2_iq_type_1 : ren1_uops_2_iq_type_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iq_type_2 = _GEN ? r_uop_2_iq_type_2 : ren1_uops_2_iq_type_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iq_type_3 = _GEN ? r_uop_2_iq_type_3 : ren1_uops_2_iq_type_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_0 = _GEN ? r_uop_2_fu_code_0 : ren1_uops_2_fu_code_0; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_1 = _GEN ? r_uop_2_fu_code_1 : ren1_uops_2_fu_code_1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_2 = _GEN ? r_uop_2_fu_code_2 : ren1_uops_2_fu_code_2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_3 = _GEN ? r_uop_2_fu_code_3 : ren1_uops_2_fu_code_3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_4 = _GEN ? r_uop_2_fu_code_4 : ren1_uops_2_fu_code_4; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_5 = _GEN ? r_uop_2_fu_code_5 : ren1_uops_2_fu_code_5; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_6 = _GEN ? r_uop_2_fu_code_6 : ren1_uops_2_fu_code_6; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_7 = _GEN ? r_uop_2_fu_code_7 : ren1_uops_2_fu_code_7; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_8 = _GEN ? r_uop_2_fu_code_8 : ren1_uops_2_fu_code_8; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fu_code_9 = _GEN ? r_uop_2_fu_code_9 : ren1_uops_2_fu_code_9; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_issued = _GEN & r_uop_2_iw_issued; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_issued_partial_agen = _GEN & r_uop_2_iw_issued_partial_agen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_issued_partial_dgen = _GEN & r_uop_2_iw_issued_partial_dgen; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_p1_speculative_child = _GEN ? r_uop_2_iw_p1_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_p2_speculative_child = _GEN ? r_uop_2_iw_p2_speculative_child : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_p1_bypass_hint = _GEN & r_uop_2_iw_p1_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_p2_bypass_hint = _GEN & r_uop_2_iw_p2_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_iw_p3_bypass_hint = _GEN & r_uop_2_iw_p3_bypass_hint; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_dis_col_sel = _GEN ? r_uop_2_dis_col_sel : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_br_mask = _GEN ? r_uop_2_br_mask : ren1_uops_2_br_mask; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_br_tag = _GEN ? r_uop_2_br_tag : ren1_uops_2_br_tag; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_br_type = _GEN ? r_uop_2_br_type : ren1_uops_2_br_type; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_sfb = _GEN ? r_uop_2_is_sfb : ren1_uops_2_is_sfb; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_fence = _GEN ? r_uop_2_is_fence : ren1_uops_2_is_fence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_fencei = _GEN ? r_uop_2_is_fencei : ren1_uops_2_is_fencei; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_sfence = _GEN ? r_uop_2_is_sfence : ren1_uops_2_is_sfence; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_amo = _GEN ? r_uop_2_is_amo : ren1_uops_2_is_amo; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_eret = _GEN ? r_uop_2_is_eret : ren1_uops_2_is_eret; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_sys_pc2epc = _GEN ? r_uop_2_is_sys_pc2epc : ren1_uops_2_is_sys_pc2epc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_rocc = _GEN ? r_uop_2_is_rocc : ren1_uops_2_is_rocc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_mov = _GEN ? r_uop_2_is_mov : ren1_uops_2_is_mov; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ftq_idx = _GEN ? r_uop_2_ftq_idx : ren1_uops_2_ftq_idx; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_edge_inst = _GEN ? r_uop_2_edge_inst : ren1_uops_2_edge_inst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_pc_lob = _GEN ? r_uop_2_pc_lob : ren1_uops_2_pc_lob; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_taken = _GEN ? r_uop_2_taken : ren1_uops_2_taken; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_imm_rename = _GEN ? r_uop_2_imm_rename : ren1_uops_2_imm_rename; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_imm_sel = _GEN ? r_uop_2_imm_sel : ren1_uops_2_imm_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_pimm = _GEN ? r_uop_2_pimm : ren1_uops_2_pimm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_imm_packed = _GEN ? r_uop_2_imm_packed : ren1_uops_2_imm_packed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_op1_sel = _GEN ? r_uop_2_op1_sel : ren1_uops_2_op1_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_op2_sel = _GEN ? r_uop_2_op2_sel : ren1_uops_2_op2_sel; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_ldst = _GEN ? r_uop_2_fp_ctrl_ldst : ren1_uops_2_fp_ctrl_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_wen = _GEN ? r_uop_2_fp_ctrl_wen : ren1_uops_2_fp_ctrl_wen; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_ren1 = _GEN ? r_uop_2_fp_ctrl_ren1 : ren1_uops_2_fp_ctrl_ren1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_ren2 = _GEN ? r_uop_2_fp_ctrl_ren2 : ren1_uops_2_fp_ctrl_ren2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_ren3 = _GEN ? r_uop_2_fp_ctrl_ren3 : ren1_uops_2_fp_ctrl_ren3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_swap12 = _GEN ? r_uop_2_fp_ctrl_swap12 : ren1_uops_2_fp_ctrl_swap12; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_swap23 = _GEN ? r_uop_2_fp_ctrl_swap23 : ren1_uops_2_fp_ctrl_swap23; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_typeTagIn = _GEN ? r_uop_2_fp_ctrl_typeTagIn : ren1_uops_2_fp_ctrl_typeTagIn; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_typeTagOut = _GEN ? r_uop_2_fp_ctrl_typeTagOut : ren1_uops_2_fp_ctrl_typeTagOut; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_fromint = _GEN ? r_uop_2_fp_ctrl_fromint : ren1_uops_2_fp_ctrl_fromint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_toint = _GEN ? r_uop_2_fp_ctrl_toint : ren1_uops_2_fp_ctrl_toint; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_fastpipe = _GEN ? r_uop_2_fp_ctrl_fastpipe : ren1_uops_2_fp_ctrl_fastpipe; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_fma = _GEN ? r_uop_2_fp_ctrl_fma : ren1_uops_2_fp_ctrl_fma; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_div = _GEN ? r_uop_2_fp_ctrl_div : ren1_uops_2_fp_ctrl_div; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_sqrt = _GEN ? r_uop_2_fp_ctrl_sqrt : ren1_uops_2_fp_ctrl_sqrt; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_wflags = _GEN ? r_uop_2_fp_ctrl_wflags : ren1_uops_2_fp_ctrl_wflags; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_ctrl_vec = _GEN & r_uop_2_fp_ctrl_vec; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_rob_idx = _GEN ? r_uop_2_rob_idx : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ldq_idx = _GEN ? r_uop_2_ldq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_stq_idx = _GEN ? r_uop_2_stq_idx : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_rxq_idx = _GEN ? r_uop_2_rxq_idx : 2'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_pdst = _GEN ? r_uop_2_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs1 = _GEN ? r_uop_2_prs1 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs2 = _GEN ? r_uop_2_prs2 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs3 = _GEN ? r_uop_2_prs3 : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ppred = _GEN ? r_uop_2_ppred : 5'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs1_busy = _GEN & r_uop_2_prs1_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs2_busy = _GEN & r_uop_2_prs2_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_prs3_busy = _GEN & r_uop_2_prs3_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ppred_busy = _GEN & r_uop_2_ppred_busy; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_stale_pdst = _GEN ? r_uop_2_stale_pdst : 7'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_exception = _GEN ? r_uop_2_exception : ren1_uops_2_exception; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_exc_cause = _GEN ? r_uop_2_exc_cause : ren1_uops_2_exc_cause; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_mem_cmd = _GEN ? r_uop_2_mem_cmd : ren1_uops_2_mem_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_mem_size = _GEN ? r_uop_2_mem_size : ren1_uops_2_mem_size; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_mem_signed = _GEN ? r_uop_2_mem_signed : ren1_uops_2_mem_signed; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_uses_ldq = _GEN ? r_uop_2_uses_ldq : ren1_uops_2_uses_ldq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_uses_stq = _GEN ? r_uop_2_uses_stq : ren1_uops_2_uses_stq; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_is_unique = _GEN ? r_uop_2_is_unique : ren1_uops_2_is_unique; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_flush_on_commit = _GEN ? r_uop_2_flush_on_commit : ren1_uops_2_flush_on_commit; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_csr_cmd = _GEN ? r_uop_2_csr_cmd : ren1_uops_2_csr_cmd; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ldst_is_rs1 = _GEN ? r_uop_2_ldst_is_rs1 : ren1_uops_2_ldst_is_rs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_ldst = _GEN ? r_uop_2_ldst : ren1_uops_2_ldst; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_lrs1 = _GEN ? r_uop_2_lrs1 : ren1_uops_2_lrs1; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_lrs2 = _GEN ? r_uop_2_lrs2 : ren1_uops_2_lrs2; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_lrs3 = _GEN ? r_uop_2_lrs3 : ren1_uops_2_lrs3; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_dst_rtype = _GEN ? r_uop_2_dst_rtype : ren1_uops_2_dst_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_lrs1_rtype = _GEN ? r_uop_2_lrs1_rtype : ren1_uops_2_lrs1_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_lrs2_rtype = _GEN ? r_uop_2_lrs2_rtype : ren1_uops_2_lrs2_rtype; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_frs3_en = _GEN ? r_uop_2_frs3_en : ren1_uops_2_frs3_en; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fcn_dw = _GEN ? r_uop_2_fcn_dw : ren1_uops_2_fcn_dw; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fcn_op = _GEN ? r_uop_2_fcn_op : ren1_uops_2_fcn_op; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_val = _GEN ? r_uop_2_fp_val : ren1_uops_2_fp_val; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_rm = _GEN ? r_uop_2_fp_rm : ren1_uops_2_fp_rm; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_fp_typ = _GEN ? r_uop_2_fp_typ : ren1_uops_2_fp_typ; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_xcpt_pf_if = _GEN ? r_uop_2_xcpt_pf_if : ren1_uops_2_xcpt_pf_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_xcpt_ae_if = _GEN ? r_uop_2_xcpt_ae_if : ren1_uops_2_xcpt_ae_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_xcpt_ma_if = _GEN & r_uop_2_xcpt_ma_if; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_bp_debug_if = _GEN ? r_uop_2_bp_debug_if : ren1_uops_2_bp_debug_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_bp_xcpt_if = _GEN ? r_uop_2_bp_xcpt_if : ren1_uops_2_bp_xcpt_if; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_debug_fsrc = _GEN ? r_uop_2_debug_fsrc : ren1_uops_2_debug_fsrc; // @[rename-stage.scala:70:29, :94:23, :95:24, :97:14, :99:20, :101:30]
assign next_uop_2_debug_tsrc = _GEN ? r_uop_2_debug_tsrc : 3'h0; // @[rename-stage.scala:94:23, :95:24, :97:14, :99:20, :101:30]
wire [15:0] _r_uop_newuop_br_mask_T_5; // @[util.scala:82:35]
wire [15:0] r_uop_newuop_2_br_mask; // @[util.scala:81:26]
wire [15:0] _r_uop_newuop_br_mask_T_4 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _r_uop_newuop_br_mask_T_5 = next_uop_2_br_mask & _r_uop_newuop_br_mask_T_4; // @[util.scala:82:{35,37}]
assign r_uop_newuop_2_br_mask = _r_uop_newuop_br_mask_T_5; // @[util.scala:81:26, :82:35]
wire _ren2_br_tags_3_valid_T = ren2_uops_2_br_type == 4'h1; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_1 = ren2_uops_2_br_type == 4'h2; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_2 = ren2_uops_2_br_type == 4'h3; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_3 = ren2_uops_2_br_type == 4'h4; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_4 = ren2_uops_2_br_type == 4'h5; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_5 = ren2_uops_2_br_type == 4'h6; // @[package.scala:16:47]
wire _ren2_br_tags_3_valid_T_6 = _ren2_br_tags_3_valid_T | _ren2_br_tags_3_valid_T_1; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_3_valid_T_7 = _ren2_br_tags_3_valid_T_6 | _ren2_br_tags_3_valid_T_2; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_3_valid_T_8 = _ren2_br_tags_3_valid_T_7 | _ren2_br_tags_3_valid_T_3; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_3_valid_T_9 = _ren2_br_tags_3_valid_T_8 | _ren2_br_tags_3_valid_T_4; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_3_valid_T_10 = _ren2_br_tags_3_valid_T_9 | _ren2_br_tags_3_valid_T_5; // @[package.scala:16:47, :81:59]
wire _ren2_br_tags_3_valid_T_11 = ~ren2_uops_2_is_sfb; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_3_valid_T_12 = _ren2_br_tags_3_valid_T_10 & _ren2_br_tags_3_valid_T_11; // @[package.scala:81:59]
wire _ren2_br_tags_3_valid_T_13 = ren2_uops_2_br_type == 4'h8; // @[rename-stage.scala:77:29]
wire _ren2_br_tags_3_valid_T_14 = _ren2_br_tags_3_valid_T_12 | _ren2_br_tags_3_valid_T_13; // @[micro-op.scala:119:34, :160:{33,45}]
assign _ren2_br_tags_3_valid_T_15 = io_dis_fire_2_0 & _ren2_br_tags_3_valid_T_14; // @[rename-stage.scala:117:45, :414:7]
assign ren2_br_tags_3_valid = _ren2_br_tags_3_valid_T_15; // @[rename-stage.scala:80:29, :117:45]
wire _imm_ip_T = ren2_uops_0_imm_sel == 3'h6; // @[util.scala:282:23]
wire [19:0] imm_ip = _imm_ip_T ? 20'h0 : ren2_uops_0_imm_packed; // @[util.scala:282:{17,23}]
wire _imm_sign_T = imm_ip[19]; // @[util.scala:282:17, :284:18]
wire imm_sign = _imm_sign_T; // @[util.scala:284:{18,37}]
wire imm_hi_hi_hi = imm_sign; // @[util.scala:284:37, :294:15]
wire _GEN_0 = ren2_uops_0_imm_sel == 3'h3; // @[util.scala:285:27]
wire _imm_i30_20_T; // @[util.scala:285:27]
assign _imm_i30_20_T = _GEN_0; // @[util.scala:285:27]
wire _imm_i19_12_T; // @[util.scala:286:27]
assign _imm_i19_12_T = _GEN_0; // @[util.scala:285:27, :286:27]
wire _imm_i11_T; // @[util.scala:287:27]
assign _imm_i11_T = _GEN_0; // @[util.scala:285:27, :287:27]
wire _imm_i10_5_T; // @[util.scala:289:27]
assign _imm_i10_5_T = _GEN_0; // @[util.scala:285:27, :289:27]
wire _imm_i4_1_T; // @[util.scala:290:27]
assign _imm_i4_1_T = _GEN_0; // @[util.scala:285:27, :290:27]
wire [10:0] _imm_i30_20_T_1 = imm_ip[18:8]; // @[util.scala:282:17, :285:39]
wire [10:0] _imm_i30_20_T_2 = _imm_i30_20_T_1; // @[util.scala:285:{39,46}]
wire [10:0] imm_i30_20 = _imm_i30_20_T ? _imm_i30_20_T_2 : {11{imm_sign}}; // @[util.scala:284:37, :285:{21,27,46}]
wire [10:0] imm_hi_hi_lo = imm_i30_20; // @[util.scala:285:21, :294:15]
wire _GEN_1 = ren2_uops_0_imm_sel == 3'h4; // @[util.scala:286:44]
wire _imm_i19_12_T_1; // @[util.scala:286:44]
assign _imm_i19_12_T_1 = _GEN_1; // @[util.scala:286:44]
wire _imm_i11_T_1; // @[util.scala:288:27]
assign _imm_i11_T_1 = _GEN_1; // @[util.scala:286:44, :288:27]
wire _imm_i19_12_T_2 = _imm_i19_12_T | _imm_i19_12_T_1; // @[util.scala:286:{27,36,44}]
wire [7:0] _imm_i19_12_T_3 = imm_ip[7:0]; // @[util.scala:282:17, :286:56]
wire [7:0] _imm_i19_12_T_4 = _imm_i19_12_T_3; // @[util.scala:286:{56,62}]
wire [7:0] imm_i19_12 = _imm_i19_12_T_2 ? _imm_i19_12_T_4 : {8{imm_sign}}; // @[util.scala:284:37, :286:{21,36,62}]
wire [7:0] imm_hi_lo_hi = imm_i19_12; // @[util.scala:286:21, :294:15]
wire _imm_i11_T_2 = ren2_uops_0_imm_sel == 3'h2; // @[util.scala:288:44]
wire _imm_i11_T_3 = _imm_i11_T_1 | _imm_i11_T_2; // @[util.scala:288:{27,36,44}]
wire _imm_i11_T_4 = imm_ip[8]; // @[util.scala:282:17, :288:56]
wire _imm_i0_T_3 = imm_ip[8]; // @[util.scala:282:17, :288:56, :291:56]
wire _imm_i11_T_5 = _imm_i11_T_4; // @[util.scala:288:{56,60}]
wire _imm_i11_T_6 = _imm_i11_T_3 ? _imm_i11_T_5 : imm_sign; // @[util.scala:284:37, :288:{21,36,60}]
wire imm_i11 = ~_imm_i11_T & _imm_i11_T_6; // @[util.scala:287:{21,27}, :288:21]
wire imm_hi_lo_lo = imm_i11; // @[util.scala:287:21, :294:15]
wire [4:0] _imm_i10_5_T_1 = imm_ip[18:14]; // @[util.scala:282:17, :289:44]
wire [4:0] _imm_i10_5_T_2 = _imm_i10_5_T_1; // @[util.scala:289:{44,52}]
wire [4:0] imm_i10_5 = _imm_i10_5_T ? 5'h0 : _imm_i10_5_T_2; // @[util.scala:289:{21,27,52}]
wire [4:0] imm_lo_hi_hi = imm_i10_5; // @[util.scala:289:21, :294:15]
wire [4:0] _imm_i4_1_T_1 = imm_ip[13:9]; // @[util.scala:282:17, :290:44]
wire [4:0] _imm_i4_1_T_2 = _imm_i4_1_T_1; // @[util.scala:290:{44,51}]
wire [4:0] imm_i4_1 = _imm_i4_1_T ? 5'h0 : _imm_i4_1_T_2; // @[util.scala:290:{21,27,51}]
wire [4:0] imm_lo_hi_lo = imm_i4_1; // @[util.scala:290:21, :294:15]
wire _imm_i0_T = ren2_uops_0_imm_sel == 3'h1; // @[util.scala:291:27]
wire _imm_i0_T_1 = ren2_uops_0_imm_sel == 3'h0; // @[util.scala:291:44]
wire _imm_i0_T_2 = _imm_i0_T | _imm_i0_T_1; // @[util.scala:291:{27,36,44}]
wire _imm_i0_T_4 = _imm_i0_T_3; // @[util.scala:291:{56,60}]
wire imm_i0 = _imm_i0_T_2 & _imm_i0_T_4; // @[util.scala:291:{21,36,60}]
wire imm_lo_lo = imm_i0; // @[util.scala:291:21, :294:15]
wire [9:0] imm_lo_hi = {imm_lo_hi_hi, imm_lo_hi_lo}; // @[util.scala:294:15]
wire [10:0] imm_lo = {imm_lo_hi, imm_lo_lo}; // @[util.scala:294:15]
wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[util.scala:294:15]
wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[util.scala:294:15]
wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[util.scala:294:15]
wire [31:0] imm = {imm_hi, imm_lo}; // @[util.scala:294:15]
wire [27:0] imm_hi_1 = imm[31:4]; // @[util.scala:294:15]
wire [4:0] imm_lo_1 = imm[4:0]; // @[util.scala:294:15]
wire _short_imm_T = imm_hi_1 == 28'h0; // @[rename-stage.scala:426:22, :428:28]
wire [27:0] _short_imm_T_1 = ~imm_hi_1; // @[rename-stage.scala:426:22, :428:39]
wire _short_imm_T_2 = _short_imm_T_1 == 28'h0; // @[rename-stage.scala:428:{28,39,47}]
wire short_imm = _short_imm_T | _short_imm_T_2; // @[rename-stage.scala:428:{28,36,47}]
wire _io_ren_stalls_0_T = ~_freelist_io_alloc_pregs_0_valid; // @[rename-stage.scala:417:24, :437:52]
assign _io_ren_stalls_0_T_1 = ren2_uops_0_imm_rename & _io_ren_stalls_0_T; // @[rename-stage.scala:77:29, :437:{49,52}]
assign io_ren_stalls_0_0 = _io_ren_stalls_0_T_1; // @[rename-stage.scala:414:7, :437:49]
assign io_ren2_uops_0_inst = io_ren2_uops_0_newuop_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_debug_inst = io_ren2_uops_0_newuop_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_is_rvc = io_ren2_uops_0_newuop_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_0_debug_pc = io_ren2_uops_0_newuop_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_0_iq_type_0 = io_ren2_uops_0_newuop_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_0_iq_type_1 = io_ren2_uops_0_newuop_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_0_iq_type_2 = io_ren2_uops_0_newuop_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_0_iq_type_3 = io_ren2_uops_0_newuop_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_0 = io_ren2_uops_0_newuop_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_1 = io_ren2_uops_0_newuop_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_2 = io_ren2_uops_0_newuop_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_3 = io_ren2_uops_0_newuop_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_4 = io_ren2_uops_0_newuop_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_5 = io_ren2_uops_0_newuop_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_6 = io_ren2_uops_0_newuop_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_7 = io_ren2_uops_0_newuop_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_8 = io_ren2_uops_0_newuop_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_0_fu_code_9 = io_ren2_uops_0_newuop_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_issued = io_ren2_uops_0_newuop_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_issued_partial_agen = io_ren2_uops_0_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_issued_partial_dgen = io_ren2_uops_0_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_p1_speculative_child = io_ren2_uops_0_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_p2_speculative_child = io_ren2_uops_0_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_p1_bypass_hint = io_ren2_uops_0_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_p2_bypass_hint = io_ren2_uops_0_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_iw_p3_bypass_hint = io_ren2_uops_0_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_0_dis_col_sel = io_ren2_uops_0_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_0_newuop_br_mask_T_1; // @[util.scala:82:35]
assign io_ren2_uops_0_br_mask = io_ren2_uops_0_newuop_br_mask; // @[util.scala:81:26]
assign io_ren2_uops_0_br_tag = io_ren2_uops_0_newuop_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_0_br_type = io_ren2_uops_0_newuop_br_type; // @[util.scala:81:26]
assign io_ren2_uops_0_is_sfb = io_ren2_uops_0_newuop_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_0_is_fence = io_ren2_uops_0_newuop_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_0_is_fencei = io_ren2_uops_0_newuop_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_0_is_sfence = io_ren2_uops_0_newuop_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_0_is_amo = io_ren2_uops_0_newuop_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_0_is_eret = io_ren2_uops_0_newuop_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_0_is_sys_pc2epc = io_ren2_uops_0_newuop_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_0_is_rocc = io_ren2_uops_0_newuop_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_0_is_mov = io_ren2_uops_0_newuop_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_0_ftq_idx = io_ren2_uops_0_newuop_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_edge_inst = io_ren2_uops_0_newuop_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_0_pc_lob = io_ren2_uops_0_newuop_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_0_taken = io_ren2_uops_0_newuop_taken; // @[util.scala:81:26]
assign io_ren2_uops_0_imm_rename = io_ren2_uops_0_newuop_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_0_imm_sel_0 = io_ren2_uops_0_newuop_imm_sel; // @[util.scala:81:26]
assign io_ren2_uops_0_imm_packed = io_ren2_uops_0_newuop_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_0_op1_sel = io_ren2_uops_0_newuop_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_0_op2_sel = io_ren2_uops_0_newuop_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_ldst = io_ren2_uops_0_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_wen = io_ren2_uops_0_newuop_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_ren1 = io_ren2_uops_0_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_ren2 = io_ren2_uops_0_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_ren3 = io_ren2_uops_0_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_swap12 = io_ren2_uops_0_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_swap23 = io_ren2_uops_0_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_typeTagIn = io_ren2_uops_0_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_typeTagOut = io_ren2_uops_0_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_fromint = io_ren2_uops_0_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_toint = io_ren2_uops_0_newuop_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_fastpipe = io_ren2_uops_0_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_fma = io_ren2_uops_0_newuop_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_div = io_ren2_uops_0_newuop_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_sqrt = io_ren2_uops_0_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_wflags = io_ren2_uops_0_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_ctrl_vec = io_ren2_uops_0_newuop_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_0_rob_idx = io_ren2_uops_0_newuop_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_ldq_idx = io_ren2_uops_0_newuop_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_stq_idx = io_ren2_uops_0_newuop_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_rxq_idx = io_ren2_uops_0_newuop_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_0_pdst = io_ren2_uops_0_newuop_pdst; // @[util.scala:81:26]
assign io_ren2_uops_0_prs1 = io_ren2_uops_0_newuop_prs1; // @[util.scala:81:26]
assign io_ren2_uops_0_prs2 = io_ren2_uops_0_newuop_prs2; // @[util.scala:81:26]
assign io_ren2_uops_0_prs3 = io_ren2_uops_0_newuop_prs3; // @[util.scala:81:26]
assign io_ren2_uops_0_ppred = io_ren2_uops_0_newuop_ppred; // @[util.scala:81:26]
assign io_ren2_uops_0_prs1_busy = io_ren2_uops_0_newuop_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_prs2_busy = io_ren2_uops_0_newuop_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_prs3_busy = io_ren2_uops_0_newuop_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_ppred_busy = io_ren2_uops_0_newuop_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_0_stale_pdst = io_ren2_uops_0_newuop_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_0_exception = io_ren2_uops_0_newuop_exception; // @[util.scala:81:26]
assign io_ren2_uops_0_exc_cause = io_ren2_uops_0_newuop_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_0_mem_cmd = io_ren2_uops_0_newuop_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_0_mem_size = io_ren2_uops_0_newuop_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_0_mem_signed = io_ren2_uops_0_newuop_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_0_uses_ldq = io_ren2_uops_0_newuop_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_0_uses_stq = io_ren2_uops_0_newuop_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_0_is_unique = io_ren2_uops_0_newuop_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_0_flush_on_commit = io_ren2_uops_0_newuop_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_0_csr_cmd = io_ren2_uops_0_newuop_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_0_ldst_is_rs1 = io_ren2_uops_0_newuop_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_0_ldst = io_ren2_uops_0_newuop_ldst; // @[util.scala:81:26]
assign io_ren2_uops_0_lrs1 = io_ren2_uops_0_newuop_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_0_lrs2 = io_ren2_uops_0_newuop_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_0_lrs3 = io_ren2_uops_0_newuop_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_0_dst_rtype = io_ren2_uops_0_newuop_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_lrs1_rtype = io_ren2_uops_0_newuop_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_lrs2_rtype = io_ren2_uops_0_newuop_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_0_frs3_en = io_ren2_uops_0_newuop_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_0_fcn_dw = io_ren2_uops_0_newuop_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_0_fcn_op = io_ren2_uops_0_newuop_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_val = io_ren2_uops_0_newuop_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_rm = io_ren2_uops_0_newuop_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_0_fp_typ = io_ren2_uops_0_newuop_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_0_xcpt_pf_if = io_ren2_uops_0_newuop_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_0_xcpt_ae_if = io_ren2_uops_0_newuop_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_0_xcpt_ma_if = io_ren2_uops_0_newuop_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_0_bp_debug_if = io_ren2_uops_0_newuop_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_0_bp_xcpt_if = io_ren2_uops_0_newuop_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_0_debug_fsrc = io_ren2_uops_0_newuop_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_0_debug_tsrc = io_ren2_uops_0_newuop_debug_tsrc; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_0_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _io_ren2_uops_0_newuop_br_mask_T_1 = ren2_uops_0_br_mask & _io_ren2_uops_0_newuop_br_mask_T; // @[util.scala:82:{35,37}]
assign io_ren2_uops_0_newuop_br_mask = _io_ren2_uops_0_newuop_br_mask_T_1; // @[util.scala:81:26, :82:35]
assign io_ren2_uops_0_pimm_0 = ren2_uops_0_imm_rename ? _freelist_io_alloc_pregs_0_bits : io_ren2_uops_0_newuop_pimm; // @[util.scala:81:26]
wire _imm_ip_T_1 = ren2_uops_1_imm_sel == 3'h6; // @[util.scala:282:23]
wire [19:0] imm_ip_1 = _imm_ip_T_1 ? 20'h0 : ren2_uops_1_imm_packed; // @[util.scala:282:{17,23}]
wire _imm_sign_T_1 = imm_ip_1[19]; // @[util.scala:282:17, :284:18]
wire imm_sign_1 = _imm_sign_T_1; // @[util.scala:284:{18,37}]
wire imm_hi_hi_hi_1 = imm_sign_1; // @[util.scala:284:37, :294:15]
wire _GEN_2 = ren2_uops_1_imm_sel == 3'h3; // @[util.scala:285:27]
wire _imm_i30_20_T_3; // @[util.scala:285:27]
assign _imm_i30_20_T_3 = _GEN_2; // @[util.scala:285:27]
wire _imm_i19_12_T_5; // @[util.scala:286:27]
assign _imm_i19_12_T_5 = _GEN_2; // @[util.scala:285:27, :286:27]
wire _imm_i11_T_7; // @[util.scala:287:27]
assign _imm_i11_T_7 = _GEN_2; // @[util.scala:285:27, :287:27]
wire _imm_i10_5_T_3; // @[util.scala:289:27]
assign _imm_i10_5_T_3 = _GEN_2; // @[util.scala:285:27, :289:27]
wire _imm_i4_1_T_3; // @[util.scala:290:27]
assign _imm_i4_1_T_3 = _GEN_2; // @[util.scala:285:27, :290:27]
wire [10:0] _imm_i30_20_T_4 = imm_ip_1[18:8]; // @[util.scala:282:17, :285:39]
wire [10:0] _imm_i30_20_T_5 = _imm_i30_20_T_4; // @[util.scala:285:{39,46}]
wire [10:0] imm_i30_20_1 = _imm_i30_20_T_3 ? _imm_i30_20_T_5 : {11{imm_sign_1}}; // @[util.scala:284:37, :285:{21,27,46}]
wire [10:0] imm_hi_hi_lo_1 = imm_i30_20_1; // @[util.scala:285:21, :294:15]
wire _GEN_3 = ren2_uops_1_imm_sel == 3'h4; // @[util.scala:286:44]
wire _imm_i19_12_T_6; // @[util.scala:286:44]
assign _imm_i19_12_T_6 = _GEN_3; // @[util.scala:286:44]
wire _imm_i11_T_8; // @[util.scala:288:27]
assign _imm_i11_T_8 = _GEN_3; // @[util.scala:286:44, :288:27]
wire _imm_i19_12_T_7 = _imm_i19_12_T_5 | _imm_i19_12_T_6; // @[util.scala:286:{27,36,44}]
wire [7:0] _imm_i19_12_T_8 = imm_ip_1[7:0]; // @[util.scala:282:17, :286:56]
wire [7:0] _imm_i19_12_T_9 = _imm_i19_12_T_8; // @[util.scala:286:{56,62}]
wire [7:0] imm_i19_12_1 = _imm_i19_12_T_7 ? _imm_i19_12_T_9 : {8{imm_sign_1}}; // @[util.scala:284:37, :286:{21,36,62}]
wire [7:0] imm_hi_lo_hi_1 = imm_i19_12_1; // @[util.scala:286:21, :294:15]
wire _imm_i11_T_9 = ren2_uops_1_imm_sel == 3'h2; // @[util.scala:288:44]
wire _imm_i11_T_10 = _imm_i11_T_8 | _imm_i11_T_9; // @[util.scala:288:{27,36,44}]
wire _imm_i11_T_11 = imm_ip_1[8]; // @[util.scala:282:17, :288:56]
wire _imm_i0_T_8 = imm_ip_1[8]; // @[util.scala:282:17, :288:56, :291:56]
wire _imm_i11_T_12 = _imm_i11_T_11; // @[util.scala:288:{56,60}]
wire _imm_i11_T_13 = _imm_i11_T_10 ? _imm_i11_T_12 : imm_sign_1; // @[util.scala:284:37, :288:{21,36,60}]
wire imm_i11_1 = ~_imm_i11_T_7 & _imm_i11_T_13; // @[util.scala:287:{21,27}, :288:21]
wire imm_hi_lo_lo_1 = imm_i11_1; // @[util.scala:287:21, :294:15]
wire [4:0] _imm_i10_5_T_4 = imm_ip_1[18:14]; // @[util.scala:282:17, :289:44]
wire [4:0] _imm_i10_5_T_5 = _imm_i10_5_T_4; // @[util.scala:289:{44,52}]
wire [4:0] imm_i10_5_1 = _imm_i10_5_T_3 ? 5'h0 : _imm_i10_5_T_5; // @[util.scala:289:{21,27,52}]
wire [4:0] imm_lo_hi_hi_1 = imm_i10_5_1; // @[util.scala:289:21, :294:15]
wire [4:0] _imm_i4_1_T_4 = imm_ip_1[13:9]; // @[util.scala:282:17, :290:44]
wire [4:0] _imm_i4_1_T_5 = _imm_i4_1_T_4; // @[util.scala:290:{44,51}]
wire [4:0] imm_i4_1_1 = _imm_i4_1_T_3 ? 5'h0 : _imm_i4_1_T_5; // @[util.scala:290:{21,27,51}]
wire [4:0] imm_lo_hi_lo_1 = imm_i4_1_1; // @[util.scala:290:21, :294:15]
wire _imm_i0_T_5 = ren2_uops_1_imm_sel == 3'h1; // @[util.scala:291:27]
wire _imm_i0_T_6 = ren2_uops_1_imm_sel == 3'h0; // @[util.scala:291:44]
wire _imm_i0_T_7 = _imm_i0_T_5 | _imm_i0_T_6; // @[util.scala:291:{27,36,44}]
wire _imm_i0_T_9 = _imm_i0_T_8; // @[util.scala:291:{56,60}]
wire imm_i0_1 = _imm_i0_T_7 & _imm_i0_T_9; // @[util.scala:291:{21,36,60}]
wire imm_lo_lo_1 = imm_i0_1; // @[util.scala:291:21, :294:15]
wire [9:0] imm_lo_hi_1 = {imm_lo_hi_hi_1, imm_lo_hi_lo_1}; // @[util.scala:294:15]
wire [10:0] imm_lo_2 = {imm_lo_hi_1, imm_lo_lo_1}; // @[util.scala:294:15]
wire [8:0] imm_hi_lo_1 = {imm_hi_lo_hi_1, imm_hi_lo_lo_1}; // @[util.scala:294:15]
wire [11:0] imm_hi_hi_1 = {imm_hi_hi_hi_1, imm_hi_hi_lo_1}; // @[util.scala:294:15]
wire [20:0] imm_hi_2 = {imm_hi_hi_1, imm_hi_lo_1}; // @[util.scala:294:15]
wire [31:0] imm_1 = {imm_hi_2, imm_lo_2}; // @[util.scala:294:15]
wire [27:0] imm_hi_3 = imm_1[31:4]; // @[util.scala:294:15]
wire [4:0] imm_lo_3 = imm_1[4:0]; // @[util.scala:294:15]
wire _short_imm_T_3 = imm_hi_3 == 28'h0; // @[rename-stage.scala:426:22, :428:28]
wire [27:0] _short_imm_T_4 = ~imm_hi_3; // @[rename-stage.scala:426:22, :428:39]
wire _short_imm_T_5 = _short_imm_T_4 == 28'h0; // @[rename-stage.scala:428:{28,39,47}]
wire short_imm_1 = _short_imm_T_3 | _short_imm_T_5; // @[rename-stage.scala:428:{28,36,47}]
wire _io_ren_stalls_1_T = ~_freelist_io_alloc_pregs_1_valid; // @[rename-stage.scala:417:24, :437:52]
assign _io_ren_stalls_1_T_1 = ren2_uops_1_imm_rename & _io_ren_stalls_1_T; // @[rename-stage.scala:77:29, :437:{49,52}]
assign io_ren_stalls_1_0 = _io_ren_stalls_1_T_1; // @[rename-stage.scala:414:7, :437:49]
assign io_ren2_uops_1_inst = io_ren2_uops_1_newuop_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_debug_inst = io_ren2_uops_1_newuop_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_is_rvc = io_ren2_uops_1_newuop_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_1_debug_pc = io_ren2_uops_1_newuop_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_1_iq_type_0 = io_ren2_uops_1_newuop_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_1_iq_type_1 = io_ren2_uops_1_newuop_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_1_iq_type_2 = io_ren2_uops_1_newuop_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_1_iq_type_3 = io_ren2_uops_1_newuop_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_0 = io_ren2_uops_1_newuop_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_1 = io_ren2_uops_1_newuop_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_2 = io_ren2_uops_1_newuop_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_3 = io_ren2_uops_1_newuop_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_4 = io_ren2_uops_1_newuop_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_5 = io_ren2_uops_1_newuop_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_6 = io_ren2_uops_1_newuop_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_7 = io_ren2_uops_1_newuop_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_8 = io_ren2_uops_1_newuop_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_1_fu_code_9 = io_ren2_uops_1_newuop_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_issued = io_ren2_uops_1_newuop_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_issued_partial_agen = io_ren2_uops_1_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_issued_partial_dgen = io_ren2_uops_1_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_p1_speculative_child = io_ren2_uops_1_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_p2_speculative_child = io_ren2_uops_1_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_p1_bypass_hint = io_ren2_uops_1_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_p2_bypass_hint = io_ren2_uops_1_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_iw_p3_bypass_hint = io_ren2_uops_1_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_1_dis_col_sel = io_ren2_uops_1_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_1_newuop_br_mask_T_1; // @[util.scala:82:35]
assign io_ren2_uops_1_br_mask = io_ren2_uops_1_newuop_br_mask; // @[util.scala:81:26]
assign io_ren2_uops_1_br_tag = io_ren2_uops_1_newuop_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_1_br_type = io_ren2_uops_1_newuop_br_type; // @[util.scala:81:26]
assign io_ren2_uops_1_is_sfb = io_ren2_uops_1_newuop_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_1_is_fence = io_ren2_uops_1_newuop_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_1_is_fencei = io_ren2_uops_1_newuop_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_1_is_sfence = io_ren2_uops_1_newuop_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_1_is_amo = io_ren2_uops_1_newuop_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_1_is_eret = io_ren2_uops_1_newuop_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_1_is_sys_pc2epc = io_ren2_uops_1_newuop_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_1_is_rocc = io_ren2_uops_1_newuop_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_1_is_mov = io_ren2_uops_1_newuop_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_1_ftq_idx = io_ren2_uops_1_newuop_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_edge_inst = io_ren2_uops_1_newuop_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_1_pc_lob = io_ren2_uops_1_newuop_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_1_taken = io_ren2_uops_1_newuop_taken; // @[util.scala:81:26]
assign io_ren2_uops_1_imm_rename = io_ren2_uops_1_newuop_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_1_imm_sel_0 = io_ren2_uops_1_newuop_imm_sel; // @[util.scala:81:26]
assign io_ren2_uops_1_imm_packed = io_ren2_uops_1_newuop_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_1_op1_sel = io_ren2_uops_1_newuop_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_1_op2_sel = io_ren2_uops_1_newuop_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_ldst = io_ren2_uops_1_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_wen = io_ren2_uops_1_newuop_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_ren1 = io_ren2_uops_1_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_ren2 = io_ren2_uops_1_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_ren3 = io_ren2_uops_1_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_swap12 = io_ren2_uops_1_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_swap23 = io_ren2_uops_1_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_typeTagIn = io_ren2_uops_1_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_typeTagOut = io_ren2_uops_1_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_fromint = io_ren2_uops_1_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_toint = io_ren2_uops_1_newuop_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_fastpipe = io_ren2_uops_1_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_fma = io_ren2_uops_1_newuop_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_div = io_ren2_uops_1_newuop_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_sqrt = io_ren2_uops_1_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_wflags = io_ren2_uops_1_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_ctrl_vec = io_ren2_uops_1_newuop_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_1_rob_idx = io_ren2_uops_1_newuop_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_ldq_idx = io_ren2_uops_1_newuop_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_stq_idx = io_ren2_uops_1_newuop_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_rxq_idx = io_ren2_uops_1_newuop_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_1_pdst = io_ren2_uops_1_newuop_pdst; // @[util.scala:81:26]
assign io_ren2_uops_1_prs1 = io_ren2_uops_1_newuop_prs1; // @[util.scala:81:26]
assign io_ren2_uops_1_prs2 = io_ren2_uops_1_newuop_prs2; // @[util.scala:81:26]
assign io_ren2_uops_1_prs3 = io_ren2_uops_1_newuop_prs3; // @[util.scala:81:26]
assign io_ren2_uops_1_ppred = io_ren2_uops_1_newuop_ppred; // @[util.scala:81:26]
assign io_ren2_uops_1_prs1_busy = io_ren2_uops_1_newuop_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_prs2_busy = io_ren2_uops_1_newuop_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_prs3_busy = io_ren2_uops_1_newuop_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_ppred_busy = io_ren2_uops_1_newuop_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_1_stale_pdst = io_ren2_uops_1_newuop_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_1_exception = io_ren2_uops_1_newuop_exception; // @[util.scala:81:26]
assign io_ren2_uops_1_exc_cause = io_ren2_uops_1_newuop_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_1_mem_cmd = io_ren2_uops_1_newuop_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_1_mem_size = io_ren2_uops_1_newuop_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_1_mem_signed = io_ren2_uops_1_newuop_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_1_uses_ldq = io_ren2_uops_1_newuop_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_1_uses_stq = io_ren2_uops_1_newuop_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_1_is_unique = io_ren2_uops_1_newuop_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_1_flush_on_commit = io_ren2_uops_1_newuop_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_1_csr_cmd = io_ren2_uops_1_newuop_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_1_ldst_is_rs1 = io_ren2_uops_1_newuop_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_1_ldst = io_ren2_uops_1_newuop_ldst; // @[util.scala:81:26]
assign io_ren2_uops_1_lrs1 = io_ren2_uops_1_newuop_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_1_lrs2 = io_ren2_uops_1_newuop_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_1_lrs3 = io_ren2_uops_1_newuop_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_1_dst_rtype = io_ren2_uops_1_newuop_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_lrs1_rtype = io_ren2_uops_1_newuop_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_lrs2_rtype = io_ren2_uops_1_newuop_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_1_frs3_en = io_ren2_uops_1_newuop_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_1_fcn_dw = io_ren2_uops_1_newuop_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_1_fcn_op = io_ren2_uops_1_newuop_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_val = io_ren2_uops_1_newuop_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_rm = io_ren2_uops_1_newuop_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_1_fp_typ = io_ren2_uops_1_newuop_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_1_xcpt_pf_if = io_ren2_uops_1_newuop_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_1_xcpt_ae_if = io_ren2_uops_1_newuop_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_1_xcpt_ma_if = io_ren2_uops_1_newuop_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_1_bp_debug_if = io_ren2_uops_1_newuop_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_1_bp_xcpt_if = io_ren2_uops_1_newuop_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_1_debug_fsrc = io_ren2_uops_1_newuop_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_1_debug_tsrc = io_ren2_uops_1_newuop_debug_tsrc; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_1_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _io_ren2_uops_1_newuop_br_mask_T_1 = ren2_uops_1_br_mask & _io_ren2_uops_1_newuop_br_mask_T; // @[util.scala:82:{35,37}]
assign io_ren2_uops_1_newuop_br_mask = _io_ren2_uops_1_newuop_br_mask_T_1; // @[util.scala:81:26, :82:35]
assign io_ren2_uops_1_pimm_0 = ren2_uops_1_imm_rename ? _freelist_io_alloc_pregs_1_bits : io_ren2_uops_1_newuop_pimm; // @[util.scala:81:26]
wire _imm_ip_T_2 = ren2_uops_2_imm_sel == 3'h6; // @[util.scala:282:23]
wire [19:0] imm_ip_2 = _imm_ip_T_2 ? 20'h0 : ren2_uops_2_imm_packed; // @[util.scala:282:{17,23}]
wire _imm_sign_T_2 = imm_ip_2[19]; // @[util.scala:282:17, :284:18]
wire imm_sign_2 = _imm_sign_T_2; // @[util.scala:284:{18,37}]
wire imm_hi_hi_hi_2 = imm_sign_2; // @[util.scala:284:37, :294:15]
wire _GEN_4 = ren2_uops_2_imm_sel == 3'h3; // @[util.scala:285:27]
wire _imm_i30_20_T_6; // @[util.scala:285:27]
assign _imm_i30_20_T_6 = _GEN_4; // @[util.scala:285:27]
wire _imm_i19_12_T_10; // @[util.scala:286:27]
assign _imm_i19_12_T_10 = _GEN_4; // @[util.scala:285:27, :286:27]
wire _imm_i11_T_14; // @[util.scala:287:27]
assign _imm_i11_T_14 = _GEN_4; // @[util.scala:285:27, :287:27]
wire _imm_i10_5_T_6; // @[util.scala:289:27]
assign _imm_i10_5_T_6 = _GEN_4; // @[util.scala:285:27, :289:27]
wire _imm_i4_1_T_6; // @[util.scala:290:27]
assign _imm_i4_1_T_6 = _GEN_4; // @[util.scala:285:27, :290:27]
wire [10:0] _imm_i30_20_T_7 = imm_ip_2[18:8]; // @[util.scala:282:17, :285:39]
wire [10:0] _imm_i30_20_T_8 = _imm_i30_20_T_7; // @[util.scala:285:{39,46}]
wire [10:0] imm_i30_20_2 = _imm_i30_20_T_6 ? _imm_i30_20_T_8 : {11{imm_sign_2}}; // @[util.scala:284:37, :285:{21,27,46}]
wire [10:0] imm_hi_hi_lo_2 = imm_i30_20_2; // @[util.scala:285:21, :294:15]
wire _GEN_5 = ren2_uops_2_imm_sel == 3'h4; // @[util.scala:286:44]
wire _imm_i19_12_T_11; // @[util.scala:286:44]
assign _imm_i19_12_T_11 = _GEN_5; // @[util.scala:286:44]
wire _imm_i11_T_15; // @[util.scala:288:27]
assign _imm_i11_T_15 = _GEN_5; // @[util.scala:286:44, :288:27]
wire _imm_i19_12_T_12 = _imm_i19_12_T_10 | _imm_i19_12_T_11; // @[util.scala:286:{27,36,44}]
wire [7:0] _imm_i19_12_T_13 = imm_ip_2[7:0]; // @[util.scala:282:17, :286:56]
wire [7:0] _imm_i19_12_T_14 = _imm_i19_12_T_13; // @[util.scala:286:{56,62}]
wire [7:0] imm_i19_12_2 = _imm_i19_12_T_12 ? _imm_i19_12_T_14 : {8{imm_sign_2}}; // @[util.scala:284:37, :286:{21,36,62}]
wire [7:0] imm_hi_lo_hi_2 = imm_i19_12_2; // @[util.scala:286:21, :294:15]
wire _imm_i11_T_16 = ren2_uops_2_imm_sel == 3'h2; // @[util.scala:288:44]
wire _imm_i11_T_17 = _imm_i11_T_15 | _imm_i11_T_16; // @[util.scala:288:{27,36,44}]
wire _imm_i11_T_18 = imm_ip_2[8]; // @[util.scala:282:17, :288:56]
wire _imm_i0_T_13 = imm_ip_2[8]; // @[util.scala:282:17, :288:56, :291:56]
wire _imm_i11_T_19 = _imm_i11_T_18; // @[util.scala:288:{56,60}]
wire _imm_i11_T_20 = _imm_i11_T_17 ? _imm_i11_T_19 : imm_sign_2; // @[util.scala:284:37, :288:{21,36,60}]
wire imm_i11_2 = ~_imm_i11_T_14 & _imm_i11_T_20; // @[util.scala:287:{21,27}, :288:21]
wire imm_hi_lo_lo_2 = imm_i11_2; // @[util.scala:287:21, :294:15]
wire [4:0] _imm_i10_5_T_7 = imm_ip_2[18:14]; // @[util.scala:282:17, :289:44]
wire [4:0] _imm_i10_5_T_8 = _imm_i10_5_T_7; // @[util.scala:289:{44,52}]
wire [4:0] imm_i10_5_2 = _imm_i10_5_T_6 ? 5'h0 : _imm_i10_5_T_8; // @[util.scala:289:{21,27,52}]
wire [4:0] imm_lo_hi_hi_2 = imm_i10_5_2; // @[util.scala:289:21, :294:15]
wire [4:0] _imm_i4_1_T_7 = imm_ip_2[13:9]; // @[util.scala:282:17, :290:44]
wire [4:0] _imm_i4_1_T_8 = _imm_i4_1_T_7; // @[util.scala:290:{44,51}]
wire [4:0] imm_i4_1_2 = _imm_i4_1_T_6 ? 5'h0 : _imm_i4_1_T_8; // @[util.scala:290:{21,27,51}]
wire [4:0] imm_lo_hi_lo_2 = imm_i4_1_2; // @[util.scala:290:21, :294:15]
wire _imm_i0_T_10 = ren2_uops_2_imm_sel == 3'h1; // @[util.scala:291:27]
wire _imm_i0_T_11 = ren2_uops_2_imm_sel == 3'h0; // @[util.scala:291:44]
wire _imm_i0_T_12 = _imm_i0_T_10 | _imm_i0_T_11; // @[util.scala:291:{27,36,44}]
wire _imm_i0_T_14 = _imm_i0_T_13; // @[util.scala:291:{56,60}]
wire imm_i0_2 = _imm_i0_T_12 & _imm_i0_T_14; // @[util.scala:291:{21,36,60}]
wire imm_lo_lo_2 = imm_i0_2; // @[util.scala:291:21, :294:15]
wire [9:0] imm_lo_hi_2 = {imm_lo_hi_hi_2, imm_lo_hi_lo_2}; // @[util.scala:294:15]
wire [10:0] imm_lo_4 = {imm_lo_hi_2, imm_lo_lo_2}; // @[util.scala:294:15]
wire [8:0] imm_hi_lo_2 = {imm_hi_lo_hi_2, imm_hi_lo_lo_2}; // @[util.scala:294:15]
wire [11:0] imm_hi_hi_2 = {imm_hi_hi_hi_2, imm_hi_hi_lo_2}; // @[util.scala:294:15]
wire [20:0] imm_hi_4 = {imm_hi_hi_2, imm_hi_lo_2}; // @[util.scala:294:15]
wire [31:0] imm_2 = {imm_hi_4, imm_lo_4}; // @[util.scala:294:15]
wire [27:0] imm_hi_5 = imm_2[31:4]; // @[util.scala:294:15]
wire [4:0] imm_lo_5 = imm_2[4:0]; // @[util.scala:294:15]
wire _short_imm_T_6 = imm_hi_5 == 28'h0; // @[rename-stage.scala:426:22, :428:28]
wire [27:0] _short_imm_T_7 = ~imm_hi_5; // @[rename-stage.scala:426:22, :428:39]
wire _short_imm_T_8 = _short_imm_T_7 == 28'h0; // @[rename-stage.scala:428:{28,39,47}]
wire short_imm_2 = _short_imm_T_6 | _short_imm_T_8; // @[rename-stage.scala:428:{28,36,47}]
wire _io_ren_stalls_2_T = ~_freelist_io_alloc_pregs_2_valid; // @[rename-stage.scala:417:24, :437:52]
assign _io_ren_stalls_2_T_1 = ren2_uops_2_imm_rename & _io_ren_stalls_2_T; // @[rename-stage.scala:77:29, :437:{49,52}]
assign io_ren_stalls_2_0 = _io_ren_stalls_2_T_1; // @[rename-stage.scala:414:7, :437:49]
assign io_ren2_uops_2_inst = io_ren2_uops_2_newuop_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_debug_inst = io_ren2_uops_2_newuop_debug_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_is_rvc = io_ren2_uops_2_newuop_is_rvc; // @[util.scala:81:26]
assign io_ren2_uops_2_debug_pc = io_ren2_uops_2_newuop_debug_pc; // @[util.scala:81:26]
assign io_ren2_uops_2_iq_type_0 = io_ren2_uops_2_newuop_iq_type_0; // @[util.scala:81:26]
assign io_ren2_uops_2_iq_type_1 = io_ren2_uops_2_newuop_iq_type_1; // @[util.scala:81:26]
assign io_ren2_uops_2_iq_type_2 = io_ren2_uops_2_newuop_iq_type_2; // @[util.scala:81:26]
assign io_ren2_uops_2_iq_type_3 = io_ren2_uops_2_newuop_iq_type_3; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_0 = io_ren2_uops_2_newuop_fu_code_0; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_1 = io_ren2_uops_2_newuop_fu_code_1; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_2 = io_ren2_uops_2_newuop_fu_code_2; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_3 = io_ren2_uops_2_newuop_fu_code_3; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_4 = io_ren2_uops_2_newuop_fu_code_4; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_5 = io_ren2_uops_2_newuop_fu_code_5; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_6 = io_ren2_uops_2_newuop_fu_code_6; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_7 = io_ren2_uops_2_newuop_fu_code_7; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_8 = io_ren2_uops_2_newuop_fu_code_8; // @[util.scala:81:26]
assign io_ren2_uops_2_fu_code_9 = io_ren2_uops_2_newuop_fu_code_9; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_issued = io_ren2_uops_2_newuop_iw_issued; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_issued_partial_agen = io_ren2_uops_2_newuop_iw_issued_partial_agen; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_issued_partial_dgen = io_ren2_uops_2_newuop_iw_issued_partial_dgen; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_p1_speculative_child = io_ren2_uops_2_newuop_iw_p1_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_p2_speculative_child = io_ren2_uops_2_newuop_iw_p2_speculative_child; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_p1_bypass_hint = io_ren2_uops_2_newuop_iw_p1_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_p2_bypass_hint = io_ren2_uops_2_newuop_iw_p2_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_iw_p3_bypass_hint = io_ren2_uops_2_newuop_iw_p3_bypass_hint; // @[util.scala:81:26]
assign io_ren2_uops_2_dis_col_sel = io_ren2_uops_2_newuop_dis_col_sel; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_2_newuop_br_mask_T_1; // @[util.scala:82:35]
assign io_ren2_uops_2_br_mask = io_ren2_uops_2_newuop_br_mask; // @[util.scala:81:26]
assign io_ren2_uops_2_br_tag = io_ren2_uops_2_newuop_br_tag; // @[util.scala:81:26]
assign io_ren2_uops_2_br_type = io_ren2_uops_2_newuop_br_type; // @[util.scala:81:26]
assign io_ren2_uops_2_is_sfb = io_ren2_uops_2_newuop_is_sfb; // @[util.scala:81:26]
assign io_ren2_uops_2_is_fence = io_ren2_uops_2_newuop_is_fence; // @[util.scala:81:26]
assign io_ren2_uops_2_is_fencei = io_ren2_uops_2_newuop_is_fencei; // @[util.scala:81:26]
assign io_ren2_uops_2_is_sfence = io_ren2_uops_2_newuop_is_sfence; // @[util.scala:81:26]
assign io_ren2_uops_2_is_amo = io_ren2_uops_2_newuop_is_amo; // @[util.scala:81:26]
assign io_ren2_uops_2_is_eret = io_ren2_uops_2_newuop_is_eret; // @[util.scala:81:26]
assign io_ren2_uops_2_is_sys_pc2epc = io_ren2_uops_2_newuop_is_sys_pc2epc; // @[util.scala:81:26]
assign io_ren2_uops_2_is_rocc = io_ren2_uops_2_newuop_is_rocc; // @[util.scala:81:26]
assign io_ren2_uops_2_is_mov = io_ren2_uops_2_newuop_is_mov; // @[util.scala:81:26]
assign io_ren2_uops_2_ftq_idx = io_ren2_uops_2_newuop_ftq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_edge_inst = io_ren2_uops_2_newuop_edge_inst; // @[util.scala:81:26]
assign io_ren2_uops_2_pc_lob = io_ren2_uops_2_newuop_pc_lob; // @[util.scala:81:26]
assign io_ren2_uops_2_taken = io_ren2_uops_2_newuop_taken; // @[util.scala:81:26]
assign io_ren2_uops_2_imm_rename = io_ren2_uops_2_newuop_imm_rename; // @[util.scala:81:26]
assign io_ren2_uops_2_imm_sel_0 = io_ren2_uops_2_newuop_imm_sel; // @[util.scala:81:26]
assign io_ren2_uops_2_imm_packed = io_ren2_uops_2_newuop_imm_packed; // @[util.scala:81:26]
assign io_ren2_uops_2_op1_sel = io_ren2_uops_2_newuop_op1_sel; // @[util.scala:81:26]
assign io_ren2_uops_2_op2_sel = io_ren2_uops_2_newuop_op2_sel; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_ldst = io_ren2_uops_2_newuop_fp_ctrl_ldst; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_wen = io_ren2_uops_2_newuop_fp_ctrl_wen; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_ren1 = io_ren2_uops_2_newuop_fp_ctrl_ren1; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_ren2 = io_ren2_uops_2_newuop_fp_ctrl_ren2; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_ren3 = io_ren2_uops_2_newuop_fp_ctrl_ren3; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_swap12 = io_ren2_uops_2_newuop_fp_ctrl_swap12; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_swap23 = io_ren2_uops_2_newuop_fp_ctrl_swap23; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_typeTagIn = io_ren2_uops_2_newuop_fp_ctrl_typeTagIn; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_typeTagOut = io_ren2_uops_2_newuop_fp_ctrl_typeTagOut; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_fromint = io_ren2_uops_2_newuop_fp_ctrl_fromint; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_toint = io_ren2_uops_2_newuop_fp_ctrl_toint; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_fastpipe = io_ren2_uops_2_newuop_fp_ctrl_fastpipe; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_fma = io_ren2_uops_2_newuop_fp_ctrl_fma; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_div = io_ren2_uops_2_newuop_fp_ctrl_div; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_sqrt = io_ren2_uops_2_newuop_fp_ctrl_sqrt; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_wflags = io_ren2_uops_2_newuop_fp_ctrl_wflags; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_ctrl_vec = io_ren2_uops_2_newuop_fp_ctrl_vec; // @[util.scala:81:26]
assign io_ren2_uops_2_rob_idx = io_ren2_uops_2_newuop_rob_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_ldq_idx = io_ren2_uops_2_newuop_ldq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_stq_idx = io_ren2_uops_2_newuop_stq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_rxq_idx = io_ren2_uops_2_newuop_rxq_idx; // @[util.scala:81:26]
assign io_ren2_uops_2_pdst = io_ren2_uops_2_newuop_pdst; // @[util.scala:81:26]
assign io_ren2_uops_2_prs1 = io_ren2_uops_2_newuop_prs1; // @[util.scala:81:26]
assign io_ren2_uops_2_prs2 = io_ren2_uops_2_newuop_prs2; // @[util.scala:81:26]
assign io_ren2_uops_2_prs3 = io_ren2_uops_2_newuop_prs3; // @[util.scala:81:26]
assign io_ren2_uops_2_ppred = io_ren2_uops_2_newuop_ppred; // @[util.scala:81:26]
assign io_ren2_uops_2_prs1_busy = io_ren2_uops_2_newuop_prs1_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_prs2_busy = io_ren2_uops_2_newuop_prs2_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_prs3_busy = io_ren2_uops_2_newuop_prs3_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_ppred_busy = io_ren2_uops_2_newuop_ppred_busy; // @[util.scala:81:26]
assign io_ren2_uops_2_stale_pdst = io_ren2_uops_2_newuop_stale_pdst; // @[util.scala:81:26]
assign io_ren2_uops_2_exception = io_ren2_uops_2_newuop_exception; // @[util.scala:81:26]
assign io_ren2_uops_2_exc_cause = io_ren2_uops_2_newuop_exc_cause; // @[util.scala:81:26]
assign io_ren2_uops_2_mem_cmd = io_ren2_uops_2_newuop_mem_cmd; // @[util.scala:81:26]
assign io_ren2_uops_2_mem_size = io_ren2_uops_2_newuop_mem_size; // @[util.scala:81:26]
assign io_ren2_uops_2_mem_signed = io_ren2_uops_2_newuop_mem_signed; // @[util.scala:81:26]
assign io_ren2_uops_2_uses_ldq = io_ren2_uops_2_newuop_uses_ldq; // @[util.scala:81:26]
assign io_ren2_uops_2_uses_stq = io_ren2_uops_2_newuop_uses_stq; // @[util.scala:81:26]
assign io_ren2_uops_2_is_unique = io_ren2_uops_2_newuop_is_unique; // @[util.scala:81:26]
assign io_ren2_uops_2_flush_on_commit = io_ren2_uops_2_newuop_flush_on_commit; // @[util.scala:81:26]
assign io_ren2_uops_2_csr_cmd = io_ren2_uops_2_newuop_csr_cmd; // @[util.scala:81:26]
assign io_ren2_uops_2_ldst_is_rs1 = io_ren2_uops_2_newuop_ldst_is_rs1; // @[util.scala:81:26]
assign io_ren2_uops_2_ldst = io_ren2_uops_2_newuop_ldst; // @[util.scala:81:26]
assign io_ren2_uops_2_lrs1 = io_ren2_uops_2_newuop_lrs1; // @[util.scala:81:26]
assign io_ren2_uops_2_lrs2 = io_ren2_uops_2_newuop_lrs2; // @[util.scala:81:26]
assign io_ren2_uops_2_lrs3 = io_ren2_uops_2_newuop_lrs3; // @[util.scala:81:26]
assign io_ren2_uops_2_dst_rtype = io_ren2_uops_2_newuop_dst_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_lrs1_rtype = io_ren2_uops_2_newuop_lrs1_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_lrs2_rtype = io_ren2_uops_2_newuop_lrs2_rtype; // @[util.scala:81:26]
assign io_ren2_uops_2_frs3_en = io_ren2_uops_2_newuop_frs3_en; // @[util.scala:81:26]
assign io_ren2_uops_2_fcn_dw = io_ren2_uops_2_newuop_fcn_dw; // @[util.scala:81:26]
assign io_ren2_uops_2_fcn_op = io_ren2_uops_2_newuop_fcn_op; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_val = io_ren2_uops_2_newuop_fp_val; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_rm = io_ren2_uops_2_newuop_fp_rm; // @[util.scala:81:26]
assign io_ren2_uops_2_fp_typ = io_ren2_uops_2_newuop_fp_typ; // @[util.scala:81:26]
assign io_ren2_uops_2_xcpt_pf_if = io_ren2_uops_2_newuop_xcpt_pf_if; // @[util.scala:81:26]
assign io_ren2_uops_2_xcpt_ae_if = io_ren2_uops_2_newuop_xcpt_ae_if; // @[util.scala:81:26]
assign io_ren2_uops_2_xcpt_ma_if = io_ren2_uops_2_newuop_xcpt_ma_if; // @[util.scala:81:26]
assign io_ren2_uops_2_bp_debug_if = io_ren2_uops_2_newuop_bp_debug_if; // @[util.scala:81:26]
assign io_ren2_uops_2_bp_xcpt_if = io_ren2_uops_2_newuop_bp_xcpt_if; // @[util.scala:81:26]
assign io_ren2_uops_2_debug_fsrc = io_ren2_uops_2_newuop_debug_fsrc; // @[util.scala:81:26]
assign io_ren2_uops_2_debug_tsrc = io_ren2_uops_2_newuop_debug_tsrc; // @[util.scala:81:26]
wire [15:0] _io_ren2_uops_2_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:82:37]
assign _io_ren2_uops_2_newuop_br_mask_T_1 = ren2_uops_2_br_mask & _io_ren2_uops_2_newuop_br_mask_T; // @[util.scala:82:{35,37}]
assign io_ren2_uops_2_newuop_br_mask = _io_ren2_uops_2_newuop_br_mask_T_1; // @[util.scala:81:26, :82:35]
assign io_ren2_uops_2_pimm_0 = ren2_uops_2_imm_rename ? _freelist_io_alloc_pregs_2_bits : io_ren2_uops_2_newuop_pimm; // @[util.scala:81:26]
reg REG; // @[rename-stage.scala:458:19] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_77( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_333 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_23( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tilelink.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLMasterToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))
a.io.protocol <> io.tilelink.a
io.tilelink.b <> b.io.protocol
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
e.io.protocol <> io.tilelink.e
io.flits.a <> a.io.flit
b.io.flit <> io.flits.b
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
io.flits.e <> e.io.flit
}
class TLMasterACDToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
a.io.protocol <> io.tilelink.a
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
io.flits.a <> a.io.flit
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
}
class TLMasterBEToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))
io.tilelink.b <> b.io.protocol
e.io.protocol <> io.tilelink.e
b.io.flit <> io.flits.b
io.flits.e <> e.io.flit
}
class TLSlaveToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val b = Decoupled(new IngressFlit(flitWidth))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
io.tilelink.a <> a.io.protocol
b.io.protocol <> io.tilelink.b
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
io.tilelink.e <> e.io.protocol
a.io.flit <> io.flits.a
io.flits.b <> b.io.flit
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
e.io.flit <> io.flits.e
}
class TLSlaveACDToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))
io.tilelink.a <> a.io.protocol
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
a.io.flit <> io.flits.a
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
}
class TLSlaveBEToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val b = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
b.io.protocol <> io.tilelink.b
io.tilelink.e <> e.io.protocol
io.flits.b <> b.io.flit
e.io.flit <> io.flits.e
}
class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {
val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })
val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })
}
trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {
def edgesIn: Seq[TLEdge]
def edgesOut: Seq[TLEdge]
def edgeInNodes: Seq[Int]
def edgeOutNodes: Seq[Int]
require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)
def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))
def genBundle = new TLBundle(wideBundle)
def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee
def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)
}
object TLConnect {
def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {
l.valid := r.valid
r.ready := l.ready
l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll
}
}
// BEGIN: TileLinkProtocolParams
case class TileLinkABCDEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]
) extends TileLinkProtocolParams {
// END: TileLinkProtocolParams
val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten
val nVirtualNetworks = 5
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A
(if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D
(if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master = Module(new TLMasterToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 3 + edgesIn.size * 2 + egressOffset,
minPayloadWidth
))
nif_master.io.tilelink := DontCare
nif_master.io.tilelink.a.valid := false.B
nif_master.io.tilelink.c.valid := false.B
nif_master.io.tilelink.e.valid := false.B
TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)
TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)
TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
nif_master.io.flits.b <> egresses(i * 2 + 0).flit
nif_master.io.flits.d <> egresses(i * 2 + 1).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave = Module(new TLSlaveToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 2 + egressOffset,
minPayloadWidth
))
nif_slave.io.tilelink := DontCare
nif_slave.io.tilelink.b.valid := false.B
nif_slave.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)
TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)
TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)
TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)
}
ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit
nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit
nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit
}
} }
}
}
case class TileLinkACDProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val nVirtualNetworks = 3
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A
(if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_acd = Module(new TLMasterACDToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 2 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_acd.io.tilelink := DontCare
nif_master_acd.io.tilelink.a.valid := false.B
nif_master_acd.io.tilelink.c.valid := false.B
nif_master_acd.io.tilelink.e.valid := false.B
TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)
}
ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a
ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c
nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_acd = Module(new TLSlaveACDToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_acd.io.tilelink := DontCare
nif_slave_acd.io.tilelink.b.valid := false.B
nif_slave_acd.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)
TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)
}
ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d
nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit
nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit
}
}}
}
}
case class TileLinkBEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val nVirtualNetworks = 2
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_be = Module(new TLMasterBEToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 1 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_be.io.tilelink := DontCare
nif_master_be.io.tilelink.a.valid := false.B
nif_master_be.io.tilelink.c.valid := false.B
nif_master_be.io.tilelink.e.valid := false.B
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)
TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e
nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_be = Module(new TLSlaveBEToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_be.io.tilelink := DontCare
nif_slave_be.io.tilelink.b.valid := false.B
nif_slave_be.io.tilelink.d.valid := false.B
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)
TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)
}
ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b
nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit
}
}}
}
}
abstract class TLNoCLike(implicit p: Parameters) extends LazyModule {
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
// TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers
port.managers map { manager => manager.v1copy(fifoId = None) }
}
)
}
)
}
abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {
val edgesIn: Seq[TLEdge]
val edgesOut: Seq[TLEdge]
val nodeMapping: DiplomaticNetworkNodeMapping
val nocName: String
lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))
lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))
lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)
lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)
def printNodeMappings() {
println(s"Constellation: TLNoC $nocName inwards mapping:")
for ((n, i) <- inNames zip edgeInNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
println(s"Constellation: TLNoC $nocName outwards mapping:")
for ((n, i) <- outNames zip edgeOutNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
}
}
trait TLNoCParams
// Instantiates a private TLNoC. Replaces the TLXbar
// BEGIN: TLNoCParams
case class SimpleTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
nocParams: NoCParams = NoCParams(),
) extends TLNoCParams
class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
// END: TLNoCParams
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),
Seq(protocolParams),
inlineNoC = inlineNoC
)))
noc.io.protocol(0) match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
case class SplitACDxBETLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
acdNoCParams: NoCParams = NoCParams(),
beNoCParams: NoCParams = NoCParams(),
beDivision: Int = 2
) extends TLNoCParams
class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val acdProtocolParams = TileLinkACDProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val beProtocolParams = TileLinkBEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC),
Seq(acdProtocolParams),
inlineNoC = inlineNoC
)))
val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC),
Seq(beProtocolParams),
widthDivision = params.beDivision,
inlineNoC = inlineNoC
)))
acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
}}
be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.b <> r.b
l.e <> r.e
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.b <> r.b
l.e <> r.e
}
}}
}
}
case class GlobalTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping
) extends TLNoCParams
// Maps this interconnect onto a global NoC
class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike {
lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
printNodeMappings()
val io_global = IO(Flipped(protocolParams.genIO()))
io_global match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
| module TLSlaveACDToNoC_4( // @[Tilelink.scala:161:7]
input clock, // @[Tilelink.scala:161:7]
input reset, // @[Tilelink.scala:161:7]
input io_tilelink_a_ready, // @[Tilelink.scala:168:14]
output io_tilelink_a_valid, // @[Tilelink.scala:168:14]
output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:168:14]
output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:168:14]
output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:168:14]
output [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:168:14]
output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:168:14]
output [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:168:14]
output [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:168:14]
output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:168:14]
input io_tilelink_c_ready, // @[Tilelink.scala:168:14]
output io_tilelink_c_valid, // @[Tilelink.scala:168:14]
output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:168:14]
output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:168:14]
output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:168:14]
output [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:168:14]
output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:168:14]
output [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:168:14]
output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:168:14]
output io_tilelink_d_ready, // @[Tilelink.scala:168:14]
input io_tilelink_d_valid, // @[Tilelink.scala:168:14]
input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:168:14]
input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:168:14]
input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:168:14]
input [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:168:14]
input [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:168:14]
input io_tilelink_d_bits_denied, // @[Tilelink.scala:168:14]
input [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:168:14]
input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:168:14]
output io_flits_a_ready, // @[Tilelink.scala:168:14]
input io_flits_a_valid, // @[Tilelink.scala:168:14]
input io_flits_a_bits_head, // @[Tilelink.scala:168:14]
input io_flits_a_bits_tail, // @[Tilelink.scala:168:14]
input [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:168:14]
output io_flits_c_ready, // @[Tilelink.scala:168:14]
input io_flits_c_valid, // @[Tilelink.scala:168:14]
input io_flits_c_bits_head, // @[Tilelink.scala:168:14]
input io_flits_c_bits_tail, // @[Tilelink.scala:168:14]
input [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:168:14]
input io_flits_d_ready, // @[Tilelink.scala:168:14]
output io_flits_d_valid, // @[Tilelink.scala:168:14]
output io_flits_d_bits_head, // @[Tilelink.scala:168:14]
output io_flits_d_bits_tail, // @[Tilelink.scala:168:14]
output [144:0] io_flits_d_bits_payload, // @[Tilelink.scala:168:14]
output [3:0] io_flits_d_bits_egress_id // @[Tilelink.scala:168:14]
);
wire [128:0] _d_io_flit_bits_payload; // @[Tilelink.scala:179:17]
TLAFromNoC a ( // @[Tilelink.scala:177:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload)
); // @[Tilelink.scala:177:17]
TLCFromNoC_1 c ( // @[Tilelink.scala:178:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_c_ready),
.io_protocol_valid (io_tilelink_c_valid),
.io_protocol_bits_opcode (io_tilelink_c_bits_opcode),
.io_protocol_bits_param (io_tilelink_c_bits_param),
.io_protocol_bits_size (io_tilelink_c_bits_size),
.io_protocol_bits_source (io_tilelink_c_bits_source),
.io_protocol_bits_address (io_tilelink_c_bits_address),
.io_protocol_bits_data (io_tilelink_c_bits_data),
.io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail),
.io_flit_bits_payload (io_flits_c_bits_payload[128:0]) // @[Tilelink.scala:185:14]
); // @[Tilelink.scala:178:17]
TLDToNoC_4 d ( // @[Tilelink.scala:179:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (_d_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_d_bits_egress_id)
); // @[Tilelink.scala:179:17]
assign io_flits_d_bits_payload = {16'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:161:7, :179:17, :186:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_180( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Breakpoint.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
def svaluePos : Int = 2
val mvalue = UInt(mvalueBits.W)
val mselect = Bool()
val pad2 = UInt((mselectPos - svalueBits - 2).W)
val svalue = UInt(svalueBits.W)
val pad1 = UInt(1.W)
val sselect = Bool()
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(vaddrBits.W)
val textra = new TExtra
def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
}
class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
val debug_if = Output(Bool())
val debug_ld = Output(Bool())
val debug_st = Output(Bool())
val bpwatch = Output(Vec(n, new BPWatch(1)))
})
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
io.debug_if := false.B
io.debug_ld := false.B
io.debug_st := false.B
(io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>
val en = bp.control.enabled(io.status)
val cx = bp.contextMatch(io.mcontext, io.scontext)
val r = en && bp.control.r && bp.addressMatch(io.ea) && cx
val w = en && bp.control.w && bp.addressMatch(io.ea) && cx
val x = en && bp.control.x && bp.addressMatch(io.pc) && cx
val end = !bp.control.chain
val action = bp.control.action
bpw.action := action
bpw.valid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }
(end || r, end || w, end || x)
}
}
| module BreakpointUnit( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [31:0] io_status_isa, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_bp_0_control_dmode, // @[Breakpoint.scala:80:14]
input io_bp_0_control_action, // @[Breakpoint.scala:80:14]
input [1:0] io_bp_0_control_tmatch, // @[Breakpoint.scala:80:14]
input io_bp_0_control_x, // @[Breakpoint.scala:80:14]
input io_bp_0_control_w, // @[Breakpoint.scala:80:14]
input io_bp_0_control_r, // @[Breakpoint.scala:80:14]
input [31:0] io_bp_0_address, // @[Breakpoint.scala:80:14]
input [22:0] io_bp_0_textra_pad2, // @[Breakpoint.scala:80:14]
input io_bp_0_textra_pad1, // @[Breakpoint.scala:80:14]
input [31:0] io_pc, // @[Breakpoint.scala:80:14]
input [31:0] io_ea, // @[Breakpoint.scala:80:14]
output io_xcpt_if, // @[Breakpoint.scala:80:14]
output io_xcpt_ld, // @[Breakpoint.scala:80:14]
output io_xcpt_st, // @[Breakpoint.scala:80:14]
output io_debug_if, // @[Breakpoint.scala:80:14]
output io_debug_ld, // @[Breakpoint.scala:80:14]
output io_debug_st, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_rvalid_0, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_wvalid_0, // @[Breakpoint.scala:80:14]
output io_bpwatch_0_ivalid_0 // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [31:0] io_status_isa_0 = io_status_isa; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_dmode_0 = io_bp_0_control_dmode; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_action_0 = io_bp_0_control_action; // @[Breakpoint.scala:79:7]
wire [1:0] io_bp_0_control_tmatch_0 = io_bp_0_control_tmatch; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_x_0 = io_bp_0_control_x; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_w_0 = io_bp_0_control_w; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_r_0 = io_bp_0_control_r; // @[Breakpoint.scala:79:7]
wire [31:0] io_bp_0_address_0 = io_bp_0_address; // @[Breakpoint.scala:79:7]
wire [22:0] io_bp_0_textra_pad2_0 = io_bp_0_textra_pad2; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_pad1_0 = io_bp_0_textra_pad1; // @[Breakpoint.scala:79:7]
wire [31:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [31:0] io_ea_0 = io_ea; // @[Breakpoint.scala:79:7]
wire [1:0] en_hi = 2'h2; // @[Breakpoint.scala:30:56]
wire [3:0] _en_T_1 = 4'h8; // @[Breakpoint.scala:30:56]
wire [3:0] _en_T_2 = 4'h1; // @[Breakpoint.scala:30:68]
wire io_bp_0_control_m = 1'h1; // @[Breakpoint.scala:79:7]
wire _en_T_3 = 1'h1; // @[Breakpoint.scala:30:68]
wire cx = 1'h1; // @[Breakpoint.scala:55:126]
wire end_0 = 1'h1; // @[Breakpoint.scala:109:15]
wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[Breakpoint.scala:79:7, :80:14]
wire [3:0] io_bp_0_control_ttype = 4'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_uxl = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_bp_0_control_zero = 2'h0; // @[Breakpoint.scala:79:7]
wire [1:0] en_lo = 2'h0; // @[Breakpoint.scala:30:56]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_bp_0_control_reserved = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_sd = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_tsr = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_tw = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_tvm = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_mxr = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sum = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_mprv = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_spp = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_spie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_chain = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_h = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_s = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_control_u = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_mselect = 1'h0; // @[Breakpoint.scala:79:7]
wire io_bp_0_textra_sselect = 1'h0; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv = 2'h3; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_prv = 2'h3; // @[Breakpoint.scala:79:7, :80:14]
wire _io_debug_ld_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:84]
wire _io_debug_st_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :119:84]
wire _io_debug_if_T = io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :120:84]
wire r; // @[Breakpoint.scala:106:58]
wire w; // @[Breakpoint.scala:107:58]
wire x; // @[Breakpoint.scala:108:58]
wire io_bpwatch_0_valid_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7]
wire io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7]
wire [2:0] io_bpwatch_0_action; // @[Breakpoint.scala:79:7]
wire io_xcpt_if_0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld_0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st_0; // @[Breakpoint.scala:79:7]
wire io_debug_if_0; // @[Breakpoint.scala:79:7]
wire io_debug_ld_0; // @[Breakpoint.scala:79:7]
wire io_debug_st_0; // @[Breakpoint.scala:79:7]
wire _en_T = ~io_status_debug_0; // @[Breakpoint.scala:30:35, :79:7]
wire en = _en_T; // @[Breakpoint.scala:30:{35,50}]
wire _r_T = en & io_bp_0_control_r_0; // @[Breakpoint.scala:30:50, :79:7, :106:16]
wire _r_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _w_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _x_T_1 = io_bp_0_control_tmatch_0[1]; // @[Breakpoint.scala:68:23, :79:7]
wire _GEN = io_ea_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7]
wire _r_T_2; // @[Breakpoint.scala:65:8]
assign _r_T_2 = _GEN; // @[Breakpoint.scala:65:8]
wire _w_T_2; // @[Breakpoint.scala:65:8]
assign _w_T_2 = _GEN; // @[Breakpoint.scala:65:8]
wire _r_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _r_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _r_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _w_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _w_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _w_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _x_T_3 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:65:36, :79:7]
wire _x_T_6 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _x_T_16 = io_bp_0_control_tmatch_0[0]; // @[Breakpoint.scala:59:56, :65:36, :79:7]
wire _r_T_4 = _r_T_2 ^ _r_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [31:0] _r_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7]
wire _r_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_7 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_17 = io_bp_0_address_0[0]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_8 = _r_T_6 & _r_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _r_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_9 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_19 = io_bp_0_address_0[1]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_10 = _r_T_8 & _r_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _r_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _w_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_11 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _x_T_21 = io_bp_0_address_0[2]; // @[Breakpoint.scala:59:83, :79:7]
wire _r_T_12 = _r_T_10 & _r_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] r_lo = {_r_T_8, _r_T_6}; // @[package.scala:45:27]
wire [1:0] r_hi = {_r_T_12, _r_T_10}; // @[package.scala:45:27]
wire [3:0] _r_T_13 = {r_hi, r_lo}; // @[package.scala:45:27]
wire [31:0] _r_T_14 = {_r_T_5[31:4], _r_T_5[3:0] | _r_T_13}; // @[package.scala:45:27]
wire [31:0] _r_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _r_T_18 = _r_T_16 & _r_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _r_T_20 = _r_T_18 & _r_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _r_T_22 = _r_T_20 & _r_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] r_lo_1 = {_r_T_18, _r_T_16}; // @[package.scala:45:27]
wire [1:0] r_hi_1 = {_r_T_22, _r_T_20}; // @[package.scala:45:27]
wire [3:0] _r_T_23 = {r_hi_1, r_lo_1}; // @[package.scala:45:27]
wire [31:0] _r_T_24 = {_r_T_15[31:4], _r_T_15[3:0] | _r_T_23}; // @[package.scala:45:27]
wire _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _r_T_26 = _r_T_1 ? _r_T_4 : _r_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _r_T_27 = _r_T & _r_T_26; // @[Breakpoint.scala:68:8, :106:{16,32}]
assign r = _r_T_27; // @[Breakpoint.scala:106:{32,58}]
assign io_bpwatch_0_rvalid_0_0 = r; // @[Breakpoint.scala:79:7, :106:58]
wire _w_T = en & io_bp_0_control_w_0; // @[Breakpoint.scala:30:50, :79:7, :107:16]
wire _w_T_4 = _w_T_2 ^ _w_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [31:0] _w_T_5 = ~io_ea_0; // @[Breakpoint.scala:62:6, :79:7]
wire _w_T_8 = _w_T_6 & _w_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _w_T_10 = _w_T_8 & _w_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _w_T_12 = _w_T_10 & _w_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] w_lo = {_w_T_8, _w_T_6}; // @[package.scala:45:27]
wire [1:0] w_hi = {_w_T_12, _w_T_10}; // @[package.scala:45:27]
wire [3:0] _w_T_13 = {w_hi, w_lo}; // @[package.scala:45:27]
wire [31:0] _w_T_14 = {_w_T_5[31:4], _w_T_5[3:0] | _w_T_13}; // @[package.scala:45:27]
wire [31:0] _w_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _w_T_18 = _w_T_16 & _w_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _w_T_20 = _w_T_18 & _w_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _w_T_22 = _w_T_20 & _w_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] w_lo_1 = {_w_T_18, _w_T_16}; // @[package.scala:45:27]
wire [1:0] w_hi_1 = {_w_T_22, _w_T_20}; // @[package.scala:45:27]
wire [3:0] _w_T_23 = {w_hi_1, w_lo_1}; // @[package.scala:45:27]
wire [31:0] _w_T_24 = {_w_T_15[31:4], _w_T_15[3:0] | _w_T_23}; // @[package.scala:45:27]
wire _w_T_25 = _w_T_14 == _w_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _w_T_26 = _w_T_1 ? _w_T_4 : _w_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _w_T_27 = _w_T & _w_T_26; // @[Breakpoint.scala:68:8, :107:{16,32}]
assign w = _w_T_27; // @[Breakpoint.scala:107:{32,58}]
assign io_bpwatch_0_wvalid_0_0 = w; // @[Breakpoint.scala:79:7, :107:58]
wire _x_T = en & io_bp_0_control_x_0; // @[Breakpoint.scala:30:50, :79:7, :108:16]
wire _x_T_2 = io_pc_0 >= io_bp_0_address_0; // @[Breakpoint.scala:65:8, :79:7]
wire _x_T_4 = _x_T_2 ^ _x_T_3; // @[Breakpoint.scala:65:{8,20,36}]
wire [31:0] _x_T_5 = ~io_pc_0; // @[Breakpoint.scala:62:6, :79:7]
wire _x_T_8 = _x_T_6 & _x_T_7; // @[Breakpoint.scala:59:{56,73,83}]
wire _x_T_10 = _x_T_8 & _x_T_9; // @[Breakpoint.scala:59:{73,83}]
wire _x_T_12 = _x_T_10 & _x_T_11; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] x_lo = {_x_T_8, _x_T_6}; // @[package.scala:45:27]
wire [1:0] x_hi = {_x_T_12, _x_T_10}; // @[package.scala:45:27]
wire [3:0] _x_T_13 = {x_hi, x_lo}; // @[package.scala:45:27]
wire [31:0] _x_T_14 = {_x_T_5[31:4], _x_T_5[3:0] | _x_T_13}; // @[package.scala:45:27]
wire [31:0] _x_T_15 = ~io_bp_0_address_0; // @[Breakpoint.scala:62:24, :79:7]
wire _x_T_18 = _x_T_16 & _x_T_17; // @[Breakpoint.scala:59:{56,73,83}]
wire _x_T_20 = _x_T_18 & _x_T_19; // @[Breakpoint.scala:59:{73,83}]
wire _x_T_22 = _x_T_20 & _x_T_21; // @[Breakpoint.scala:59:{73,83}]
wire [1:0] x_lo_1 = {_x_T_18, _x_T_16}; // @[package.scala:45:27]
wire [1:0] x_hi_1 = {_x_T_22, _x_T_20}; // @[package.scala:45:27]
wire [3:0] _x_T_23 = {x_hi_1, x_lo_1}; // @[package.scala:45:27]
wire [31:0] _x_T_24 = {_x_T_15[31:4], _x_T_15[3:0] | _x_T_23}; // @[package.scala:45:27]
wire _x_T_25 = _x_T_14 == _x_T_24; // @[Breakpoint.scala:62:{9,19,33}]
wire _x_T_26 = _x_T_1 ? _x_T_4 : _x_T_25; // @[Breakpoint.scala:62:19, :65:20, :68:{8,23}]
wire _x_T_27 = _x_T & _x_T_26; // @[Breakpoint.scala:68:8, :108:{16,32}]
assign x = _x_T_27; // @[Breakpoint.scala:108:{32,58}]
assign io_bpwatch_0_ivalid_0_0 = x; // @[Breakpoint.scala:79:7, :108:58]
assign io_bpwatch_0_action = {2'h0, io_bp_0_control_action_0}; // @[Breakpoint.scala:79:7, :112:16]
wire _io_xcpt_ld_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51]
assign io_xcpt_ld_0 = r & _io_xcpt_ld_T; // @[Breakpoint.scala:79:7, :97:14, :106:58, :118:{27,40,51}]
assign io_debug_ld_0 = r & _io_debug_ld_T; // @[Breakpoint.scala:79:7, :100:15, :106:58, :118:{27,73,84}]
wire _io_xcpt_st_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :119:51]
assign io_xcpt_st_0 = w & _io_xcpt_st_T; // @[Breakpoint.scala:79:7, :98:14, :107:58, :119:{27,40,51}]
assign io_debug_st_0 = w & _io_debug_st_T; // @[Breakpoint.scala:79:7, :101:15, :107:58, :119:{27,73,84}]
wire _io_xcpt_if_T = ~io_bp_0_control_action_0; // @[Breakpoint.scala:79:7, :118:51, :120:51]
assign io_xcpt_if_0 = x & _io_xcpt_if_T; // @[Breakpoint.scala:79:7, :96:14, :108:58, :120:{27,40,51}]
assign io_debug_if_0 = x & _io_debug_if_T; // @[Breakpoint.scala:79:7, :99:15, :108:58, :120:{27,73,84}]
assign io_bpwatch_0_valid_0 = x | w | r; // @[Breakpoint.scala:79:7, :106:58, :107:58, :108:58, :118:27, :119:{27,107}, :120:{27,107}]
assign io_xcpt_if = io_xcpt_if_0; // @[Breakpoint.scala:79:7]
assign io_xcpt_ld = io_xcpt_ld_0; // @[Breakpoint.scala:79:7]
assign io_xcpt_st = io_xcpt_st_0; // @[Breakpoint.scala:79:7]
assign io_debug_if = io_debug_if_0; // @[Breakpoint.scala:79:7]
assign io_debug_ld = io_debug_ld_0; // @[Breakpoint.scala:79:7]
assign io_debug_st = io_debug_st_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_rvalid_0 = io_bpwatch_0_rvalid_0_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_wvalid_0 = io_bpwatch_0_wvalid_0_0; // @[Breakpoint.scala:79:7]
assign io_bpwatch_0_ivalid_0 = io_bpwatch_0_ivalid_0_0; // @[Breakpoint.scala:79:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module test_router_18ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [4:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [21:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [21:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_14 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready),
.auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid),
.auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head),
.auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload),
.auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File HellaQueue.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
val io = IO(new QueueIO(data, entries))
require(entries > 1)
val do_flow = Wire(Bool())
val do_enq = io.enq.fire && !do_flow
val do_deq = io.deq.fire && !do_flow
val maybe_full = RegInit(false.B)
val enq_ptr = Counter(do_enq, entries)._1
val (deq_ptr, deq_done) = Counter(do_deq, entries)
when (do_enq =/= do_deq) { maybe_full := do_enq }
val ptr_match = enq_ptr === deq_ptr
val empty = ptr_match && !maybe_full
val full = ptr_match && maybe_full
val atLeastTwo = full || enq_ptr - deq_ptr >= 2.U
do_flow := empty && io.deq.ready
val ram = SyncReadMem(entries, data)
when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
// BUG! does not hold the output of the SRAM when !ready
// ... However, HellaQueue is correct due to the pipe stage
val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
val raddr = Mux(io.deq.valid, Mux(deq_done, 0.U, deq_ptr + 1.U), deq_ptr)
val ram_out_valid = RegNext(ren)
io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
io.enq.ready := !full
io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren))
// Count was never correctly set. To keep the same behavior across chisel3 upgrade, we are explicitly setting it to DontCare
io.count := DontCare
}
class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module {
val io = IO(new QueueIO(data, entries))
val fq = Module(new HellaFlowQueue(entries)(data))
fq.io.enq <> io.enq
io.deq <> Queue(fq.io.deq, 1, pipe = true)
io.count := fq.io.count
}
object HellaQueue {
def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = {
val q = Module((new HellaQueue(entries)) { enq.bits })
q.io.enq.valid := enq.valid // not using <> so that override is allowed
q.io.enq.bits := enq.bits
enq.ready := q.io.enq.ready
q.io.deq
}
}
| module HellaQueue_4( // @[HellaQueue.scala:44:7]
input clock, // @[HellaQueue.scala:44:7]
input reset, // @[HellaQueue.scala:44:7]
output io_enq_ready, // @[HellaQueue.scala:45:14]
input io_enq_valid, // @[HellaQueue.scala:45:14]
input [1:0] io_enq_bits, // @[HellaQueue.scala:45:14]
input io_deq_ready, // @[HellaQueue.scala:45:14]
output io_deq_valid, // @[HellaQueue.scala:45:14]
output [1:0] io_deq_bits // @[HellaQueue.scala:45:14]
);
wire _io_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _fq_io_deq_valid; // @[HellaQueue.scala:47:18]
wire [1:0] _fq_io_deq_bits; // @[HellaQueue.scala:47:18]
wire io_enq_valid_0 = io_enq_valid; // @[HellaQueue.scala:44:7]
wire [1:0] io_enq_bits_0 = io_enq_bits; // @[HellaQueue.scala:44:7]
wire io_deq_ready_0 = io_deq_ready; // @[HellaQueue.scala:44:7]
wire [6:0] io_count = 7'h0; // @[HellaQueue.scala:44:7, :45:14, :47:18]
wire io_enq_ready_0; // @[HellaQueue.scala:44:7]
wire io_deq_valid_0; // @[HellaQueue.scala:44:7]
wire [1:0] io_deq_bits_0; // @[HellaQueue.scala:44:7]
HellaFlowQueue_4 fq ( // @[HellaQueue.scala:47:18]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[HellaQueue.scala:44:7]
.io_enq_bits (io_enq_bits_0), // @[HellaQueue.scala:44:7]
.io_deq_ready (_io_deq_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_deq_valid (_fq_io_deq_valid),
.io_deq_bits (_fq_io_deq_bits)
); // @[HellaQueue.scala:47:18]
Queue1_UInt2 io_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_io_deq_q_io_enq_ready),
.io_enq_valid (_fq_io_deq_valid), // @[HellaQueue.scala:47:18]
.io_enq_bits (_fq_io_deq_bits), // @[HellaQueue.scala:47:18]
.io_deq_ready (io_deq_ready_0), // @[HellaQueue.scala:44:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits (io_deq_bits_0)
); // @[Decoupled.scala:362:21]
assign io_enq_ready = io_enq_ready_0; // @[HellaQueue.scala:44:7]
assign io_deq_valid = io_deq_valid_0; // @[HellaQueue.scala:44:7]
assign io_deq_bits = io_deq_bits_0; // @[HellaQueue.scala:44:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_11( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_11 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Replacement.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
def way: UInt
def miss: Unit
def hit: Unit
def access(touch_way: UInt): Unit
def access(touch_ways: Seq[Valid[UInt]]): Unit
def state_read: UInt
def get_next_state(state: UInt, touch_way: UInt): UInt
def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = {
touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev))
}
def get_replace_way(state: UInt): UInt
}
object ReplacementPolicy {
def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match {
case "random" => new RandomReplacement(n_ways)
case "lru" => new TrueLRU(n_ways)
case "plru" => new PseudoLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
}
class RandomReplacement(n_ways: Int) extends ReplacementPolicy {
private val replace = Wire(Bool())
replace := false.B
def nBits = 16
def perSet = false
private val lfsr = LFSR(nBits, replace)
def state_read = WireDefault(lfsr)
def way = Random(n_ways, lfsr)
def miss = replace := true.B
def hit = {}
def access(touch_way: UInt) = {}
def access(touch_ways: Seq[Valid[UInt]]) = {}
def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare
def get_replace_way(state: UInt) = way
}
abstract class SeqReplacementPolicy {
def access(set: UInt): Unit
def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
def way: UInt
}
abstract class SetAssocReplacementPolicy {
def access(set: UInt, touch_way: UInt): Unit
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
def way(set: UInt): UInt
}
class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
val logic = new RandomReplacement(n_ways)
def access(set: UInt) = { }
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
when (valid && !hit) { logic.miss }
}
def way = logic.way
}
class TrueLRU(n_ways: Int) extends ReplacementPolicy {
// True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others.
// The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits):
// [5] - 3 more recent than 2
// [4] - 3 more recent than 1
// [3] - 2 more recent than 1
// [2] - 3 more recent than 0
// [1] - 2 more recent than 0
// [0] - 1 more recent than 0
def nBits = (n_ways * (n_ways-1)) / 2
def perSet = true
private val state_reg = RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
private def extractMRUVec(state: UInt): Seq[UInt] = {
// Extract per-way information about which higher-indexed ways are more recently used
val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W)))
var lsb = 0
for (i <- 0 until n_ways-1) {
moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W))
lsb = lsb + (n_ways - i - 1)
}
moreRecentVec
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W)))
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
val wayDec = UIntToOH(touch_way, n_ways)
// Compute next value of triangular matrix
// set the touched way as more recent than every other way
nextState.zipWithIndex.map { case (e, i) =>
e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec)
}
nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1
}
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous")
}
}
def get_replace_way(state: UInt): UInt = {
val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix
// For each way, determine if all other ways are more recent
val mruWayDec = (0 until n_ways).map { i =>
val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR)
val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _))
upperMoreRecent && lowerMoreRecent
}
OHToUInt(mruWayDec)
}
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
@deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05")
def replace: UInt = way
}
class PseudoLRU(n_ways: Int) extends ReplacementPolicy {
// Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU
//
//
// - bits storage example for 4-way PLRU binary tree:
// bit[2]: ways 3+2 older than ways 1+0
// / \
// bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0
//
//
// - bits storage example for 3-way PLRU binary tree:
// bit[1]: way 2 older than ways 1+0
// \
// bit[0]: way 1 older than way 0
//
//
// - bits storage example for 8-way PLRU binary tree:
// bit[6]: ways 7-4 older than ways 3-0
// / \
// bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0
// / \ / \
// bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0
def nBits = n_ways - 1
def perSet = true
private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W))
def state_read = WireDefault(state_reg)
def access(touch_way: UInt): Unit = {
state_reg := get_next_state(state_reg, touch_way)
}
def access(touch_ways: Seq[Valid[UInt]]): Unit = {
when (touch_ways.map(_.valid).orR) {
state_reg := get_next_state(state_reg, touch_ways)
}
for (i <- 1 until touch_ways.size) {
cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous")
}
}
/** @param state state_reg bits for this sub-tree
* @param touch_way touched way encoded value bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways")
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val set_left_older = !touch_way(log2Ceil(tree_nways)-1)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(set_left_older,
Mux(set_left_older,
left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree
get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(set_left_older,
Mux(set_left_older,
get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer
right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value
!touch_way(0)
} else { // tree_nways <= 1
// we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires)
0.U(1.W)
}
}
def get_next_state(state: UInt, touch_way: UInt): UInt = {
val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways))
else touch_way.extract(log2Ceil(n_ways)-1,0)
get_next_state(state, touch_way_sized, n_ways)
}
/** @param state state_reg bits for this sub-tree
* @param tree_nways number of ways in this sub-tree
*/
def get_replace_way(state: UInt, tree_nways: Int): UInt = {
require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways")
// this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb
if (tree_nways > 2) {
// we are at a branching node in the tree, so recurse
val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree
val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree
val left_subtree_older = state(tree_nways-2)
val left_subtree_state = state.extract(tree_nways-3, right_nways-1)
val right_subtree_state = state(right_nways-2, 0)
if (left_nways > 1) {
// we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right
get_replace_way(left_subtree_state, left_nways), // recurse left
get_replace_way(right_subtree_state, right_nways))) // recurse right
} else {
// we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree
Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value
Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right
0.U(1.W),
get_replace_way(right_subtree_state, right_nways))) // recurse right
}
} else if (tree_nways == 2) {
// we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value
state(0)
} else { // tree_nways <= 1
// we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value
0.U(1.W)
}
}
def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways)
def way = get_replace_way(state_reg)
def miss = access(way)
def hit = {}
}
class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
val logic = new PseudoLRU(n_ways)
val state = SyncReadMem(n_sets, UInt(logic.nBits.W))
val current_state = Wire(UInt(logic.nBits.W))
val next_state = Wire(UInt(logic.nBits.W))
val plru_way = logic.get_replace_way(current_state)
def access(set: UInt) = {
current_state := state.read(set)
}
def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
val update_way = Mux(hit, way, plru_way)
next_state := logic.get_next_state(current_state, update_way)
when (valid) { state.write(set, next_state) }
}
def way = plru_way
}
class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy {
val logic = policy.toLowerCase match {
case "plru" => new PseudoLRU(n_ways)
case "lru" => new TrueLRU(n_ways)
case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t")
}
val state_vec =
if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line
else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W))))
def access(set: UInt, touch_way: UInt) = {
state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
}
def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
for (set <- 0 until n_sets) {
val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
when (set_touch_ways.map(_.valid).orR) {
state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
}
}
}
def way(set: UInt) = logic.get_replace_way(state_vec(set))
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) {
val plru = new PseudoLRU(n_ways)
// step
io.finished := RegNext(true.B, false.B)
val get_replace_ways = (0 until (1 << (n_ways-1))).map(state =>
plru.get_replace_way(state = state.U((n_ways-1).W)))
val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way =>
plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W))))
n_ways match {
case 2 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1))
assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1))
}
case 3 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3))
assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2))
assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2))
assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2))
assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2))
}
case 4 => {
assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0))
assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1))
assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2))
assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3))
assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4))
assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5))
assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6))
assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7))
assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0))
assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1))
assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2))
assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3))
assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0))
assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1))
assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2))
assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3))
assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0))
assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1))
assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2))
assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3))
assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0))
assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1))
assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2))
assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3))
assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0))
assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1))
assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2))
assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3))
assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0))
assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1))
assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2))
assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3))
assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0))
assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1))
assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2))
assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3))
assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0))
assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1))
assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2))
assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3))
}
case 5 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15))
assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0))
assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1))
assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2))
assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3))
assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4))
assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0))
assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1))
assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2))
assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3))
assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4))
assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0))
assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1))
assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2))
assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3))
assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4))
assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0))
assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1))
assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2))
assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3))
assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4))
assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0))
assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1))
assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2))
assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3))
assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4))
assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0))
assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1))
assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2))
assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3))
assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4))
assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0))
assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1))
assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2))
assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3))
assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4))
assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0))
assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1))
assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2))
assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3))
assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4))
assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0))
assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1))
assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2))
assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3))
assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4))
assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0))
assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1))
assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2))
assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3))
assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4))
assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0))
assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1))
assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2))
assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3))
assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4))
assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0))
assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1))
assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2))
assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3))
assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4))
assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0))
assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1))
assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2))
assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3))
assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4))
assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0))
assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1))
assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2))
assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3))
assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4))
assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0))
assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1))
assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2))
assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3))
assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4))
assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0))
assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1))
assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2))
assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3))
assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4))
}
case 6 => {
assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0))
assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1))
assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2))
assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3))
assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4))
assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5))
assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6))
assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7))
assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8))
assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9))
assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10))
assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11))
assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12))
assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13))
assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14))
assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15))
assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16))
assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17))
assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18))
assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19))
assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20))
assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21))
assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22))
assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23))
assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24))
assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25))
assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26))
assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27))
assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28))
assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29))
assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30))
assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31))
}
case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways")
}
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File TLBPermissions.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool, // if false, the below are undefined
r: Bool, // readable
w: Bool, // writeable
x: Bool, // executable
c: Bool, // cacheable
a: Bool, // arithmetic ops
l: Bool) // logical ops
object TLBPageLookup
{
private case class TLBFixedPermissions(
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
c: Boolean, // cacheable
a: Boolean, // arithmetic ops
l: Boolean) { // logical ops
val useful = r || w || x || c || a || l
}
private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = {
val permissions = managers.map { m =>
(m.address, TLBFixedPermissions(
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,
c = m.supportsAcquireB,
a = m.supportsArithmetic,
l = m.supportsLogical))
}
permissions
.filter(_._2.useful) // get rid of no-permission devices
.groupBy(_._2) // group by permission type
.mapValues(seq =>
AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
.toMap
}
// Unmapped memory is considered to be inhomogeneous
def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = {
require (isPow2(xLen) && xLen >= 8)
require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
val allSizes = TransferSizes(1, maxRequestBytes)
val amoSizes = TransferSizes(4, xLen/8)
val permissions = managers.foreach { m =>
require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}")
require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}")
require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)")
}
val grouped = groupRegions(managers)
.mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
// Find the minimal bits needed to distinguish between yes and no
val decisionMask = AddressDecoder(Seq(yes, no))
def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
val (yesf, nof) = (simplify(yes), simplify(no))
if (yesf.size < no.size) {
(x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _)
} else {
(x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _)
}
}
// Derive simplified property circuits (don't care when !homo)
val rfn = lowCostProperty(_.r)
val wfn = lowCostProperty(_.w)
val xfn = lowCostProperty(_.x)
val cfn = lowCostProperty(_.c)
val afn = lowCostProperty(_.a)
val lfn = lowCostProperty(_.l)
val homo = AddressSet.unify(grouped.values.flatten.toList)
(x: UInt) => TLBPermissions(
homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _),
r = rfn(x),
w = wfn(x),
x = xfn(x),
c = cfn(x),
a = afn(x),
l = lfn(x))
}
// Are all pageSize intervals of mapped regions homogeneous?
def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = {
groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize))
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File PTW.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
import chisel3.withClock
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ListBuffer
/** PTE request from TLB to PTW
*
* TLB send a PTE request to PTW when L1TLB miss
*/
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(vpnBits.W)
val need_gpa = Bool()
val vstage1 = Bool()
val stage2 = Bool()
}
/** PTE info from L2TLB to TLB
*
* containing: target PTE, exceptions, two-satge tanslation info
*/
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
/** ptw access exception */
val ae_ptw = Bool()
/** final access exception */
val ae_final = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** hypervisor read */
val hr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor execute */
val hx = Bool()
/** PTE to refill L1TLB
*
* source: L2TLB
*/
val pte = new PTE
/** pte pglevel */
val level = UInt(log2Ceil(pgLevels).W)
/** fragmented_superpage support */
val fragmented_superpage = Bool()
/** homogeneous for both pma and pmp */
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}
/** IO between TLB and PTW
*
* PTW receives :
* - PTE request
* - CSRs info
* - pmp results from PMP(in TLB)
*/
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val req = Decoupled(Valid(new PTWReq))
val resp = Flipped(Valid(new PTWResp))
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val customCSRs = Flipped(coreParams.customCSRs)
}
/** PTW performance statistics */
class PTWPerfEvents extends Bundle {
val l2miss = Bool()
val l2hit = Bool()
val pte_miss = Bool()
val pte_hit = Bool()
}
/** Datapath IO between PTW and Core
*
* PTW receives CSRs info, pmp checks, sfence instruction info
*
* PTW sends its performance statistics to core
*/
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val sfence = Flipped(Valid(new SFenceReq))
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val perf = Output(new PTWPerfEvents())
val customCSRs = Flipped(coreParams.customCSRs)
/** enable clock generated by ptw */
val clock_enabled = Output(Bool())
}
/** PTE template for transmission
*
* contains useful methods to check PTE attributes
* @see RV-priv spec 4.3.1 for pgae table entry format
*/
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
val reserved_for_future = UInt(10.W)
val ppn = UInt(44.W)
val reserved_for_software = Bits(2.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** global mapping */
val g = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
/** valid bit */
val v = Bool()
/** return true if find a pointer to next level page table */
def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U
/** return true if find a leaf PTE */
def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
/** user read */
def ur(dummy: Int = 0) = sr() && u
/** user write*/
def uw(dummy: Int = 0) = sw() && u
/** user execute */
def ux(dummy: Int = 0) = sx() && u
/** supervisor read */
def sr(dummy: Int = 0) = leaf() && r
/** supervisor write */
def sw(dummy: Int = 0) = leaf() && w && d
/** supervisor execute */
def sx(dummy: Int = 0) = leaf() && x
/** full permission: writable and executable in user mode */
def isFullPerm(dummy: Int = 0) = uw() && ux()
}
/** L2TLB PTE template
*
* contains tag bits
* @param nSets number of sets in L2TLB
* @see RV-priv spec 4.3.1 for page table entry format
*/
class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val idxBits = log2Ceil(nSets)
val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0)
val tag = UInt(tagBits.W)
val ppn = UInt(ppnBits.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
}
/** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC)
*
* It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb.
* Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process.
*
* ==Structure==
* - l2tlb : for leaf PTEs
* - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]]))
* - PLRU
* - pte_cache: for non-leaf PTEs
* - set-associative
* - LRU
* - s2_pte_cache: for non-leaf PTEs in 2-stage translation
* - set-associative
* - PLRU
*
* l2tlb Pipeline: 3 stage
* {{{
* stage 0 : read
* stage 1 : decode
* stage 2 : hit check
* }}}
* ==State Machine==
* s_ready: ready to reveive request from TLB
* s_req: request mem; pte_cache hit judge
* s_wait1: deal with l2tlb error
* s_wait2: final hit judge
* s_wait3: receive mem response
* s_fragment_superpage: for superpage PTE
*
* @note l2tlb hit happens in s_req or s_wait1
* @see RV-priv spec 4.3-4.6 for Virtual-Memory System
* @see RV-priv spec 8.5 for Two-Stage Address Translation
* @todo details in two-stage translation
*/
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
/** to n TLB */
val requestor = Flipped(Vec(n, new TLBPTWIO))
/** to HellaCache */
val mem = new HellaCacheIO
/** to Core
*
* contains CSRs info and performance statistics
*/
val dpath = new DatapathPTWIO
})
val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8)
val state = RegInit(s_ready)
val l2_refill_wire = Wire(Bool())
/** Arbiter to arbite request from n TLB */
val arb = Module(new Arbiter(Valid(new PTWReq), n))
// use TLB req as arbitor's input
arb.io.in <> io.requestor.map(_.req)
// receive req only when s_ready and not in refill
arb.io.out.ready := (state === s_ready) && !l2_refill_wire
val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B)))
val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate
io.dpath.clock_enabled := usingVM.B && clock_en
val gated_clock =
if (!usingVM || !tileParams.dcache.get.clockGate) clock
else ClockGate(clock, clock_en, "ptw_clock_gate")
withClock (gated_clock) { // entering gated-clock domain
val invalidated = Reg(Bool())
/** current PTE level
* {{{
* 0 <= count <= pgLevel-1
* count = pgLevel - 1 : leaf PTE
* count < pgLevel - 1 : non-leaf PTE
* }}}
*/
val count = Reg(UInt(log2Ceil(pgLevels).W))
val resp_ae_ptw = Reg(Bool())
val resp_ae_final = Reg(Bool())
val resp_pf = Reg(Bool())
val resp_gf = Reg(Bool())
val resp_hr = Reg(Bool())
val resp_hw = Reg(Bool())
val resp_hx = Reg(Bool())
val resp_fragmented_superpage = Reg(Bool())
/** tlb request */
val r_req = Reg(new PTWReq)
/** current selected way in arbitor */
val r_req_dest = Reg(Bits())
// to respond to L1TLB : l2_hit
// to construct mem.req.addr
val r_pte = Reg(new PTE)
val r_hgatp = Reg(new PTBR)
// 2-stage pageLevel
val aux_count = Reg(UInt(log2Ceil(pgLevels).W))
/** pte for 2-stage translation */
val aux_pte = Reg(new PTE)
val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case
val stage2 = Reg(Bool())
val stage2_final = Reg(Bool())
val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels
/** 2-stage translation both enable */
val do_both_stages = r_req.vstage1 && r_req.stage2
val max_count = count max aux_count
val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr)
val mem_resp_valid = RegNext(io.mem.resp.valid)
val mem_resp_data = RegNext(io.mem.resp.bits.data)
io.mem.uncached_resp.map { resp =>
assert(!(resp.valid && io.mem.resp.valid))
resp.ready := true.B
when (resp.valid) {
mem_resp_valid := true.B
mem_resp_data := resp.bits.data
}
}
// construct pte from mem.resp
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B }
}
(res,
Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U),
do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn))
}
// find non-leaf PTE, need traverse
val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U
/** address send to mem for enquerry */
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map { i =>
val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0)
(vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0)
}
val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U)
val vpn_idx = vpn_idxs(count) & mask
val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8)
val size = if (usingHypervisor) vaddrBits else paddrBits
//use r_pte.ppn as page table base address
//use vpn slice as offset
raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0)
}
/** stage2_pte_cache input addr */
val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else {
val vpn_idxs = (0 until pgLevels - 1).map { i =>
(r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0)
}
val vpn_idx = vpn_idxs(aux_count)
val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8)
raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0)
}
def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = {
(pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
}
/** PTECache caches non-leaf PTE
* @param s2 true: 2-stage address translation
*/
def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) {
(false.B, 0.U)
} else {
val plru = new PseudoLRU(coreParams.nPTECacheEntries)
val valid = RegInit(0.U(coreParams.nPTECacheEntries.W))
val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W)))
// not include full pte, only ppn
val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W)))
val can_hit =
if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final
else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2)
val can_refill =
if (s2) do_both_stages && !stage2 && !stage2_final
else can_hit
val tag =
if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits))
else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits))
val hits = tags.map(_ === tag).asUInt & valid
val hit = hits.orR && can_hit
// refill with mem response
when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) {
val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := tag
data(r) := pte.ppn
plru.access(r)
}
// replace
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U }
val lcount = if (s2) aux_count else count
for (i <- 0 until pgLevels-1) {
ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
}
(hit, Mux1H(hits, data))
}
// generate pte_cache
val (pte_cache_hit, pte_cache_data) = makePTECache(false)
// generate pte_cache with 2-stage translation
val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true)
// pte_cache hit or 2-stage pte_cache hit
val pte_hit = RegNext(false.B)
io.dpath.perf.pte_miss := false.B
io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
"PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
// l2_refill happens when find the leaf pte
val l2_refill = RegNext(false.B)
l2_refill_wire := l2_refill
io.dpath.perf.l2miss := false.B
io.dpath.perf.l2hit := false.B
// l2tlb
val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
require(isPow2(coreParams.nL2TLBWays))
require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays)
val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays
require(isPow2(nL2TLBSets))
val idxBits = log2Ceil(nL2TLBSets)
val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru")
val ram = DescribedSRAM(
name = "l2_tlb_ram",
desc = "L2 TLB",
size = nL2TLBSets,
data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W))
)
val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W)))
val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
// use r_req to construct tag
val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)
/** the valid vec for the selected set(including n ways) */
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := r_valid_vec
// replacement way
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U)
// refill with r_pte(leaf pte)
when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
entry.ppn := r_pte.ppn
entry.d := r_pte.d
entry.a := r_pte.a
entry.u := r_pte.u
entry.x := r_pte.x
entry.w := r_pte.w
entry.r := r_pte.r
entry.tag := r_tag
// if all the way are valid, use plru to select one way to be replaced,
// otherwise use PriorityEncoderOH to select one
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)
val mask = UIntToOH(r_idx)
for (way <- 0 until coreParams.nL2TLBWays) {
when (wmask(way)) {
valid(way) := valid(way) | mask
g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask)
}
}
}
// sfence happens
when (io.dpath.sfence.valid) {
val hg = usingHypervisor.B && io.dpath.sfence.bits.hg
for (way <- 0 until coreParams.nL2TLBWays) {
valid(way) :=
Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way),
0.U))
}
}
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
// read from tlb idx
val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid)))
val s2_valid_vec = RegEnable(r_valid_vec, s1_valid)
val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid)
val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR
when (s2_valid && s2_error) { valid.foreach { _ := 0.U }}
// decode
val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets)))
val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag))
val s2_hit = s2_valid && s2_hit_vec.orR
io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR)
io.dpath.perf.l2hit := s2_hit
when (s2_hit) {
l2_plru.access(r_idx, OHToUInt(s2_hit_vec))
assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit")
}
val s2_pte = Wire(new PTE)
val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec)
s2_pte.ppn := s2_hit_entry.ppn
s2_pte.d := s2_hit_entry.d
s2_pte.a := s2_hit_entry.a
s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec)
s2_pte.u := s2_hit_entry.u
s2_pte.x := s2_hit_entry.x
s2_pte.w := s2_hit_entry.w
s2_pte.r := s2_hit_entry.r
s2_pte.v := true.B
s2_pte.reserved_for_future := 0.U
s2_pte.reserved_for_software := 0.U
for (way <- 0 until coreParams.nL2TLBWays) {
ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way")
}
(s2_hit, s2_error, s2_pte, Some(ram))
}
// if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk
invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready)
// mem request
io.mem.keep_clock_enabled := false.B
io.mem.req.valid := state === s_req || state === s_dummy1
io.mem.req.bits.phys := true.B
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.size := log2Ceil(xLen/8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.idx.foreach(_ := pte_addr)
io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition
io.mem.req.bits.dv := do_both_stages && !stage2
io.mem.req.bits.tag := DontCare
io.mem.req.bits.no_resp := false.B
io.mem.req.bits.no_alloc := DontCare
io.mem.req.bits.no_xcpt := DontCare
io.mem.req.bits.data := DontCare
io.mem.req.bits.mask := DontCare
io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf
io.mem.s1_data := DontCare
io.mem.s2_kill := false.B
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}")
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous
}
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count)
val homogeneous = pmaHomogeneous && pmpHomogeneous
// response to tlb
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw
io.requestor(i).resp.bits.ae_final := resp_ae_final
io.requestor(i).resp.bits.pf := resp_pf
io.requestor(i).resp.bits.gf := resp_gf
io.requestor(i).resp.bits.hr := resp_hr
io.requestor(i).resp.bits.hw := resp_hw
io.requestor(i).resp.bits.hx := resp_hx
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := max_count
io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B
io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
io.requestor(i).customCSRs <> io.dpath.customCSRs
io.requestor(i).status := io.dpath.status
io.requestor(i).hstatus := io.dpath.hstatus
io.requestor(i).gstatus := io.dpath.gstatus
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine
val next_state = WireDefault(state)
state := OptimizationBarrier(next_state)
val do_switch = WireDefault(false.B)
switch (state) {
is (s_ready) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
r_req := arb.io.out.bits.bits
r_req_dest := arb.io.chosen
next_state := Mux(arb.io.out.bits.valid, s_req, s_ready)
stage2 := arb.io.out.bits.bits.stage2
stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1
count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U)
aux_pte.ppn := aux_ppn
aux_pte.reserved_for_future := 0.U
resp_ae_ptw := false.B
resp_ae_final := false.B
resp_pf := false.B
resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2
resp_hr := true.B
resp_hw := true.B
resp_hx := true.B
resp_fragmented_superpage := false.B
r_hgatp := io.dpath.hgatp
assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)
}
}
is (s_req) {
when(stage2 && count === r_hgatp_initial_count) {
gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr)
}
// pte_cache hit
when (stage2_pte_cache_hit) {
aux_count := aux_count + 1.U
aux_pte.ppn := stage2_pte_cache_data
aux_pte.reserved_for_future := 0.U
pte_hit := true.B
}.elsewhen (pte_cache_hit) {
count := count + 1.U
pte_hit := true.B
}.otherwise {
next_state := Mux(io.mem.req.ready, s_wait1, s_req)
}
when(resp_gf) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_wait1) {
// This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below
next_state := Mux(l2_hit, s_req, s_wait2)
}
is (s_wait2) {
next_state := s_wait3
io.dpath.perf.pte_miss := count < (pgLevels-1).U
when (io.mem.s2_xcpt.ae.ld) {
resp_ae_ptw := true.B
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_fragment_superpage) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
when (!homogeneous) {
count := (pgLevels-1).U
resp_fragmented_superpage := true.B
}
when (do_both_stages) {
resp_fragmented_superpage := true.B
}
}
}
val merged_pte = {
val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U)
val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U))
val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn
val stage1_ppn = stage1_ppns(count)
makePTE(stage1_ppn & superpage_mask, aux_pte)
}
r_pte := OptimizationBarrier(
// l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB
Mux(l2_hit && !l2_error && !resp_gf, l2_pte,
// S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp
Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte),
// pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem
Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte),
// 2-stage translation
Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte),
// when mem respond, store mem.resp.pte
Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte),
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte))))))))
when (l2_hit && !l2_error && !resp_gf) {
assert(state === s_req || state === s_wait1)
next_state := s_ready
resp_valid(r_req_dest) := true.B
count := (pgLevels-1).U
}
when (mem_resp_valid) {
assert(state === s_wait3)
next_state := s_req
when (traverse) {
when (do_both_stages && !stage2) { do_switch := true.B }
count := count + 1.U
}.otherwise {
val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
val ae = pte.v && invalid_paddr
val pf = pte.v && pte.reserved_for_future =/= 0.U
val success = pte.v && !ae && !pf && !gf
when (do_both_stages && !stage2_final && success) {
when (stage2) {
stage2 := false.B
count := aux_count
}.otherwise {
stage2_final := true.B
do_switch := true.B
}
}.otherwise {
// find a leaf pte, start l2 refill
l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa &&
(!r_req.vstage1 && !r_req.stage2 ||
do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm())
count := max_count
when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) {
next_state := s_fragment_superpage
}.otherwise {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
resp_ae_final := ae && pte.leaf()
resp_pf := pf && !stage2
resp_gf := gf || (pf && stage2)
resp_hr := !stage2 || (!pf && !gf && pte.ur())
resp_hw := !stage2 || (!pf && !gf && pte.uw())
resp_hx := !stage2 || (!pf && !gf && pte.ux())
}
}
}
when (io.mem.s2_nack) {
assert(state === s_wait2)
next_state := s_req
}
when (do_switch) {
aux_count := Mux(traverse, count + 1.U, count)
count := r_hgatp_initial_count
aux_pte := Mux(traverse, pte, {
val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn
makePTE(s1_ppns(count), pte)
})
stage2 := true.B
}
for (i <- 0 until pgLevels) {
val leaf = mem_resp_valid && !traverse && count === i.U
ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i")
ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i")
ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
} // leaving gated-clock domain
private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
/** Relace PTE.ppn with ppn */
private def makePTE(ppn: UInt, default: PTE) = {
val pte = WireDefault(default)
pte.ppn := ppn
pte
}
/** use hgatp and vpn to construct a new ppn */
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
}
/** use hgatp and vpn to check for gpa out of range */
private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits))
idxs.extract(count) =/= 0.U
}
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io.mem <> DontCare
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
}
File tlb.scala:
package boom.v4.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{CacheBlockBytes}
import freechips.rocketchip.diplomacy.{RegionType}
import freechips.rocketchip.util._
import boom.v4.common._
import boom.v4.exu.{BrResolutionInfo, Exception, CommitSignals}
import boom.v4.util._
class NBDTLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) {
require(!instruction)
val io = IO(new Bundle {
val req = Flipped(Vec(lsuWidth, Decoupled(new TLBReq(lgMaxSize))))
val miss_rdy = Output(Bool())
val resp = Output(Vec(lsuWidth, new TLBResp))
val sfence = Input(Valid(new SFenceReq))
val ptw = new TLBPTWIO
val kill = Input(Bool())
})
class EntryData extends Bundle {
val ppn = UInt(ppnBits.W)
val u = Bool()
val g = Bool()
val ae = Bool()
val sw = Bool()
val sx = Bool()
val sr = Bool()
val pw = Bool()
val px = Bool()
val pr = Bool()
val pal = Bool() // AMO logical
val paa = Bool() // AMO arithmetic
val eff = Bool() // get/put effects
val c = Bool()
val fragmented_superpage = Bool()
}
class Entry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean) extends Bundle {
require(nSectors == 1 || !superpage)
require(isPow2(nSectors))
require(!superpageOnly || superpage)
val level = UInt(log2Ceil(pgLevels).W)
val tag = UInt(vpnBits.W)
val data = Vec(nSectors, UInt(new EntryData().getWidth.W))
val valid = Vec(nSectors, Bool())
def entry_data = data.map(_.asTypeOf(new EntryData))
private def sectorIdx(vpn: UInt) = vpn.extract(log2Ceil(nSectors)-1, 0)
def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new EntryData))
def sectorHit(vpn: UInt) = valid.orR && sectorTagMatch(vpn)
def sectorTagMatch(vpn: UInt) = ((tag ^ vpn) >> log2Ceil(nSectors)) === 0.U
def hit(vpn: UInt) = {
if (superpage && usingVM) {
var tagMatch = valid.head
for (j <- 0 until pgLevels) {
val base = vpnBits - (j + 1) * pgLevelBits
val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B
tagMatch = tagMatch && (ignore || tag(base + pgLevelBits - 1, base) === vpn(base + pgLevelBits - 1, base))
}
tagMatch
} else {
val idx = sectorIdx(vpn)
valid(idx) && sectorTagMatch(vpn)
}
}
def ppn(vpn: UInt) = {
val data = getData(vpn)
if (superpage && usingVM) {
var res = data.ppn >> pgLevelBits*(pgLevels - 1)
for (j <- 1 until pgLevels) {
val ignore = (level < j.U) || (superpageOnly && j == pgLevels - 1).B
res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(vpnBits - j*pgLevelBits - 1, vpnBits - (j + 1)*pgLevelBits))
}
res
} else {
data.ppn
}
}
def insert(tag: UInt, level: UInt, entry: EntryData) {
this.tag := tag
this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0)
val idx = sectorIdx(tag)
valid(idx) := true.B
data(idx) := entry.asUInt
}
def invalidate() { valid.foreach(_ := false.B) }
def invalidateVPN(vpn: UInt) {
if (superpage) {
when (hit(vpn)) { invalidate() }
} else {
when (sectorTagMatch(vpn)) { valid(sectorIdx(vpn)) := false.B }
// For fragmented superpage mappings, we assume the worst (largest)
// case, and zap entries whose most-significant VPNs match
when (((tag ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) {
for ((v, e) <- valid zip entry_data)
when (e.fragmented_superpage) { v := false.B }
}
}
}
def invalidateNonGlobal() {
for ((v, e) <- valid zip entry_data)
when (!e.g) { v := false.B }
}
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f))
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
val sectored_entries = Reg(Vec((cfg.nSets * cfg.nWays) / cfg.nSectors, new Entry(cfg.nSectors, false, false)))
val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new Entry(1, true, true)))
val special_entry = (!pageGranularityPMPs).option(Reg(new Entry(1, true, false)))
def ordinary_entries = sectored_entries ++ superpage_entries
def all_entries = ordinary_entries ++ special_entry
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4)
val state = RegInit(s_ready)
val r_refill_tag = Reg(UInt(vpnBits.W))
val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W))
val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.size).W))
val r_sectored_hit_addr = Reg(UInt(log2Ceil(sectored_entries.size).W))
val r_sectored_hit = Reg(Bool())
val priv = if (instruction) io.ptw.status.prv else io.ptw.status.dprv
val priv_s = priv(0)
val priv_uses_vm = priv <= PRV.S.U
val vm_enabled = widthMap(w => usingVM.B && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req(w).bits.passthrough)
// share a single physical memory attribute checker (unshare if critical path)
val vpn = widthMap(w => io.req(w).bits.vaddr(vaddrBits-1, pgIdxBits))
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
val do_refill = usingVM.B && io.ptw.resp.valid
val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid
val mpu_ppn = widthMap(w =>
Mux(do_refill, refill_ppn,
Mux(vm_enabled(w) && special_entry.nonEmpty.B, special_entry.map(_.ppn(vpn(w))).getOrElse(0.U), io.req(w).bits.vaddr >> pgIdxBits)))
val mpu_physaddr = widthMap(w => Cat(mpu_ppn(w), io.req(w).bits.vaddr(pgIdxBits-1, 0)))
val pmp = Seq.fill(lsuWidth) { Module(new PMPChecker(lgMaxSize)) }
for (w <- 0 until lsuWidth) {
pmp(w).io.addr := mpu_physaddr(w)
pmp(w).io.size := io.req(w).bits.size
pmp(w).io.pmp := (io.ptw.pmp: Seq[PMP])
pmp(w).io.prv := Mux(usingVM.B && (do_refill || io.req(w).bits.passthrough /* PTW */), PRV.S.U, priv) // TODO should add separate bit to track PTW
}
val legal_address = widthMap(w => edge.manager.findSafe(mpu_physaddr(w)).reduce(_||_))
def fastCheck(member: TLManagerParameters => Boolean, w: Int) =
legal_address(w) && edge.manager.fastProperty(mpu_physaddr(w), member, (b:Boolean) => b.B)
val cacheable = widthMap(w => fastCheck(_.supportsAcquireT, w) && (instruction || !usingDataScratchpad).B)
val homogeneous = widthMap(w => TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr(w)).homogeneous)
val prot_r = widthMap(w => fastCheck(_.supportsGet, w) && pmp(w).io.r)
val prot_w = widthMap(w => fastCheck(_.supportsPutFull, w) && pmp(w).io.w)
val prot_al = widthMap(w => fastCheck(_.supportsLogical, w))
val prot_aa = widthMap(w => fastCheck(_.supportsArithmetic, w))
val prot_x = widthMap(w => fastCheck(_.executable, w) && pmp(w).io.x)
val prot_eff = widthMap(w => fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType, w))
val sector_hits = widthMap(w => VecInit(sectored_entries.map(_.sectorHit(vpn(w)))))
val superpage_hits = widthMap(w => VecInit(superpage_entries.map(_.hit(vpn(w)))))
val hitsVec = widthMap(w => VecInit(all_entries.map(vm_enabled(w) && _.hit(vpn(w)))))
val real_hits = widthMap(w => hitsVec(w).asUInt)
val hits = widthMap(w => Cat(!vm_enabled(w), real_hits(w)))
val ppn = widthMap(w => Mux1H(hitsVec(w) :+ !vm_enabled(w), all_entries.map(_.ppn(vpn(w))) :+ vpn(w)(ppnBits-1, 0)))
// permission bit arrays
when (do_refill) {
val pte = io.ptw.resp.bits.pte
val newEntry = Wire(new EntryData)
newEntry.ppn := pte.ppn
newEntry.c := cacheable(0)
newEntry.u := pte.u
newEntry.g := pte.g
newEntry.ae := io.ptw.resp.bits.ae_final
newEntry.sr := pte.sr()
newEntry.sw := pte.sw()
newEntry.sx := pte.sx()
newEntry.pr := prot_r(0)
newEntry.pw := prot_w(0)
newEntry.px := prot_x(0)
newEntry.pal := prot_al(0)
newEntry.paa := prot_aa(0)
newEntry.eff := prot_eff(0)
newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage
when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) {
special_entry.foreach(_.insert(r_refill_tag, io.ptw.resp.bits.level, newEntry))
}.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) {
for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) {
e.insert(r_refill_tag, io.ptw.resp.bits.level, newEntry)
}
}.otherwise {
val waddr = Mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr)
for ((e, i) <- sectored_entries.zipWithIndex) when (waddr === i.U) {
when (!r_sectored_hit) { e.invalidate() }
e.insert(r_refill_tag, 0.U, newEntry)
}
}
}
val entries = widthMap(w => VecInit(all_entries.map(_.getData(vpn(w)))))
val normal_entries = widthMap(w => VecInit(ordinary_entries.map(_.getData(vpn(w)))))
val nPhysicalEntries = 1 + special_entry.size
val ptw_ae_array = widthMap(w => Cat(false.B, entries(w).map(_.ae).asUInt))
val priv_rw_ok = widthMap(w => Mux(!priv_s || io.ptw.status.sum, entries(w).map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries(w).map(_.u).asUInt, 0.U))
val priv_x_ok = widthMap(w => Mux(priv_s, ~entries(w).map(_.u).asUInt, entries(w).map(_.u).asUInt))
val r_array = widthMap(w => Cat(true.B, priv_rw_ok(w) & (entries(w).map(_.sr).asUInt | Mux(io.ptw.status.mxr, entries(w).map(_.sx).asUInt, 0.U))))
val w_array = widthMap(w => Cat(true.B, priv_rw_ok(w) & entries(w).map(_.sw).asUInt))
val x_array = widthMap(w => Cat(true.B, priv_x_ok(w) & entries(w).map(_.sx).asUInt))
val pr_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_r(w)) , normal_entries(w).map(_.pr).asUInt) & ~ptw_ae_array(w))
val pw_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_w(w)) , normal_entries(w).map(_.pw).asUInt) & ~ptw_ae_array(w))
val px_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_x(w)) , normal_entries(w).map(_.px).asUInt) & ~ptw_ae_array(w))
val eff_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_eff(w)) , normal_entries(w).map(_.eff).asUInt))
val c_array = widthMap(w => Cat(Fill(nPhysicalEntries, cacheable(w)), normal_entries(w).map(_.c).asUInt))
val paa_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_aa(w)) , normal_entries(w).map(_.paa).asUInt))
val pal_array = widthMap(w => Cat(Fill(nPhysicalEntries, prot_al(w)) , normal_entries(w).map(_.pal).asUInt))
val paa_array_if_cached = widthMap(w => paa_array(w) | Mux(usingAtomicsInCache.B, c_array(w), 0.U))
val pal_array_if_cached = widthMap(w => pal_array(w) | Mux(usingAtomicsInCache.B, c_array(w), 0.U))
val prefetchable_array = widthMap(w => Cat((cacheable(w) && homogeneous(w)) << (nPhysicalEntries-1), normal_entries(w).map(_.c).asUInt))
val misaligned = widthMap(w => (io.req(w).bits.vaddr & (UIntToOH(io.req(w).bits.size) - 1.U)).orR)
val bad_va = widthMap(w => if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled(w) && {
val nPgLevelChoices = pgLevels - minPgLevels + 1
val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits
(for (i <- 0 until nPgLevelChoices) yield {
val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - 1))).U
val maskedVAddr = io.req(w).bits.vaddr & mask
io.ptw.ptbr.additionalPgLevels === i.U && !(maskedVAddr === 0.U || maskedVAddr === mask)
}).orR
})
val cmd_lrsc = widthMap(w => usingAtomics.B && io.req(w).bits.cmd.isOneOf(M_XLR, M_XSC))
val cmd_amo_logical = widthMap(w => usingAtomics.B && isAMOLogical(io.req(w).bits.cmd))
val cmd_amo_arithmetic = widthMap(w => usingAtomics.B && isAMOArithmetic(io.req(w).bits.cmd))
val cmd_read = widthMap(w => isRead(io.req(w).bits.cmd))
val cmd_write = widthMap(w => isWrite(io.req(w).bits.cmd))
val cmd_write_perms = widthMap(w => cmd_write(w) ||
coreParams.haveCFlush.B && io.req(w).bits.cmd === M_FLUSH_ALL) // not a write, but needs write permissions
val lrscAllowed = widthMap(w => Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array(w)))
val ae_array = widthMap(w =>
Mux(misaligned(w), eff_array(w), 0.U) |
Mux(cmd_lrsc(w) , ~lrscAllowed(w), 0.U))
val ae_valid_array = widthMap(w => Cat(if (special_entry.isEmpty) true.B else Cat(true.B, Fill(special_entry.size, !do_refill)),
Fill(normal_entries(w).size, true.B)))
val ae_ld_array = widthMap(w => Mux(cmd_read(w), ae_array(w) | ~pr_array(w), 0.U))
val ae_st_array = widthMap(w =>
Mux(cmd_write_perms(w) , ae_array(w) | ~pw_array(w), 0.U) |
Mux(cmd_amo_logical(w) , ~pal_array_if_cached(w), 0.U) |
Mux(cmd_amo_arithmetic(w), ~paa_array_if_cached(w), 0.U))
val must_alloc_array = widthMap(w =>
Mux(cmd_amo_logical(w) , ~paa_array(w), 0.U) |
Mux(cmd_amo_arithmetic(w), ~pal_array(w), 0.U) |
Mux(cmd_lrsc(w) , ~0.U(pal_array(w).getWidth.W), 0.U))
val ma_ld_array = widthMap(w => Mux(misaligned(w) && cmd_read(w) , ~eff_array(w), 0.U))
val ma_st_array = widthMap(w => Mux(misaligned(w) && cmd_write(w), ~eff_array(w), 0.U))
val pf_ld_array = widthMap(w => Mux(cmd_read(w) , ~(r_array(w) | ptw_ae_array(w)), 0.U))
val pf_st_array = widthMap(w => Mux(cmd_write_perms(w), ~(w_array(w) | ptw_ae_array(w)), 0.U))
val pf_inst_array = widthMap(w => ~(x_array(w) | ptw_ae_array(w)))
val tlb_hit = widthMap(w => real_hits(w).orR)
val tlb_miss = widthMap(w => vm_enabled(w) && !bad_va(w) && !tlb_hit(w))
val sectored_plru = new PseudoLRU(sectored_entries.size)
val superpage_plru = new PseudoLRU(superpage_entries.size)
for (w <- 0 until lsuWidth) {
when (io.req(w).valid && vm_enabled(w)) {
when (sector_hits(w).orR) { sectored_plru.access(OHToUInt(sector_hits(w))) }
when (superpage_hits(w).orR) { superpage_plru.access(OHToUInt(superpage_hits(w))) }
}
}
// Superpages create the possibility that two entries in the TLB may match.
// This corresponds to a software bug, but we can't return complete garbage;
// we must return either the old translation or the new translation. This
// isn't compatible with the Mux1H approach. So, flush the TLB and report
// a miss on duplicate entries.
val multipleHits = widthMap(w => PopCountAtLeast(real_hits(w), 2))
io.miss_rdy := state === s_ready
for (w <- 0 until lsuWidth) {
io.req(w).ready := true.B
io.resp(w).gpa := DontCare
io.resp(w).gpa_is_pte := DontCare
io.resp(w).gf.ld := false.B
io.resp(w).gf.st := false.B
io.resp(w).gf.inst := false.B
io.resp(w).pf.ld := (bad_va(w) && cmd_read(w)) || (pf_ld_array(w) & hits(w)).orR
io.resp(w).pf.st := (bad_va(w) && cmd_write_perms(w)) || (pf_st_array(w) & hits(w)).orR
io.resp(w).pf.inst := bad_va(w) || (pf_inst_array(w) & hits(w)).orR
io.resp(w).ae.ld := (ae_valid_array(w) & ae_ld_array(w) & hits(w)).orR
io.resp(w).ae.st := (ae_valid_array(w) & ae_st_array(w) & hits(w)).orR
io.resp(w).ae.inst := (ae_valid_array(w) & ~px_array(w) & hits(w)).orR
io.resp(w).ma.ld := (ma_ld_array(w) & hits(w)).orR
io.resp(w).ma.st := (ma_st_array(w) & hits(w)).orR
io.resp(w).ma.inst := false.B // this is up to the pipeline to figure out
io.resp(w).cacheable := (c_array(w) & hits(w)).orR
io.resp(w).must_alloc := (must_alloc_array(w) & hits(w)).orR
io.resp(w).prefetchable := (prefetchable_array(w) & hits(w)).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B
io.resp(w).miss := do_refill || tlb_miss(w) || multipleHits(w)
io.resp(w).paddr := Cat(ppn(w), io.req(w).bits.vaddr(pgIdxBits-1, 0))
io.resp(w).size := io.req(w).bits.size
io.resp(w).cmd := io.req(w).bits.cmd
}
io.ptw.customCSRs := DontCare
io.ptw.req.valid := state === s_request
io.ptw.req.bits := DontCare
io.ptw.req.bits.valid := !io.kill
io.ptw.req.bits.bits.addr := r_refill_tag
if (usingVM) {
val sfence = io.sfence.valid
for (w <- 0 until lsuWidth) {
when (io.req(w).fire && tlb_miss(w) && state === s_ready) {
state := s_request
r_refill_tag := vpn(w)
r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way)
r_sectored_repl_addr := replacementEntry(sectored_entries, sectored_plru.way)
r_sectored_hit_addr := OHToUInt(sector_hits(w))
r_sectored_hit := sector_hits(w).orR
}
}
when (state === s_request) {
when (sfence) { state := s_ready }
when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) }
when (io.kill) { state := s_ready }
}
when (state === s_wait && sfence) {
state := s_wait_invalidate
}
when (io.ptw.resp.valid) {
state := s_ready
}
when (sfence) {
for (w <- 0 until lsuWidth) {
assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn(w))
for (e <- all_entries) {
when (io.sfence.bits.rs1) { e.invalidateVPN(vpn(w)) }
.elsewhen (io.sfence.bits.rs2) { e.invalidateNonGlobal() }
.otherwise { e.invalidate() }
}
}
}
when (multipleHits.orR || reset.asBool) {
all_entries.foreach(_.invalidate())
}
}
def replacementEntry(set: Seq[Entry], alt: UInt) = {
val valids = set.map(_.valid.orR).asUInt
Mux(valids.andR, alt, PriorityEncoder(~valids))
}
}
| module NBDTLB_1( // @[tlb.scala:17:7]
input clock, // @[tlb.scala:17:7]
input reset, // @[tlb.scala:17:7]
input io_req_0_valid, // @[tlb.scala:19:14]
input [33:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14]
input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14]
input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14]
output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14]
output io_resp_0_pf_ld, // @[tlb.scala:19:14]
output io_resp_0_pf_st, // @[tlb.scala:19:14]
output io_resp_0_ae_ld, // @[tlb.scala:19:14]
output io_resp_0_ae_st, // @[tlb.scala:19:14]
output io_resp_0_ma_ld, // @[tlb.scala:19:14]
output io_resp_0_ma_st, // @[tlb.scala:19:14]
output io_resp_0_cacheable, // @[tlb.scala:19:14]
output [20:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14]
input io_ptw_resp_valid, // @[tlb.scala:19:14]
input [43:0] io_ptw_resp_bits_pte_ppn // @[tlb.scala:19:14]
);
wire _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_11_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_10_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_9_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_8_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_7_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_6_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_5_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_4_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_3_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_2_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_1_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_c; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_eff; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_paa; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_pal; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_pr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_px; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_pw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_sr; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_sx; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_sw; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_ae; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_g; // @[tlb.scala:212:45]
wire _normal_entries_WIRE_24_0_u; // @[tlb.scala:212:45]
wire [19:0] _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:212:45]
wire _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_12_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_12_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_11_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_11_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_10_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_10_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_9_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_9_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_8_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_8_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_7_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_7_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_6_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_6_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_5_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_5_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_4_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_4_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_3_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_3_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_2_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_2_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_1_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_1_ppn; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_c; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_eff; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_paa; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_pal; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_pr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_px; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_pw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_sr; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_sx; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_sw; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_ae; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_g; // @[tlb.scala:211:38]
wire _entries_WIRE_26_0_u; // @[tlb.scala:211:38]
wire [19:0] _entries_WIRE_26_0_ppn; // @[tlb.scala:211:38]
wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7]
wire [33:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7]
wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7]
wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7]
wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[tlb.scala:17:7, :122:29]
wire [11:0] _ae_valid_array_T_2 = 12'hFFF; // @[tlb.scala:255:9]
wire [34:0] _prot_r_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_r_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_w_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_w_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_al_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_al_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_aa_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_aa_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [13:0] _hits_T_1 = 14'h2000; // @[tlb.scala:119:49, :173:31]
wire [13:0] hits_0 = 14'h2000; // @[tlb.scala:119:49, :173:31]
wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73]
wire [12:0] _real_hits_T = 13'h0; // @[tlb.scala:172:44]
wire [12:0] real_hits_0 = 13'h0; // @[tlb.scala:119:49]
wire [12:0] _priv_rw_ok_T_6 = 13'h0; // @[tlb.scala:215:108]
wire [12:0] _r_array_T_2 = 13'h0; // @[tlb.scala:217:98]
wire [1:0] _ae_valid_array_T_1 = 2'h3; // @[tlb.scala:254:84]
wire [13:0] _ae_valid_array_T_3 = 14'h3FFF; // @[tlb.scala:254:41]
wire [13:0] ae_valid_array_0 = 14'h3FFF; // @[tlb.scala:119:49]
wire [13:0] _must_alloc_array_T_5 = 14'h3FFF; // @[tlb.scala:264:32]
wire [6:0] real_hits_hi = 7'h0; // @[tlb.scala:172:44]
wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[tlb.scala:17:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7, :19:14]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Misc.scala:181:37]
wire [5:0] real_hits_lo = 6'h0; // @[Misc.scala:181:37]
wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7, :19:14]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7, :19:14]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14]
wire [31:0] io_ptw_status_isa = 32'h0; // @[tlb.scala:17:7, :19:14]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7, :19:14]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Misc.scala:182:39]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Misc.scala:182:39]
wire [3:0] real_hits_hi_hi = 4'h0; // @[Misc.scala:182:39]
wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [3:0] io_ptw_ptbr_mode = 4'h8; // @[tlb.scala:17:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[tlb.scala:17:7, :19:14]
wire [32:0] io_sfence_bits_addr = 33'h0; // @[tlb.scala:17:7, :19:14]
wire [32:0] io_ptw_resp_bits_gpa_bits = 33'h0; // @[tlb.scala:17:7, :19:14]
wire [33:0] io_resp_0_gpa = 34'h0; // @[tlb.scala:17:7]
wire [33:0] _mpu_ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_3 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_5 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_7 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_9 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_11 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_13 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_15 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_17 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_19 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_21 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_23 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _ppn_data_WIRE_25 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_1 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_3 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_5 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_7 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_9 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_11 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_13 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_15 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_17 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_19 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_21 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_23 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _entries_WIRE_25 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_1 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_3 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_5 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_7 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_9 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_11 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_13 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_15 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_17 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_19 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_21 = 34'h0; // @[tlb.scala:58:79]
wire [33:0] _normal_entries_WIRE_23 = 34'h0; // @[tlb.scala:58:79]
wire [1:0] io_req_0_bits_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_dprv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_sxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_uxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_fs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_mpp = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] _pmp_0_io_prv_T_2 = 2'h0; // @[tlb.scala:155:25]
wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[tlb.scala:172:44]
wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[tlb.scala:172:44]
wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[tlb.scala:172:44]
wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[tlb.scala:172:44]
wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[tlb.scala:172:44]
wire [1:0] special_entry_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_1_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_2_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_3_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_4_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_5_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_6_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_7_data_hi_hi_lo = 2'h0; // @[tlb.scala:95:26]
wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] io_ptw_resp_bits_level = 2'h2; // @[tlb.scala:17:7]
wire [1:0] _special_entry_level_T = 2'h2; // @[package.scala:163:13]
wire [1:0] special_entry_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_0_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_1_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_2_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_3_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_4_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_5_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_6_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_7_data_hi_lo_hi = 2'h2; // @[tlb.scala:95:26]
wire [2:0] real_hits_lo_lo = 3'h0; // @[tlb.scala:172:44]
wire [2:0] real_hits_lo_hi = 3'h0; // @[tlb.scala:172:44]
wire [2:0] real_hits_hi_lo = 3'h0; // @[tlb.scala:172:44]
wire [2:0] waddr = 3'h0; // @[tlb.scala:203:22]
wire [2:0] state_reg_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] state_reg_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7]
wire io_miss_rdy = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_req_ready = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_req_bits_valid = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_d = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_a = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_u = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_w = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_r = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_v = 1'h1; // @[tlb.scala:17:7]
wire priv_uses_vm = 1'h1; // @[tlb.scala:138:27]
wire _vm_enabled_T = 1'h1; // @[tlb.scala:139:63]
wire _vm_enabled_T_3 = 1'h1; // @[tlb.scala:139:112]
wire _homogeneous_T_24 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_25 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_39 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_40 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_w_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_al_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_aa_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _hits_T = 1'h1; // @[tlb.scala:173:32]
wire _ppn_T = 1'h1; // @[tlb.scala:174:47]
wire newEntry_u = 1'h1; // @[tlb.scala:179:24]
wire newEntry_sw = 1'h1; // @[tlb.scala:179:24]
wire newEntry_sr = 1'h1; // @[tlb.scala:179:24]
wire _newEntry_sr_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sr_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sr_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _newEntry_sr_T_5 = 1'h1; // @[PTW.scala:149:35]
wire _newEntry_sw_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sw_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sw_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _newEntry_sw_T_5 = 1'h1; // @[PTW.scala:151:35]
wire _newEntry_sw_T_6 = 1'h1; // @[PTW.scala:151:40]
wire _newEntry_sx_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sx_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sx_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _priv_rw_ok_T = 1'h1; // @[tlb.scala:215:40]
wire _priv_rw_ok_T_1 = 1'h1; // @[tlb.scala:215:48]
wire _ae_valid_array_T = 1'h1; // @[tlb.scala:254:118]
wire _tlb_miss_T = 1'h1; // @[tlb.scala:272:49]
wire _tlb_miss_T_2 = 1'h1; // @[tlb.scala:272:63]
wire _io_miss_rdy_T = 1'h1; // @[tlb.scala:290:24]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[tlb.scala:319:28]
wire io_req_0_bits_passthrough = 1'h0; // @[tlb.scala:17:7]
wire io_req_0_bits_v = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_miss = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_valid = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_rs1 = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_rs2 = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_asid = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_hv = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_hg = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_valid = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_ae_ptw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_ae_final = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pf = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gf = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hx = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_g = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_x = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_homogeneous = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gpa_valid = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_debug = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_cease = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_wfi = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_dv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_v = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sd = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mpv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mxr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sum = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mprv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_spp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mpie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_spie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[tlb.scala:17:7]
wire io_kill = 1'h0; // @[tlb.scala:17:7]
wire priv_s = 1'h0; // @[tlb.scala:137:20]
wire _vm_enabled_T_1 = 1'h0; // @[tlb.scala:139:44]
wire _vm_enabled_T_2 = 1'h0; // @[tlb.scala:139:93]
wire _vm_enabled_T_4 = 1'h0; // @[tlb.scala:139:109]
wire vm_enabled_0 = 1'h0; // @[tlb.scala:119:49]
wire do_refill = 1'h0; // @[tlb.scala:144:29]
wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire invalidate_refill = 1'h0; // @[tlb.scala:145:88]
wire _mpu_ppn_T = 1'h0; // @[tlb.scala:148:35]
wire _pmp_0_io_prv_T = 1'h0; // @[tlb.scala:155:50]
wire _pmp_0_io_prv_T_1 = 1'h0; // @[tlb.scala:155:36]
wire _cacheable_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _prot_x_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _prot_eff_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _sector_hits_T = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_7 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_14 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_21 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_28 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_35 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_42 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_49 = 1'h0; // @[package.scala:81:59]
wire _superpage_hits_T_3 = 1'h0; // @[tlb.scala:72:20]
wire _superpage_hits_T_7 = 1'h0; // @[tlb.scala:72:20]
wire _superpage_hits_T_11 = 1'h0; // @[tlb.scala:72:20]
wire _superpage_hits_T_15 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_3 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_4 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_8 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_9 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_13 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_14 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_18 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_19 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_23 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_24 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_28 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_29 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_33 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_34 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_38 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_39 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_43 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_44 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_48 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_49 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_53 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_54 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_58 = 1'h0; // @[tlb.scala:72:20]
wire _hitsVec_T_59 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_T_64 = 1'h0; // @[tlb.scala:171:69]
wire _hitsVec_WIRE_0 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_1 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_2 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_3 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_4 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_5 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_6 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_7 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_8 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_9 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_10 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_11 = 1'h0; // @[tlb.scala:171:38]
wire _hitsVec_WIRE_12 = 1'h0; // @[tlb.scala:171:38]
wire hitsVec_0_0 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_1 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_2 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_3 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_4 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_5 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_6 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_7 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_8 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_9 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_10 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_11 = 1'h0; // @[tlb.scala:119:49]
wire hitsVec_0_12 = 1'h0; // @[tlb.scala:119:49]
wire newEntry_g = 1'h0; // @[tlb.scala:179:24]
wire newEntry_ae = 1'h0; // @[tlb.scala:179:24]
wire newEntry_sx = 1'h0; // @[tlb.scala:179:24]
wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:179:24]
wire _newEntry_sr_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sw_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sx_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35]
wire _superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13]
wire bad_va_0 = 1'h0; // @[tlb.scala:119:49]
wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:248:29]
wire _tlb_hit_T = 1'h0; // @[tlb.scala:271:44]
wire tlb_hit_0 = 1'h0; // @[tlb.scala:119:49]
wire _tlb_miss_T_1 = 1'h0; // @[tlb.scala:272:46]
wire _tlb_miss_T_3 = 1'h0; // @[tlb.scala:272:60]
wire tlb_miss_0 = 1'h0; // @[tlb.scala:119:49]
wire state_reg_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state_3 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_3 = 1'h0; // @[Replacement.scala:198:38]
wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire _multipleHits_T_49 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_0 = 1'h0; // @[tlb.scala:119:49]
wire _io_resp_0_pf_ld_T = 1'h0; // @[tlb.scala:298:38]
wire _io_resp_0_pf_st_T = 1'h0; // @[tlb.scala:299:38]
wire _io_resp_0_miss_T = 1'h0; // @[tlb.scala:310:35]
wire _io_resp_0_miss_T_1 = 1'h0; // @[tlb.scala:310:50]
wire _io_ptw_req_valid_T = 1'h0; // @[tlb.scala:317:29]
wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7]
wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7]
wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:311:28]
wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:298:54]
wire _io_resp_0_pf_st_T_3; // @[tlb.scala:299:61]
wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:300:37]
wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:301:74]
wire _io_resp_0_ae_st_T_2; // @[tlb.scala:302:74]
wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:303:74]
wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:304:54]
wire _io_resp_0_ma_st_T_1; // @[tlb.scala:305:54]
wire _io_resp_0_cacheable_T_1; // @[tlb.scala:307:55]
wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:308:64]
wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:309:70]
wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_pf_st_0; // @[tlb.scala:17:7]
wire io_resp_0_pf_inst; // @[tlb.scala:17:7]
wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_ae_st_0; // @[tlb.scala:17:7]
wire io_resp_0_ae_inst; // @[tlb.scala:17:7]
wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_ma_st_0; // @[tlb.scala:17:7]
wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7]
wire io_resp_0_cacheable_0; // @[tlb.scala:17:7]
wire io_resp_0_must_alloc; // @[tlb.scala:17:7]
wire io_resp_0_prefetchable; // @[tlb.scala:17:7]
wire [20:0] _vpn_T = io_req_0_bits_vaddr_0[32:12]; // @[tlb.scala:17:7, :142:47]
wire [20:0] vpn_0 = _vpn_T; // @[tlb.scala:119:49, :142:47]
wire [20:0] _sector_hits_T_3 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_10 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_17 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_24 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_31 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_38 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_45 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _sector_hits_T_52 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _superpage_hits_T = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _superpage_hits_T_4 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _superpage_hits_T_8 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _superpage_hits_T_12 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_5 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_10 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_15 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_20 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_25 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_30 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_35 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_40 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_45 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_50 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_55 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [20:0] _hitsVec_T_60 = vpn_0; // @[tlb.scala:60:43, :119:49]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :143:44, :179:24]
wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_13; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_12; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_11; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_10; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_9; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_8; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_7; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_6; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_5; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_4; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_3; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_2; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T_1; // @[tlb.scala:58:79]
wire _mpu_ppn_data_T; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:58:79]
wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:58:79]
assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79]
wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:58:79]
wire [21:0] _mpu_ppn_T_1 = io_req_0_bits_vaddr_0[33:12]; // @[tlb.scala:17:7, :148:134]
wire [21:0] _mpu_ppn_T_2 = _mpu_ppn_T_1; // @[tlb.scala:148:{20,134}]
wire [21:0] _mpu_ppn_T_3 = _mpu_ppn_T_2; // @[tlb.scala:147:20, :148:20]
wire [21:0] mpu_ppn_0 = _mpu_ppn_T_3; // @[tlb.scala:119:49, :147:20]
wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72]
wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :149:72, :311:57]
wire [33:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:119:49, :149:{39,72}]
wire [33:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:119:49, :149:39]
wire [33:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_26 = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _GEN = {mpu_physaddr_0[33:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T; // @[Parameters.scala:137:31]
assign _legal_address_T = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T; // @[Parameters.scala:137:31]
assign _homogeneous_T = _GEN; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [33:0] _GEN_0 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_16; // @[Parameters.scala:137:31]
assign _prot_x_T_16 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_16; // @[Parameters.scala:137:31]
assign _prot_eff_T_16 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [33:0] _legal_address_T_10 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [33:0] _GEN_1 = {mpu_physaddr_0[33:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [33:0] _GEN_2 = {mpu_physaddr_0[33:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _cacheable_T_5; // @[Parameters.scala:137:31]
assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31]
assign _homogeneous_T_15 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_33; // @[Parameters.scala:137:31]
assign _homogeneous_T_33 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_5; // @[Parameters.scala:137:31]
assign _prot_x_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_5; // @[Parameters.scala:137:31]
assign _prot_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire _legal_address_T_25 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_26 = _legal_address_T_25 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_27 = _legal_address_T_26 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_28 = _legal_address_T_27 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire legal_address_0 = _legal_address_T_28; // @[tlb.scala:119:49, :157:84]
wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22]
wire _prot_w_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22]
wire _prot_al_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22]
wire _prot_aa_T_5 = legal_address_0; // @[tlb.scala:119:49, :159:22]
wire [34:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _cacheable_T_2 = _cacheable_T_1 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46]
wire _cacheable_T_4 = _cacheable_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _cacheable_T_7 = _cacheable_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46]
wire _cacheable_T_9 = _cacheable_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _cacheable_T_11 = _cacheable_T_9; // @[Mux.scala:30:73]
wire _cacheable_T_12 = _cacheable_T_11; // @[Mux.scala:30:73]
wire _cacheable_WIRE = _cacheable_T_12; // @[Mux.scala:30:73]
wire _cacheable_T_13 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73]
wire _cacheable_T_14 = _cacheable_T_13; // @[tlb.scala:159:22, :160:66]
wire cacheable_0 = _cacheable_T_14; // @[tlb.scala:119:49, :160:66]
wire newEntry_c = cacheable_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_20 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_21 = _homogeneous_T_20 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_22 = _homogeneous_T_21 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_23 = _homogeneous_T_22 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire homogeneous_0 = _homogeneous_T_23; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_27 = {1'h0, _homogeneous_T_26}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_28 = _homogeneous_T_27 & 35'h80002000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_29 = _homogeneous_T_28; // @[Parameters.scala:137:46]
wire _homogeneous_T_30 = _homogeneous_T_29 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_31 = _homogeneous_T_30; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_32 = ~_homogeneous_T_31; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_34 = {1'h0, _homogeneous_T_33}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_35 = _homogeneous_T_34 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_36 = _homogeneous_T_35; // @[Parameters.scala:137:46]
wire _homogeneous_T_37 = _homogeneous_T_36 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_38 = _homogeneous_T_37; // @[TLBPermissions.scala:85:66]
wire [34:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}]
wire _prot_r_T_6 = _prot_r_T_5; // @[tlb.scala:159:22, :162:60]
wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:119:49, :162:60]
wire newEntry_pr = prot_r_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}]
wire _prot_w_T_6 = _prot_w_T_5; // @[tlb.scala:159:22, :163:64]
wire prot_w_0 = _prot_w_T_6; // @[tlb.scala:119:49, :163:64]
wire newEntry_pw = prot_w_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}]
wire prot_al_0 = _prot_al_T_5; // @[tlb.scala:119:49, :159:22]
wire newEntry_pal = prot_al_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}]
wire prot_aa_0 = _prot_aa_T_5; // @[tlb.scala:119:49, :159:22]
wire newEntry_paa = prot_aa_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_2 = _prot_x_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46]
wire _prot_x_T_4 = _prot_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_7 = _prot_x_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46]
wire _prot_x_T_9 = _prot_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_x_T_10 = _prot_x_T_4 | _prot_x_T_9; // @[Parameters.scala:629:89]
wire _prot_x_T_22 = _prot_x_T_10; // @[Mux.scala:30:73]
wire [33:0] _GEN_3 = {mpu_physaddr_0[33:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_11; // @[Parameters.scala:137:31]
assign _prot_x_T_11 = _GEN_3; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_11; // @[Parameters.scala:137:31]
assign _prot_eff_T_11 = _GEN_3; // @[Parameters.scala:137:31]
wire [34:0] _prot_x_T_12 = {1'h0, _prot_x_T_11}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_13 = _prot_x_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_14 = _prot_x_T_13; // @[Parameters.scala:137:46]
wire _prot_x_T_15 = _prot_x_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_x_T_17 = {1'h0, _prot_x_T_16}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_18 = _prot_x_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_19 = _prot_x_T_18; // @[Parameters.scala:137:46]
wire _prot_x_T_20 = _prot_x_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_x_T_21 = _prot_x_T_15 | _prot_x_T_20; // @[Parameters.scala:629:89]
wire _prot_x_T_24 = _prot_x_T_22; // @[Mux.scala:30:73]
wire _prot_x_WIRE = _prot_x_T_24; // @[Mux.scala:30:73]
wire _prot_x_T_25 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73]
wire _prot_x_T_26 = _prot_x_T_25; // @[tlb.scala:159:22, :166:59]
wire prot_x_0 = _prot_x_T_26; // @[tlb.scala:119:49, :166:59]
wire newEntry_px = prot_x_0; // @[tlb.scala:119:49, :179:24]
wire [34:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_2 = _prot_eff_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46]
wire _prot_eff_T_4 = _prot_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_7 = _prot_eff_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46]
wire _prot_eff_T_9 = _prot_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_eff_T_10 = _prot_eff_T_4 | _prot_eff_T_9; // @[Parameters.scala:629:89]
wire [34:0] _prot_eff_T_12 = {1'h0, _prot_eff_T_11}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_13 = _prot_eff_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_14 = _prot_eff_T_13; // @[Parameters.scala:137:46]
wire _prot_eff_T_15 = _prot_eff_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_eff_T_17 = {1'h0, _prot_eff_T_16}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_18 = _prot_eff_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_19 = _prot_eff_T_18; // @[Parameters.scala:137:46]
wire _prot_eff_T_20 = _prot_eff_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_eff_T_21 = _prot_eff_T_15 | _prot_eff_T_20; // @[Parameters.scala:629:89]
wire _prot_eff_T_23 = _prot_eff_T_21; // @[Mux.scala:30:73]
wire _prot_eff_T_24 = _prot_eff_T_23; // @[Mux.scala:30:73]
wire _prot_eff_WIRE = _prot_eff_T_24; // @[Mux.scala:30:73]
wire _prot_eff_T_25 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73]
wire prot_eff_0 = _prot_eff_T_25; // @[tlb.scala:119:49, :159:22]
wire newEntry_eff = prot_eff_0; // @[tlb.scala:119:49, :179:24]
wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59]
wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_8 = _sector_hits_T_7; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_11 = _sector_hits_T_10[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_12 = _sector_hits_T_11 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59]
wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_15 = _sector_hits_T_14; // @[package.scala:81:59]
wire _sector_hits_T_16 = _sector_hits_T_15; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_18 = _sector_hits_T_17[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_19 = _sector_hits_T_18 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_20 = _sector_hits_T_16 & _sector_hits_T_19; // @[package.scala:81:59]
wire _sector_hits_WIRE_2 = _sector_hits_T_20; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_22 = _sector_hits_T_21; // @[package.scala:81:59]
wire _sector_hits_T_23 = _sector_hits_T_22; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_25 = _sector_hits_T_24[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_26 = _sector_hits_T_25 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_27 = _sector_hits_T_23 & _sector_hits_T_26; // @[package.scala:81:59]
wire _sector_hits_WIRE_3 = _sector_hits_T_27; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_29 = _sector_hits_T_28; // @[package.scala:81:59]
wire _sector_hits_T_30 = _sector_hits_T_29; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_32 = _sector_hits_T_31[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_33 = _sector_hits_T_32 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_34 = _sector_hits_T_30 & _sector_hits_T_33; // @[package.scala:81:59]
wire _sector_hits_WIRE_4 = _sector_hits_T_34; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_36 = _sector_hits_T_35; // @[package.scala:81:59]
wire _sector_hits_T_37 = _sector_hits_T_36; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_39 = _sector_hits_T_38[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_40 = _sector_hits_T_39 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_41 = _sector_hits_T_37 & _sector_hits_T_40; // @[package.scala:81:59]
wire _sector_hits_WIRE_5 = _sector_hits_T_41; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_43 = _sector_hits_T_42; // @[package.scala:81:59]
wire _sector_hits_T_44 = _sector_hits_T_43; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_46 = _sector_hits_T_45[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_47 = _sector_hits_T_46 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_48 = _sector_hits_T_44 & _sector_hits_T_47; // @[package.scala:81:59]
wire _sector_hits_WIRE_6 = _sector_hits_T_48; // @[tlb.scala:59:42, :169:42]
wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59]
wire _sector_hits_T_51 = _sector_hits_T_50; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_53 = _sector_hits_T_52[20:2]; // @[tlb.scala:60:{43,50}]
wire _sector_hits_T_54 = _sector_hits_T_53 == 19'h0; // @[tlb.scala:60:{50,73}]
wire _sector_hits_T_55 = _sector_hits_T_51 & _sector_hits_T_54; // @[package.scala:81:59]
wire _sector_hits_WIRE_7 = _sector_hits_T_55; // @[tlb.scala:59:42, :169:42]
wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_2 = _sector_hits_WIRE_2; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_3 = _sector_hits_WIRE_3; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_4 = _sector_hits_WIRE_4; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_5 = _sector_hits_WIRE_5; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_6 = _sector_hits_WIRE_6; // @[tlb.scala:119:49, :169:42]
wire sector_hits_0_7 = _sector_hits_WIRE_7; // @[tlb.scala:119:49, :169:42]
wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[tlb.scala:60:{43,50}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire _superpage_hits_WIRE_0 = _superpage_hits_T_3; // @[tlb.scala:72:20, :170:45]
wire [20:0] _superpage_hits_T_5 = _superpage_hits_T_4; // @[tlb.scala:60:{43,50}]
wire _superpage_hits_T_6 = _superpage_hits_T_5 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire _superpage_hits_WIRE_1 = _superpage_hits_T_7; // @[tlb.scala:72:20, :170:45]
wire [20:0] _superpage_hits_T_9 = _superpage_hits_T_8; // @[tlb.scala:60:{43,50}]
wire _superpage_hits_T_10 = _superpage_hits_T_9 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire _superpage_hits_WIRE_2 = _superpage_hits_T_11; // @[tlb.scala:72:20, :170:45]
wire [20:0] _superpage_hits_T_13 = _superpage_hits_T_12; // @[tlb.scala:60:{43,50}]
wire _superpage_hits_T_14 = _superpage_hits_T_13 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire _superpage_hits_WIRE_3 = _superpage_hits_T_15; // @[tlb.scala:72:20, :170:45]
wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:119:49, :170:45]
wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:119:49, :170:45]
wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:119:49, :170:45]
wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:119:49, :170:45]
wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_6 = _hitsVec_T_5[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_7 = _hitsVec_T_6 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_11 = _hitsVec_T_10[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_12 = _hitsVec_T_11 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_16 = _hitsVec_T_15[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_17 = _hitsVec_T_16 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_21 = _hitsVec_T_20[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_22 = _hitsVec_T_21 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_26 = _hitsVec_T_25[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_27 = _hitsVec_T_26 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [18:0] _hitsVec_T_36 = _hitsVec_T_35[20:2]; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_37 = _hitsVec_T_36 == 19'h0; // @[tlb.scala:60:{50,73}]
wire [20:0] _hitsVec_T_41 = _hitsVec_T_40; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_42 = _hitsVec_T_41 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire [20:0] _hitsVec_T_46 = _hitsVec_T_45; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_47 = _hitsVec_T_46 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire [20:0] _hitsVec_T_51 = _hitsVec_T_50; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_52 = _hitsVec_T_51 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire [20:0] _hitsVec_T_56 = _hitsVec_T_55; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_57 = _hitsVec_T_56 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:60:{43,50}]
wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[tlb.scala:60:{50,73}, :122:29]
wire _hitsVec_T_63 = _hitsVec_T_62; // @[tlb.scala:60:73, :72:20]
wire [19:0] _ppn_data_T_15; // @[tlb.scala:58:79]
wire _ppn_data_T_14; // @[tlb.scala:58:79]
wire _ppn_data_T_13; // @[tlb.scala:58:79]
wire _ppn_data_T_12; // @[tlb.scala:58:79]
wire _ppn_data_T_11; // @[tlb.scala:58:79]
wire _ppn_data_T_10; // @[tlb.scala:58:79]
wire _ppn_data_T_9; // @[tlb.scala:58:79]
wire _ppn_data_T_8; // @[tlb.scala:58:79]
wire _ppn_data_T_7; // @[tlb.scala:58:79]
wire _ppn_data_T_6; // @[tlb.scala:58:79]
wire _ppn_data_T_5; // @[tlb.scala:58:79]
wire _ppn_data_T_4; // @[tlb.scala:58:79]
wire _ppn_data_T_3; // @[tlb.scala:58:79]
wire _ppn_data_T_2; // @[tlb.scala:58:79]
wire _ppn_data_T_1; // @[tlb.scala:58:79]
assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:58:79]
assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:58:79]
assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:58:79]
assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:58:79]
assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:58:79]
assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:58:79]
assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:58:79]
assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:58:79]
assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:58:79]
assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:58:79]
assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:58:79]
assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:58:79]
assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:58:79]
assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:58:79]
assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_31; // @[tlb.scala:58:79]
wire _ppn_data_T_30; // @[tlb.scala:58:79]
wire _ppn_data_T_29; // @[tlb.scala:58:79]
wire _ppn_data_T_28; // @[tlb.scala:58:79]
wire _ppn_data_T_27; // @[tlb.scala:58:79]
wire _ppn_data_T_26; // @[tlb.scala:58:79]
wire _ppn_data_T_25; // @[tlb.scala:58:79]
wire _ppn_data_T_24; // @[tlb.scala:58:79]
wire _ppn_data_T_23; // @[tlb.scala:58:79]
wire _ppn_data_T_22; // @[tlb.scala:58:79]
wire _ppn_data_T_21; // @[tlb.scala:58:79]
wire _ppn_data_T_20; // @[tlb.scala:58:79]
wire _ppn_data_T_19; // @[tlb.scala:58:79]
wire _ppn_data_T_18; // @[tlb.scala:58:79]
wire _ppn_data_T_17; // @[tlb.scala:58:79]
assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:58:79]
assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:58:79]
assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:58:79]
assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:58:79]
assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:58:79]
assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:58:79]
assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:58:79]
assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:58:79]
assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:58:79]
assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:58:79]
assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:58:79]
assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:58:79]
assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:58:79]
assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:58:79]
assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_47; // @[tlb.scala:58:79]
wire _ppn_data_T_46; // @[tlb.scala:58:79]
wire _ppn_data_T_45; // @[tlb.scala:58:79]
wire _ppn_data_T_44; // @[tlb.scala:58:79]
wire _ppn_data_T_43; // @[tlb.scala:58:79]
wire _ppn_data_T_42; // @[tlb.scala:58:79]
wire _ppn_data_T_41; // @[tlb.scala:58:79]
wire _ppn_data_T_40; // @[tlb.scala:58:79]
wire _ppn_data_T_39; // @[tlb.scala:58:79]
wire _ppn_data_T_38; // @[tlb.scala:58:79]
wire _ppn_data_T_37; // @[tlb.scala:58:79]
wire _ppn_data_T_36; // @[tlb.scala:58:79]
wire _ppn_data_T_35; // @[tlb.scala:58:79]
wire _ppn_data_T_34; // @[tlb.scala:58:79]
wire _ppn_data_T_33; // @[tlb.scala:58:79]
assign _ppn_data_T_33 = _ppn_data_WIRE_5[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_33; // @[tlb.scala:58:79]
assign _ppn_data_T_34 = _ppn_data_WIRE_5[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_c = _ppn_data_T_34; // @[tlb.scala:58:79]
assign _ppn_data_T_35 = _ppn_data_WIRE_5[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_eff = _ppn_data_T_35; // @[tlb.scala:58:79]
assign _ppn_data_T_36 = _ppn_data_WIRE_5[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_paa = _ppn_data_T_36; // @[tlb.scala:58:79]
assign _ppn_data_T_37 = _ppn_data_WIRE_5[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_pal = _ppn_data_T_37; // @[tlb.scala:58:79]
assign _ppn_data_T_38 = _ppn_data_WIRE_5[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_pr = _ppn_data_T_38; // @[tlb.scala:58:79]
assign _ppn_data_T_39 = _ppn_data_WIRE_5[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_px = _ppn_data_T_39; // @[tlb.scala:58:79]
assign _ppn_data_T_40 = _ppn_data_WIRE_5[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_pw = _ppn_data_T_40; // @[tlb.scala:58:79]
assign _ppn_data_T_41 = _ppn_data_WIRE_5[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_sr = _ppn_data_T_41; // @[tlb.scala:58:79]
assign _ppn_data_T_42 = _ppn_data_WIRE_5[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_sx = _ppn_data_T_42; // @[tlb.scala:58:79]
assign _ppn_data_T_43 = _ppn_data_WIRE_5[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_sw = _ppn_data_T_43; // @[tlb.scala:58:79]
assign _ppn_data_T_44 = _ppn_data_WIRE_5[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_ae = _ppn_data_T_44; // @[tlb.scala:58:79]
assign _ppn_data_T_45 = _ppn_data_WIRE_5[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_g = _ppn_data_T_45; // @[tlb.scala:58:79]
assign _ppn_data_T_46 = _ppn_data_WIRE_5[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_4_u = _ppn_data_T_46; // @[tlb.scala:58:79]
assign _ppn_data_T_47 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_47; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_63; // @[tlb.scala:58:79]
wire _ppn_data_T_62; // @[tlb.scala:58:79]
wire _ppn_data_T_61; // @[tlb.scala:58:79]
wire _ppn_data_T_60; // @[tlb.scala:58:79]
wire _ppn_data_T_59; // @[tlb.scala:58:79]
wire _ppn_data_T_58; // @[tlb.scala:58:79]
wire _ppn_data_T_57; // @[tlb.scala:58:79]
wire _ppn_data_T_56; // @[tlb.scala:58:79]
wire _ppn_data_T_55; // @[tlb.scala:58:79]
wire _ppn_data_T_54; // @[tlb.scala:58:79]
wire _ppn_data_T_53; // @[tlb.scala:58:79]
wire _ppn_data_T_52; // @[tlb.scala:58:79]
wire _ppn_data_T_51; // @[tlb.scala:58:79]
wire _ppn_data_T_50; // @[tlb.scala:58:79]
wire _ppn_data_T_49; // @[tlb.scala:58:79]
assign _ppn_data_T_49 = _ppn_data_WIRE_7[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_49; // @[tlb.scala:58:79]
assign _ppn_data_T_50 = _ppn_data_WIRE_7[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_c = _ppn_data_T_50; // @[tlb.scala:58:79]
assign _ppn_data_T_51 = _ppn_data_WIRE_7[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_eff = _ppn_data_T_51; // @[tlb.scala:58:79]
assign _ppn_data_T_52 = _ppn_data_WIRE_7[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_paa = _ppn_data_T_52; // @[tlb.scala:58:79]
assign _ppn_data_T_53 = _ppn_data_WIRE_7[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_pal = _ppn_data_T_53; // @[tlb.scala:58:79]
assign _ppn_data_T_54 = _ppn_data_WIRE_7[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_pr = _ppn_data_T_54; // @[tlb.scala:58:79]
assign _ppn_data_T_55 = _ppn_data_WIRE_7[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_px = _ppn_data_T_55; // @[tlb.scala:58:79]
assign _ppn_data_T_56 = _ppn_data_WIRE_7[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_pw = _ppn_data_T_56; // @[tlb.scala:58:79]
assign _ppn_data_T_57 = _ppn_data_WIRE_7[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_sr = _ppn_data_T_57; // @[tlb.scala:58:79]
assign _ppn_data_T_58 = _ppn_data_WIRE_7[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_sx = _ppn_data_T_58; // @[tlb.scala:58:79]
assign _ppn_data_T_59 = _ppn_data_WIRE_7[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_sw = _ppn_data_T_59; // @[tlb.scala:58:79]
assign _ppn_data_T_60 = _ppn_data_WIRE_7[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_ae = _ppn_data_T_60; // @[tlb.scala:58:79]
assign _ppn_data_T_61 = _ppn_data_WIRE_7[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_g = _ppn_data_T_61; // @[tlb.scala:58:79]
assign _ppn_data_T_62 = _ppn_data_WIRE_7[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_6_u = _ppn_data_T_62; // @[tlb.scala:58:79]
assign _ppn_data_T_63 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_63; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_79; // @[tlb.scala:58:79]
wire _ppn_data_T_78; // @[tlb.scala:58:79]
wire _ppn_data_T_77; // @[tlb.scala:58:79]
wire _ppn_data_T_76; // @[tlb.scala:58:79]
wire _ppn_data_T_75; // @[tlb.scala:58:79]
wire _ppn_data_T_74; // @[tlb.scala:58:79]
wire _ppn_data_T_73; // @[tlb.scala:58:79]
wire _ppn_data_T_72; // @[tlb.scala:58:79]
wire _ppn_data_T_71; // @[tlb.scala:58:79]
wire _ppn_data_T_70; // @[tlb.scala:58:79]
wire _ppn_data_T_69; // @[tlb.scala:58:79]
wire _ppn_data_T_68; // @[tlb.scala:58:79]
wire _ppn_data_T_67; // @[tlb.scala:58:79]
wire _ppn_data_T_66; // @[tlb.scala:58:79]
wire _ppn_data_T_65; // @[tlb.scala:58:79]
assign _ppn_data_T_65 = _ppn_data_WIRE_9[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_65; // @[tlb.scala:58:79]
assign _ppn_data_T_66 = _ppn_data_WIRE_9[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_c = _ppn_data_T_66; // @[tlb.scala:58:79]
assign _ppn_data_T_67 = _ppn_data_WIRE_9[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_eff = _ppn_data_T_67; // @[tlb.scala:58:79]
assign _ppn_data_T_68 = _ppn_data_WIRE_9[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_paa = _ppn_data_T_68; // @[tlb.scala:58:79]
assign _ppn_data_T_69 = _ppn_data_WIRE_9[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_pal = _ppn_data_T_69; // @[tlb.scala:58:79]
assign _ppn_data_T_70 = _ppn_data_WIRE_9[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_pr = _ppn_data_T_70; // @[tlb.scala:58:79]
assign _ppn_data_T_71 = _ppn_data_WIRE_9[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_px = _ppn_data_T_71; // @[tlb.scala:58:79]
assign _ppn_data_T_72 = _ppn_data_WIRE_9[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_pw = _ppn_data_T_72; // @[tlb.scala:58:79]
assign _ppn_data_T_73 = _ppn_data_WIRE_9[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_sr = _ppn_data_T_73; // @[tlb.scala:58:79]
assign _ppn_data_T_74 = _ppn_data_WIRE_9[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_sx = _ppn_data_T_74; // @[tlb.scala:58:79]
assign _ppn_data_T_75 = _ppn_data_WIRE_9[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_sw = _ppn_data_T_75; // @[tlb.scala:58:79]
assign _ppn_data_T_76 = _ppn_data_WIRE_9[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_ae = _ppn_data_T_76; // @[tlb.scala:58:79]
assign _ppn_data_T_77 = _ppn_data_WIRE_9[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_g = _ppn_data_T_77; // @[tlb.scala:58:79]
assign _ppn_data_T_78 = _ppn_data_WIRE_9[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_8_u = _ppn_data_T_78; // @[tlb.scala:58:79]
assign _ppn_data_T_79 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_79; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_95; // @[tlb.scala:58:79]
wire _ppn_data_T_94; // @[tlb.scala:58:79]
wire _ppn_data_T_93; // @[tlb.scala:58:79]
wire _ppn_data_T_92; // @[tlb.scala:58:79]
wire _ppn_data_T_91; // @[tlb.scala:58:79]
wire _ppn_data_T_90; // @[tlb.scala:58:79]
wire _ppn_data_T_89; // @[tlb.scala:58:79]
wire _ppn_data_T_88; // @[tlb.scala:58:79]
wire _ppn_data_T_87; // @[tlb.scala:58:79]
wire _ppn_data_T_86; // @[tlb.scala:58:79]
wire _ppn_data_T_85; // @[tlb.scala:58:79]
wire _ppn_data_T_84; // @[tlb.scala:58:79]
wire _ppn_data_T_83; // @[tlb.scala:58:79]
wire _ppn_data_T_82; // @[tlb.scala:58:79]
wire _ppn_data_T_81; // @[tlb.scala:58:79]
assign _ppn_data_T_81 = _ppn_data_WIRE_11[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_81; // @[tlb.scala:58:79]
assign _ppn_data_T_82 = _ppn_data_WIRE_11[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_c = _ppn_data_T_82; // @[tlb.scala:58:79]
assign _ppn_data_T_83 = _ppn_data_WIRE_11[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_eff = _ppn_data_T_83; // @[tlb.scala:58:79]
assign _ppn_data_T_84 = _ppn_data_WIRE_11[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_paa = _ppn_data_T_84; // @[tlb.scala:58:79]
assign _ppn_data_T_85 = _ppn_data_WIRE_11[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_pal = _ppn_data_T_85; // @[tlb.scala:58:79]
assign _ppn_data_T_86 = _ppn_data_WIRE_11[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_pr = _ppn_data_T_86; // @[tlb.scala:58:79]
assign _ppn_data_T_87 = _ppn_data_WIRE_11[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_px = _ppn_data_T_87; // @[tlb.scala:58:79]
assign _ppn_data_T_88 = _ppn_data_WIRE_11[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_pw = _ppn_data_T_88; // @[tlb.scala:58:79]
assign _ppn_data_T_89 = _ppn_data_WIRE_11[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_sr = _ppn_data_T_89; // @[tlb.scala:58:79]
assign _ppn_data_T_90 = _ppn_data_WIRE_11[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_sx = _ppn_data_T_90; // @[tlb.scala:58:79]
assign _ppn_data_T_91 = _ppn_data_WIRE_11[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_sw = _ppn_data_T_91; // @[tlb.scala:58:79]
assign _ppn_data_T_92 = _ppn_data_WIRE_11[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_ae = _ppn_data_T_92; // @[tlb.scala:58:79]
assign _ppn_data_T_93 = _ppn_data_WIRE_11[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_g = _ppn_data_T_93; // @[tlb.scala:58:79]
assign _ppn_data_T_94 = _ppn_data_WIRE_11[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_10_u = _ppn_data_T_94; // @[tlb.scala:58:79]
assign _ppn_data_T_95 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_95; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_111; // @[tlb.scala:58:79]
wire _ppn_data_T_110; // @[tlb.scala:58:79]
wire _ppn_data_T_109; // @[tlb.scala:58:79]
wire _ppn_data_T_108; // @[tlb.scala:58:79]
wire _ppn_data_T_107; // @[tlb.scala:58:79]
wire _ppn_data_T_106; // @[tlb.scala:58:79]
wire _ppn_data_T_105; // @[tlb.scala:58:79]
wire _ppn_data_T_104; // @[tlb.scala:58:79]
wire _ppn_data_T_103; // @[tlb.scala:58:79]
wire _ppn_data_T_102; // @[tlb.scala:58:79]
wire _ppn_data_T_101; // @[tlb.scala:58:79]
wire _ppn_data_T_100; // @[tlb.scala:58:79]
wire _ppn_data_T_99; // @[tlb.scala:58:79]
wire _ppn_data_T_98; // @[tlb.scala:58:79]
wire _ppn_data_T_97; // @[tlb.scala:58:79]
assign _ppn_data_T_97 = _ppn_data_WIRE_13[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_97; // @[tlb.scala:58:79]
assign _ppn_data_T_98 = _ppn_data_WIRE_13[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_c = _ppn_data_T_98; // @[tlb.scala:58:79]
assign _ppn_data_T_99 = _ppn_data_WIRE_13[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_eff = _ppn_data_T_99; // @[tlb.scala:58:79]
assign _ppn_data_T_100 = _ppn_data_WIRE_13[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_paa = _ppn_data_T_100; // @[tlb.scala:58:79]
assign _ppn_data_T_101 = _ppn_data_WIRE_13[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_pal = _ppn_data_T_101; // @[tlb.scala:58:79]
assign _ppn_data_T_102 = _ppn_data_WIRE_13[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_pr = _ppn_data_T_102; // @[tlb.scala:58:79]
assign _ppn_data_T_103 = _ppn_data_WIRE_13[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_px = _ppn_data_T_103; // @[tlb.scala:58:79]
assign _ppn_data_T_104 = _ppn_data_WIRE_13[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_pw = _ppn_data_T_104; // @[tlb.scala:58:79]
assign _ppn_data_T_105 = _ppn_data_WIRE_13[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_sr = _ppn_data_T_105; // @[tlb.scala:58:79]
assign _ppn_data_T_106 = _ppn_data_WIRE_13[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_sx = _ppn_data_T_106; // @[tlb.scala:58:79]
assign _ppn_data_T_107 = _ppn_data_WIRE_13[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_sw = _ppn_data_T_107; // @[tlb.scala:58:79]
assign _ppn_data_T_108 = _ppn_data_WIRE_13[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_ae = _ppn_data_T_108; // @[tlb.scala:58:79]
assign _ppn_data_T_109 = _ppn_data_WIRE_13[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_g = _ppn_data_T_109; // @[tlb.scala:58:79]
assign _ppn_data_T_110 = _ppn_data_WIRE_13[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_12_u = _ppn_data_T_110; // @[tlb.scala:58:79]
assign _ppn_data_T_111 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_111; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_127; // @[tlb.scala:58:79]
wire _ppn_data_T_126; // @[tlb.scala:58:79]
wire _ppn_data_T_125; // @[tlb.scala:58:79]
wire _ppn_data_T_124; // @[tlb.scala:58:79]
wire _ppn_data_T_123; // @[tlb.scala:58:79]
wire _ppn_data_T_122; // @[tlb.scala:58:79]
wire _ppn_data_T_121; // @[tlb.scala:58:79]
wire _ppn_data_T_120; // @[tlb.scala:58:79]
wire _ppn_data_T_119; // @[tlb.scala:58:79]
wire _ppn_data_T_118; // @[tlb.scala:58:79]
wire _ppn_data_T_117; // @[tlb.scala:58:79]
wire _ppn_data_T_116; // @[tlb.scala:58:79]
wire _ppn_data_T_115; // @[tlb.scala:58:79]
wire _ppn_data_T_114; // @[tlb.scala:58:79]
wire _ppn_data_T_113; // @[tlb.scala:58:79]
assign _ppn_data_T_113 = _ppn_data_WIRE_15[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_fragmented_superpage = _ppn_data_T_113; // @[tlb.scala:58:79]
assign _ppn_data_T_114 = _ppn_data_WIRE_15[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_c = _ppn_data_T_114; // @[tlb.scala:58:79]
assign _ppn_data_T_115 = _ppn_data_WIRE_15[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_eff = _ppn_data_T_115; // @[tlb.scala:58:79]
assign _ppn_data_T_116 = _ppn_data_WIRE_15[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_paa = _ppn_data_T_116; // @[tlb.scala:58:79]
assign _ppn_data_T_117 = _ppn_data_WIRE_15[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_pal = _ppn_data_T_117; // @[tlb.scala:58:79]
assign _ppn_data_T_118 = _ppn_data_WIRE_15[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_pr = _ppn_data_T_118; // @[tlb.scala:58:79]
assign _ppn_data_T_119 = _ppn_data_WIRE_15[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_px = _ppn_data_T_119; // @[tlb.scala:58:79]
assign _ppn_data_T_120 = _ppn_data_WIRE_15[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_pw = _ppn_data_T_120; // @[tlb.scala:58:79]
assign _ppn_data_T_121 = _ppn_data_WIRE_15[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_sr = _ppn_data_T_121; // @[tlb.scala:58:79]
assign _ppn_data_T_122 = _ppn_data_WIRE_15[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_sx = _ppn_data_T_122; // @[tlb.scala:58:79]
assign _ppn_data_T_123 = _ppn_data_WIRE_15[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_sw = _ppn_data_T_123; // @[tlb.scala:58:79]
assign _ppn_data_T_124 = _ppn_data_WIRE_15[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_ae = _ppn_data_T_124; // @[tlb.scala:58:79]
assign _ppn_data_T_125 = _ppn_data_WIRE_15[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_g = _ppn_data_T_125; // @[tlb.scala:58:79]
assign _ppn_data_T_126 = _ppn_data_WIRE_15[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_14_u = _ppn_data_T_126; // @[tlb.scala:58:79]
assign _ppn_data_T_127 = _ppn_data_WIRE_15[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_14_ppn = _ppn_data_T_127; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_142; // @[tlb.scala:58:79]
wire _ppn_data_T_141; // @[tlb.scala:58:79]
wire _ppn_data_T_140; // @[tlb.scala:58:79]
wire _ppn_data_T_139; // @[tlb.scala:58:79]
wire _ppn_data_T_138; // @[tlb.scala:58:79]
wire _ppn_data_T_137; // @[tlb.scala:58:79]
wire _ppn_data_T_136; // @[tlb.scala:58:79]
wire _ppn_data_T_135; // @[tlb.scala:58:79]
wire _ppn_data_T_134; // @[tlb.scala:58:79]
wire _ppn_data_T_133; // @[tlb.scala:58:79]
wire _ppn_data_T_132; // @[tlb.scala:58:79]
wire _ppn_data_T_131; // @[tlb.scala:58:79]
wire _ppn_data_T_130; // @[tlb.scala:58:79]
wire _ppn_data_T_129; // @[tlb.scala:58:79]
wire _ppn_data_T_128; // @[tlb.scala:58:79]
assign _ppn_data_T_128 = _ppn_data_WIRE_17[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_fragmented_superpage = _ppn_data_T_128; // @[tlb.scala:58:79]
assign _ppn_data_T_129 = _ppn_data_WIRE_17[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_c = _ppn_data_T_129; // @[tlb.scala:58:79]
assign _ppn_data_T_130 = _ppn_data_WIRE_17[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_eff = _ppn_data_T_130; // @[tlb.scala:58:79]
assign _ppn_data_T_131 = _ppn_data_WIRE_17[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_paa = _ppn_data_T_131; // @[tlb.scala:58:79]
assign _ppn_data_T_132 = _ppn_data_WIRE_17[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_pal = _ppn_data_T_132; // @[tlb.scala:58:79]
assign _ppn_data_T_133 = _ppn_data_WIRE_17[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_pr = _ppn_data_T_133; // @[tlb.scala:58:79]
assign _ppn_data_T_134 = _ppn_data_WIRE_17[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_px = _ppn_data_T_134; // @[tlb.scala:58:79]
assign _ppn_data_T_135 = _ppn_data_WIRE_17[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_pw = _ppn_data_T_135; // @[tlb.scala:58:79]
assign _ppn_data_T_136 = _ppn_data_WIRE_17[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_sr = _ppn_data_T_136; // @[tlb.scala:58:79]
assign _ppn_data_T_137 = _ppn_data_WIRE_17[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_sx = _ppn_data_T_137; // @[tlb.scala:58:79]
assign _ppn_data_T_138 = _ppn_data_WIRE_17[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_sw = _ppn_data_T_138; // @[tlb.scala:58:79]
assign _ppn_data_T_139 = _ppn_data_WIRE_17[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_ae = _ppn_data_T_139; // @[tlb.scala:58:79]
assign _ppn_data_T_140 = _ppn_data_WIRE_17[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_g = _ppn_data_T_140; // @[tlb.scala:58:79]
assign _ppn_data_T_141 = _ppn_data_WIRE_17[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_16_u = _ppn_data_T_141; // @[tlb.scala:58:79]
assign _ppn_data_T_142 = _ppn_data_WIRE_17[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_16_ppn = _ppn_data_T_142; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_157; // @[tlb.scala:58:79]
wire _ppn_data_T_156; // @[tlb.scala:58:79]
wire _ppn_data_T_155; // @[tlb.scala:58:79]
wire _ppn_data_T_154; // @[tlb.scala:58:79]
wire _ppn_data_T_153; // @[tlb.scala:58:79]
wire _ppn_data_T_152; // @[tlb.scala:58:79]
wire _ppn_data_T_151; // @[tlb.scala:58:79]
wire _ppn_data_T_150; // @[tlb.scala:58:79]
wire _ppn_data_T_149; // @[tlb.scala:58:79]
wire _ppn_data_T_148; // @[tlb.scala:58:79]
wire _ppn_data_T_147; // @[tlb.scala:58:79]
wire _ppn_data_T_146; // @[tlb.scala:58:79]
wire _ppn_data_T_145; // @[tlb.scala:58:79]
wire _ppn_data_T_144; // @[tlb.scala:58:79]
wire _ppn_data_T_143; // @[tlb.scala:58:79]
assign _ppn_data_T_143 = _ppn_data_WIRE_19[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_fragmented_superpage = _ppn_data_T_143; // @[tlb.scala:58:79]
assign _ppn_data_T_144 = _ppn_data_WIRE_19[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_c = _ppn_data_T_144; // @[tlb.scala:58:79]
assign _ppn_data_T_145 = _ppn_data_WIRE_19[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_eff = _ppn_data_T_145; // @[tlb.scala:58:79]
assign _ppn_data_T_146 = _ppn_data_WIRE_19[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_paa = _ppn_data_T_146; // @[tlb.scala:58:79]
assign _ppn_data_T_147 = _ppn_data_WIRE_19[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_pal = _ppn_data_T_147; // @[tlb.scala:58:79]
assign _ppn_data_T_148 = _ppn_data_WIRE_19[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_pr = _ppn_data_T_148; // @[tlb.scala:58:79]
assign _ppn_data_T_149 = _ppn_data_WIRE_19[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_px = _ppn_data_T_149; // @[tlb.scala:58:79]
assign _ppn_data_T_150 = _ppn_data_WIRE_19[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_pw = _ppn_data_T_150; // @[tlb.scala:58:79]
assign _ppn_data_T_151 = _ppn_data_WIRE_19[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_sr = _ppn_data_T_151; // @[tlb.scala:58:79]
assign _ppn_data_T_152 = _ppn_data_WIRE_19[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_sx = _ppn_data_T_152; // @[tlb.scala:58:79]
assign _ppn_data_T_153 = _ppn_data_WIRE_19[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_sw = _ppn_data_T_153; // @[tlb.scala:58:79]
assign _ppn_data_T_154 = _ppn_data_WIRE_19[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_ae = _ppn_data_T_154; // @[tlb.scala:58:79]
assign _ppn_data_T_155 = _ppn_data_WIRE_19[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_g = _ppn_data_T_155; // @[tlb.scala:58:79]
assign _ppn_data_T_156 = _ppn_data_WIRE_19[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_18_u = _ppn_data_T_156; // @[tlb.scala:58:79]
assign _ppn_data_T_157 = _ppn_data_WIRE_19[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_18_ppn = _ppn_data_T_157; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_172; // @[tlb.scala:58:79]
wire _ppn_data_T_171; // @[tlb.scala:58:79]
wire _ppn_data_T_170; // @[tlb.scala:58:79]
wire _ppn_data_T_169; // @[tlb.scala:58:79]
wire _ppn_data_T_168; // @[tlb.scala:58:79]
wire _ppn_data_T_167; // @[tlb.scala:58:79]
wire _ppn_data_T_166; // @[tlb.scala:58:79]
wire _ppn_data_T_165; // @[tlb.scala:58:79]
wire _ppn_data_T_164; // @[tlb.scala:58:79]
wire _ppn_data_T_163; // @[tlb.scala:58:79]
wire _ppn_data_T_162; // @[tlb.scala:58:79]
wire _ppn_data_T_161; // @[tlb.scala:58:79]
wire _ppn_data_T_160; // @[tlb.scala:58:79]
wire _ppn_data_T_159; // @[tlb.scala:58:79]
wire _ppn_data_T_158; // @[tlb.scala:58:79]
assign _ppn_data_T_158 = _ppn_data_WIRE_21[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_fragmented_superpage = _ppn_data_T_158; // @[tlb.scala:58:79]
assign _ppn_data_T_159 = _ppn_data_WIRE_21[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_c = _ppn_data_T_159; // @[tlb.scala:58:79]
assign _ppn_data_T_160 = _ppn_data_WIRE_21[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_eff = _ppn_data_T_160; // @[tlb.scala:58:79]
assign _ppn_data_T_161 = _ppn_data_WIRE_21[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_paa = _ppn_data_T_161; // @[tlb.scala:58:79]
assign _ppn_data_T_162 = _ppn_data_WIRE_21[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_pal = _ppn_data_T_162; // @[tlb.scala:58:79]
assign _ppn_data_T_163 = _ppn_data_WIRE_21[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_pr = _ppn_data_T_163; // @[tlb.scala:58:79]
assign _ppn_data_T_164 = _ppn_data_WIRE_21[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_px = _ppn_data_T_164; // @[tlb.scala:58:79]
assign _ppn_data_T_165 = _ppn_data_WIRE_21[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_pw = _ppn_data_T_165; // @[tlb.scala:58:79]
assign _ppn_data_T_166 = _ppn_data_WIRE_21[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_sr = _ppn_data_T_166; // @[tlb.scala:58:79]
assign _ppn_data_T_167 = _ppn_data_WIRE_21[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_sx = _ppn_data_T_167; // @[tlb.scala:58:79]
assign _ppn_data_T_168 = _ppn_data_WIRE_21[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_sw = _ppn_data_T_168; // @[tlb.scala:58:79]
assign _ppn_data_T_169 = _ppn_data_WIRE_21[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_ae = _ppn_data_T_169; // @[tlb.scala:58:79]
assign _ppn_data_T_170 = _ppn_data_WIRE_21[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_g = _ppn_data_T_170; // @[tlb.scala:58:79]
assign _ppn_data_T_171 = _ppn_data_WIRE_21[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_20_u = _ppn_data_T_171; // @[tlb.scala:58:79]
assign _ppn_data_T_172 = _ppn_data_WIRE_21[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_20_ppn = _ppn_data_T_172; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_187; // @[tlb.scala:58:79]
wire _ppn_data_T_186; // @[tlb.scala:58:79]
wire _ppn_data_T_185; // @[tlb.scala:58:79]
wire _ppn_data_T_184; // @[tlb.scala:58:79]
wire _ppn_data_T_183; // @[tlb.scala:58:79]
wire _ppn_data_T_182; // @[tlb.scala:58:79]
wire _ppn_data_T_181; // @[tlb.scala:58:79]
wire _ppn_data_T_180; // @[tlb.scala:58:79]
wire _ppn_data_T_179; // @[tlb.scala:58:79]
wire _ppn_data_T_178; // @[tlb.scala:58:79]
wire _ppn_data_T_177; // @[tlb.scala:58:79]
wire _ppn_data_T_176; // @[tlb.scala:58:79]
wire _ppn_data_T_175; // @[tlb.scala:58:79]
wire _ppn_data_T_174; // @[tlb.scala:58:79]
wire _ppn_data_T_173; // @[tlb.scala:58:79]
assign _ppn_data_T_173 = _ppn_data_WIRE_23[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_fragmented_superpage = _ppn_data_T_173; // @[tlb.scala:58:79]
assign _ppn_data_T_174 = _ppn_data_WIRE_23[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_c = _ppn_data_T_174; // @[tlb.scala:58:79]
assign _ppn_data_T_175 = _ppn_data_WIRE_23[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_eff = _ppn_data_T_175; // @[tlb.scala:58:79]
assign _ppn_data_T_176 = _ppn_data_WIRE_23[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_paa = _ppn_data_T_176; // @[tlb.scala:58:79]
assign _ppn_data_T_177 = _ppn_data_WIRE_23[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_pal = _ppn_data_T_177; // @[tlb.scala:58:79]
assign _ppn_data_T_178 = _ppn_data_WIRE_23[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_pr = _ppn_data_T_178; // @[tlb.scala:58:79]
assign _ppn_data_T_179 = _ppn_data_WIRE_23[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_px = _ppn_data_T_179; // @[tlb.scala:58:79]
assign _ppn_data_T_180 = _ppn_data_WIRE_23[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_pw = _ppn_data_T_180; // @[tlb.scala:58:79]
assign _ppn_data_T_181 = _ppn_data_WIRE_23[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_sr = _ppn_data_T_181; // @[tlb.scala:58:79]
assign _ppn_data_T_182 = _ppn_data_WIRE_23[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_sx = _ppn_data_T_182; // @[tlb.scala:58:79]
assign _ppn_data_T_183 = _ppn_data_WIRE_23[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_sw = _ppn_data_T_183; // @[tlb.scala:58:79]
assign _ppn_data_T_184 = _ppn_data_WIRE_23[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_ae = _ppn_data_T_184; // @[tlb.scala:58:79]
assign _ppn_data_T_185 = _ppn_data_WIRE_23[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_g = _ppn_data_T_185; // @[tlb.scala:58:79]
assign _ppn_data_T_186 = _ppn_data_WIRE_23[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_22_u = _ppn_data_T_186; // @[tlb.scala:58:79]
assign _ppn_data_T_187 = _ppn_data_WIRE_23[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_22_ppn = _ppn_data_T_187; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_T_202; // @[tlb.scala:58:79]
wire _ppn_data_T_201; // @[tlb.scala:58:79]
wire _ppn_data_T_200; // @[tlb.scala:58:79]
wire _ppn_data_T_199; // @[tlb.scala:58:79]
wire _ppn_data_T_198; // @[tlb.scala:58:79]
wire _ppn_data_T_197; // @[tlb.scala:58:79]
wire _ppn_data_T_196; // @[tlb.scala:58:79]
wire _ppn_data_T_195; // @[tlb.scala:58:79]
wire _ppn_data_T_194; // @[tlb.scala:58:79]
wire _ppn_data_T_193; // @[tlb.scala:58:79]
wire _ppn_data_T_192; // @[tlb.scala:58:79]
wire _ppn_data_T_191; // @[tlb.scala:58:79]
wire _ppn_data_T_190; // @[tlb.scala:58:79]
wire _ppn_data_T_189; // @[tlb.scala:58:79]
wire _ppn_data_T_188; // @[tlb.scala:58:79]
assign _ppn_data_T_188 = _ppn_data_WIRE_25[0]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_fragmented_superpage = _ppn_data_T_188; // @[tlb.scala:58:79]
assign _ppn_data_T_189 = _ppn_data_WIRE_25[1]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_c = _ppn_data_T_189; // @[tlb.scala:58:79]
assign _ppn_data_T_190 = _ppn_data_WIRE_25[2]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_eff = _ppn_data_T_190; // @[tlb.scala:58:79]
assign _ppn_data_T_191 = _ppn_data_WIRE_25[3]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_paa = _ppn_data_T_191; // @[tlb.scala:58:79]
assign _ppn_data_T_192 = _ppn_data_WIRE_25[4]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_pal = _ppn_data_T_192; // @[tlb.scala:58:79]
assign _ppn_data_T_193 = _ppn_data_WIRE_25[5]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_pr = _ppn_data_T_193; // @[tlb.scala:58:79]
assign _ppn_data_T_194 = _ppn_data_WIRE_25[6]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_px = _ppn_data_T_194; // @[tlb.scala:58:79]
assign _ppn_data_T_195 = _ppn_data_WIRE_25[7]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_pw = _ppn_data_T_195; // @[tlb.scala:58:79]
assign _ppn_data_T_196 = _ppn_data_WIRE_25[8]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_sr = _ppn_data_T_196; // @[tlb.scala:58:79]
assign _ppn_data_T_197 = _ppn_data_WIRE_25[9]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_sx = _ppn_data_T_197; // @[tlb.scala:58:79]
assign _ppn_data_T_198 = _ppn_data_WIRE_25[10]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_sw = _ppn_data_T_198; // @[tlb.scala:58:79]
assign _ppn_data_T_199 = _ppn_data_WIRE_25[11]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_ae = _ppn_data_T_199; // @[tlb.scala:58:79]
assign _ppn_data_T_200 = _ppn_data_WIRE_25[12]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_g = _ppn_data_T_200; // @[tlb.scala:58:79]
assign _ppn_data_T_201 = _ppn_data_WIRE_25[13]; // @[tlb.scala:58:79]
wire _ppn_data_WIRE_24_u = _ppn_data_T_201; // @[tlb.scala:58:79]
assign _ppn_data_T_202 = _ppn_data_WIRE_25[33:14]; // @[tlb.scala:58:79]
wire [19:0] _ppn_data_WIRE_24_ppn = _ppn_data_T_202; // @[tlb.scala:58:79]
wire [19:0] _ppn_T_1 = vpn_0[19:0]; // @[tlb.scala:119:49, :174:103]
wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73]
wire [19:0] _ppn_WIRE = _ppn_T_28; // @[Mux.scala:30:73]
wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73]
wire [1:0] _GEN_4 = {newEntry_eff, newEntry_c}; // @[tlb.scala:95:26, :179:24]
wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:95:26]
assign special_entry_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:95:26]
assign superpage_entries_0_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:95:26]
assign superpage_entries_1_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:95:26]
assign superpage_entries_2_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:95:26]
assign superpage_entries_3_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_0_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_1_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_2_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_2_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_3_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_3_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_4_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_4_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_5_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_5_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_6_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_6_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_7_data_lo_lo_hi; // @[tlb.scala:95:26]
assign sectored_entries_7_data_lo_lo_hi = _GEN_4; // @[tlb.scala:95:26]
wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [1:0] _GEN_5 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:95:26, :179:24]
wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:95:26]
assign special_entry_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:95:26]
assign superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:95:26]
assign superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:95:26]
assign superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:95:26]
assign superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_0_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_1_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_2_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_2_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_3_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_3_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_4_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_4_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_5_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_5_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_6_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_6_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_7_data_lo_hi_lo; // @[tlb.scala:95:26]
assign sectored_entries_7_data_lo_hi_lo = _GEN_5; // @[tlb.scala:95:26]
wire [1:0] _GEN_6 = {newEntry_px, newEntry_pr}; // @[tlb.scala:95:26, :179:24]
wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:95:26]
assign special_entry_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_0_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_1_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_2_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_3_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_0_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_1_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_2_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_2_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_3_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_3_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_4_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_4_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_5_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_5_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_6_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_6_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_7_data_lo_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_7_data_lo_hi_hi = _GEN_6; // @[tlb.scala:95:26]
wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:95:26]
wire [1:0] _GEN_7 = {1'h1, newEntry_pw}; // @[tlb.scala:95:26, :179:24]
wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:95:26]
assign special_entry_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:95:26]
assign superpage_entries_0_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:95:26]
assign superpage_entries_1_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:95:26]
assign superpage_entries_2_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:95:26]
assign superpage_entries_3_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_0_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_1_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_2_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_2_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_3_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_3_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_4_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_4_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_5_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_5_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_6_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_6_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [1:0] sectored_entries_7_data_hi_lo_lo; // @[tlb.scala:95:26]
assign sectored_entries_7_data_hi_lo_lo = _GEN_7; // @[tlb.scala:95:26]
wire [3:0] special_entry_data_0_hi_lo = {2'h2, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:95:26]
wire [20:0] _GEN_8 = {newEntry_ppn, 1'h1}; // @[tlb.scala:95:26, :179:24]
wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:95:26]
assign special_entry_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_0_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_1_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_2_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:95:26]
assign superpage_entries_3_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_0_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_1_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_2_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_2_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_3_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_3_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_4_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_4_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_5_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_5_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_6_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_6_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [20:0] sectored_entries_7_data_hi_hi_hi; // @[tlb.scala:95:26]
assign sectored_entries_7_data_hi_hi_hi = _GEN_8; // @[tlb.scala:95:26]
wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:95:26]
wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_0_data_0_hi_lo = {2'h2, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:95:26]
wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_1_data_0_hi_lo = {2'h2, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:95:26]
wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_2_data_0_hi_lo = {2'h2, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:95:26]
wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] superpage_entries_3_data_0_hi_lo = {2'h2, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_0_data_hi_lo = {2'h2, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_1_data_hi_lo = {2'h2, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_2_data_lo_lo = {sectored_entries_2_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_2_data_lo_hi = {sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_2_data_lo = {sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_2_data_hi_lo = {2'h2, sectored_entries_2_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_2_data_hi_hi = {sectored_entries_2_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_2_data_hi = {sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_2_data_T = {sectored_entries_2_data_hi, sectored_entries_2_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_3_data_lo_lo = {sectored_entries_3_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_3_data_lo_hi = {sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_3_data_lo = {sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_3_data_hi_lo = {2'h2, sectored_entries_3_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_3_data_hi_hi = {sectored_entries_3_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_3_data_hi = {sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_3_data_T = {sectored_entries_3_data_hi, sectored_entries_3_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_4_data_lo_lo = {sectored_entries_4_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_4_data_lo_hi = {sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_4_data_lo = {sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_4_data_hi_lo = {2'h2, sectored_entries_4_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_4_data_hi_hi = {sectored_entries_4_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_4_data_hi = {sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_4_data_T = {sectored_entries_4_data_hi, sectored_entries_4_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_5_data_lo_lo = {sectored_entries_5_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_5_data_lo_hi = {sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_5_data_lo = {sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_5_data_hi_lo = {2'h2, sectored_entries_5_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_5_data_hi_hi = {sectored_entries_5_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_5_data_hi = {sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_5_data_T = {sectored_entries_5_data_hi, sectored_entries_5_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_6_data_lo_lo = {sectored_entries_6_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_6_data_lo_hi = {sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_6_data_lo = {sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_6_data_hi_lo = {2'h2, sectored_entries_6_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_6_data_hi_hi = {sectored_entries_6_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_6_data_hi = {sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_6_data_T = {sectored_entries_6_data_hi, sectored_entries_6_data_lo}; // @[tlb.scala:95:26]
wire [2:0] sectored_entries_7_data_lo_lo = {sectored_entries_7_data_lo_lo_hi, 1'h0}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_7_data_lo_hi = {sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo}; // @[tlb.scala:95:26]
wire [6:0] sectored_entries_7_data_lo = {sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo}; // @[tlb.scala:95:26]
wire [3:0] sectored_entries_7_data_hi_lo = {2'h2, sectored_entries_7_data_hi_lo_lo}; // @[tlb.scala:95:26]
wire [22:0] sectored_entries_7_data_hi_hi = {sectored_entries_7_data_hi_hi_hi, 2'h0}; // @[tlb.scala:95:26]
wire [26:0] sectored_entries_7_data_hi = {sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo}; // @[tlb.scala:95:26]
wire [33:0] _sectored_entries_7_data_T = {sectored_entries_7_data_hi, sectored_entries_7_data_lo}; // @[tlb.scala:95:26]
wire [19:0] _entries_T_15; // @[tlb.scala:58:79]
wire _entries_T_14; // @[tlb.scala:58:79]
wire _entries_T_13; // @[tlb.scala:58:79]
wire _entries_T_12; // @[tlb.scala:58:79]
wire _entries_T_11; // @[tlb.scala:58:79]
wire _entries_T_10; // @[tlb.scala:58:79]
wire _entries_T_9; // @[tlb.scala:58:79]
wire _entries_T_8; // @[tlb.scala:58:79]
wire _entries_T_7; // @[tlb.scala:58:79]
wire _entries_T_6; // @[tlb.scala:58:79]
wire _entries_T_5; // @[tlb.scala:58:79]
wire _entries_T_4; // @[tlb.scala:58:79]
wire _entries_T_3; // @[tlb.scala:58:79]
wire _entries_T_2; // @[tlb.scala:58:79]
wire _entries_T_1; // @[tlb.scala:58:79]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:58:79]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:58:79]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:58:79]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:58:79]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:58:79]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:58:79]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:58:79]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:58:79]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:58:79]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:58:79]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:58:79]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:58:79]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:58:79]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:58:79]
assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:58:79]
wire [19:0] _entries_T_31; // @[tlb.scala:58:79]
wire _entries_T_30; // @[tlb.scala:58:79]
wire _entries_T_29; // @[tlb.scala:58:79]
wire _entries_T_28; // @[tlb.scala:58:79]
wire _entries_T_27; // @[tlb.scala:58:79]
wire _entries_T_26; // @[tlb.scala:58:79]
wire _entries_T_25; // @[tlb.scala:58:79]
wire _entries_T_24; // @[tlb.scala:58:79]
wire _entries_T_23; // @[tlb.scala:58:79]
wire _entries_T_22; // @[tlb.scala:58:79]
wire _entries_T_21; // @[tlb.scala:58:79]
wire _entries_T_20; // @[tlb.scala:58:79]
wire _entries_T_19; // @[tlb.scala:58:79]
wire _entries_T_18; // @[tlb.scala:58:79]
wire _entries_T_17; // @[tlb.scala:58:79]
assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:58:79]
assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:58:79]
assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:58:79]
assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:58:79]
assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:58:79]
assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:58:79]
assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:58:79]
assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:58:79]
assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:58:79]
assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:58:79]
assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:58:79]
assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:58:79]
assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:58:79]
assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:58:79]
assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:58:79]
wire [19:0] _entries_T_47; // @[tlb.scala:58:79]
wire _entries_T_46; // @[tlb.scala:58:79]
wire _entries_T_45; // @[tlb.scala:58:79]
wire _entries_T_44; // @[tlb.scala:58:79]
wire _entries_T_43; // @[tlb.scala:58:79]
wire _entries_T_42; // @[tlb.scala:58:79]
wire _entries_T_41; // @[tlb.scala:58:79]
wire _entries_T_40; // @[tlb.scala:58:79]
wire _entries_T_39; // @[tlb.scala:58:79]
wire _entries_T_38; // @[tlb.scala:58:79]
wire _entries_T_37; // @[tlb.scala:58:79]
wire _entries_T_36; // @[tlb.scala:58:79]
wire _entries_T_35; // @[tlb.scala:58:79]
wire _entries_T_34; // @[tlb.scala:58:79]
wire _entries_T_33; // @[tlb.scala:58:79]
assign _entries_T_33 = _entries_WIRE_5[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_33; // @[tlb.scala:58:79]
assign _entries_T_34 = _entries_WIRE_5[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_c = _entries_T_34; // @[tlb.scala:58:79]
assign _entries_T_35 = _entries_WIRE_5[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_eff = _entries_T_35; // @[tlb.scala:58:79]
assign _entries_T_36 = _entries_WIRE_5[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_paa = _entries_T_36; // @[tlb.scala:58:79]
assign _entries_T_37 = _entries_WIRE_5[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_pal = _entries_T_37; // @[tlb.scala:58:79]
assign _entries_T_38 = _entries_WIRE_5[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_pr = _entries_T_38; // @[tlb.scala:58:79]
assign _entries_T_39 = _entries_WIRE_5[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_px = _entries_T_39; // @[tlb.scala:58:79]
assign _entries_T_40 = _entries_WIRE_5[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_pw = _entries_T_40; // @[tlb.scala:58:79]
assign _entries_T_41 = _entries_WIRE_5[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_sr = _entries_T_41; // @[tlb.scala:58:79]
assign _entries_T_42 = _entries_WIRE_5[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_sx = _entries_T_42; // @[tlb.scala:58:79]
assign _entries_T_43 = _entries_WIRE_5[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_sw = _entries_T_43; // @[tlb.scala:58:79]
assign _entries_T_44 = _entries_WIRE_5[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_ae = _entries_T_44; // @[tlb.scala:58:79]
assign _entries_T_45 = _entries_WIRE_5[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_g = _entries_T_45; // @[tlb.scala:58:79]
assign _entries_T_46 = _entries_WIRE_5[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_4_u = _entries_T_46; // @[tlb.scala:58:79]
assign _entries_T_47 = _entries_WIRE_5[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_47; // @[tlb.scala:58:79]
wire [19:0] _entries_T_63; // @[tlb.scala:58:79]
wire _entries_T_62; // @[tlb.scala:58:79]
wire _entries_T_61; // @[tlb.scala:58:79]
wire _entries_T_60; // @[tlb.scala:58:79]
wire _entries_T_59; // @[tlb.scala:58:79]
wire _entries_T_58; // @[tlb.scala:58:79]
wire _entries_T_57; // @[tlb.scala:58:79]
wire _entries_T_56; // @[tlb.scala:58:79]
wire _entries_T_55; // @[tlb.scala:58:79]
wire _entries_T_54; // @[tlb.scala:58:79]
wire _entries_T_53; // @[tlb.scala:58:79]
wire _entries_T_52; // @[tlb.scala:58:79]
wire _entries_T_51; // @[tlb.scala:58:79]
wire _entries_T_50; // @[tlb.scala:58:79]
wire _entries_T_49; // @[tlb.scala:58:79]
assign _entries_T_49 = _entries_WIRE_7[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_49; // @[tlb.scala:58:79]
assign _entries_T_50 = _entries_WIRE_7[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_c = _entries_T_50; // @[tlb.scala:58:79]
assign _entries_T_51 = _entries_WIRE_7[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_eff = _entries_T_51; // @[tlb.scala:58:79]
assign _entries_T_52 = _entries_WIRE_7[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_paa = _entries_T_52; // @[tlb.scala:58:79]
assign _entries_T_53 = _entries_WIRE_7[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_pal = _entries_T_53; // @[tlb.scala:58:79]
assign _entries_T_54 = _entries_WIRE_7[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_pr = _entries_T_54; // @[tlb.scala:58:79]
assign _entries_T_55 = _entries_WIRE_7[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_px = _entries_T_55; // @[tlb.scala:58:79]
assign _entries_T_56 = _entries_WIRE_7[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_pw = _entries_T_56; // @[tlb.scala:58:79]
assign _entries_T_57 = _entries_WIRE_7[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_sr = _entries_T_57; // @[tlb.scala:58:79]
assign _entries_T_58 = _entries_WIRE_7[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_sx = _entries_T_58; // @[tlb.scala:58:79]
assign _entries_T_59 = _entries_WIRE_7[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_sw = _entries_T_59; // @[tlb.scala:58:79]
assign _entries_T_60 = _entries_WIRE_7[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_ae = _entries_T_60; // @[tlb.scala:58:79]
assign _entries_T_61 = _entries_WIRE_7[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_g = _entries_T_61; // @[tlb.scala:58:79]
assign _entries_T_62 = _entries_WIRE_7[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_6_u = _entries_T_62; // @[tlb.scala:58:79]
assign _entries_T_63 = _entries_WIRE_7[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_63; // @[tlb.scala:58:79]
wire [19:0] _entries_T_79; // @[tlb.scala:58:79]
wire _entries_T_78; // @[tlb.scala:58:79]
wire _entries_T_77; // @[tlb.scala:58:79]
wire _entries_T_76; // @[tlb.scala:58:79]
wire _entries_T_75; // @[tlb.scala:58:79]
wire _entries_T_74; // @[tlb.scala:58:79]
wire _entries_T_73; // @[tlb.scala:58:79]
wire _entries_T_72; // @[tlb.scala:58:79]
wire _entries_T_71; // @[tlb.scala:58:79]
wire _entries_T_70; // @[tlb.scala:58:79]
wire _entries_T_69; // @[tlb.scala:58:79]
wire _entries_T_68; // @[tlb.scala:58:79]
wire _entries_T_67; // @[tlb.scala:58:79]
wire _entries_T_66; // @[tlb.scala:58:79]
wire _entries_T_65; // @[tlb.scala:58:79]
assign _entries_T_65 = _entries_WIRE_9[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_65; // @[tlb.scala:58:79]
assign _entries_T_66 = _entries_WIRE_9[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_c = _entries_T_66; // @[tlb.scala:58:79]
assign _entries_T_67 = _entries_WIRE_9[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_eff = _entries_T_67; // @[tlb.scala:58:79]
assign _entries_T_68 = _entries_WIRE_9[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_paa = _entries_T_68; // @[tlb.scala:58:79]
assign _entries_T_69 = _entries_WIRE_9[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_pal = _entries_T_69; // @[tlb.scala:58:79]
assign _entries_T_70 = _entries_WIRE_9[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_pr = _entries_T_70; // @[tlb.scala:58:79]
assign _entries_T_71 = _entries_WIRE_9[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_px = _entries_T_71; // @[tlb.scala:58:79]
assign _entries_T_72 = _entries_WIRE_9[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_pw = _entries_T_72; // @[tlb.scala:58:79]
assign _entries_T_73 = _entries_WIRE_9[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_sr = _entries_T_73; // @[tlb.scala:58:79]
assign _entries_T_74 = _entries_WIRE_9[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_sx = _entries_T_74; // @[tlb.scala:58:79]
assign _entries_T_75 = _entries_WIRE_9[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_sw = _entries_T_75; // @[tlb.scala:58:79]
assign _entries_T_76 = _entries_WIRE_9[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_ae = _entries_T_76; // @[tlb.scala:58:79]
assign _entries_T_77 = _entries_WIRE_9[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_g = _entries_T_77; // @[tlb.scala:58:79]
assign _entries_T_78 = _entries_WIRE_9[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_8_u = _entries_T_78; // @[tlb.scala:58:79]
assign _entries_T_79 = _entries_WIRE_9[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_79; // @[tlb.scala:58:79]
wire [19:0] _entries_T_95; // @[tlb.scala:58:79]
wire _entries_T_94; // @[tlb.scala:58:79]
wire _entries_T_93; // @[tlb.scala:58:79]
wire _entries_T_92; // @[tlb.scala:58:79]
wire _entries_T_91; // @[tlb.scala:58:79]
wire _entries_T_90; // @[tlb.scala:58:79]
wire _entries_T_89; // @[tlb.scala:58:79]
wire _entries_T_88; // @[tlb.scala:58:79]
wire _entries_T_87; // @[tlb.scala:58:79]
wire _entries_T_86; // @[tlb.scala:58:79]
wire _entries_T_85; // @[tlb.scala:58:79]
wire _entries_T_84; // @[tlb.scala:58:79]
wire _entries_T_83; // @[tlb.scala:58:79]
wire _entries_T_82; // @[tlb.scala:58:79]
wire _entries_T_81; // @[tlb.scala:58:79]
assign _entries_T_81 = _entries_WIRE_11[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_81; // @[tlb.scala:58:79]
assign _entries_T_82 = _entries_WIRE_11[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_c = _entries_T_82; // @[tlb.scala:58:79]
assign _entries_T_83 = _entries_WIRE_11[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_eff = _entries_T_83; // @[tlb.scala:58:79]
assign _entries_T_84 = _entries_WIRE_11[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_paa = _entries_T_84; // @[tlb.scala:58:79]
assign _entries_T_85 = _entries_WIRE_11[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_pal = _entries_T_85; // @[tlb.scala:58:79]
assign _entries_T_86 = _entries_WIRE_11[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_pr = _entries_T_86; // @[tlb.scala:58:79]
assign _entries_T_87 = _entries_WIRE_11[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_px = _entries_T_87; // @[tlb.scala:58:79]
assign _entries_T_88 = _entries_WIRE_11[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_pw = _entries_T_88; // @[tlb.scala:58:79]
assign _entries_T_89 = _entries_WIRE_11[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_sr = _entries_T_89; // @[tlb.scala:58:79]
assign _entries_T_90 = _entries_WIRE_11[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_sx = _entries_T_90; // @[tlb.scala:58:79]
assign _entries_T_91 = _entries_WIRE_11[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_sw = _entries_T_91; // @[tlb.scala:58:79]
assign _entries_T_92 = _entries_WIRE_11[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_ae = _entries_T_92; // @[tlb.scala:58:79]
assign _entries_T_93 = _entries_WIRE_11[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_g = _entries_T_93; // @[tlb.scala:58:79]
assign _entries_T_94 = _entries_WIRE_11[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_10_u = _entries_T_94; // @[tlb.scala:58:79]
assign _entries_T_95 = _entries_WIRE_11[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_95; // @[tlb.scala:58:79]
wire [19:0] _entries_T_111; // @[tlb.scala:58:79]
wire _entries_T_110; // @[tlb.scala:58:79]
wire _entries_T_109; // @[tlb.scala:58:79]
wire _entries_T_108; // @[tlb.scala:58:79]
wire _entries_T_107; // @[tlb.scala:58:79]
wire _entries_T_106; // @[tlb.scala:58:79]
wire _entries_T_105; // @[tlb.scala:58:79]
wire _entries_T_104; // @[tlb.scala:58:79]
wire _entries_T_103; // @[tlb.scala:58:79]
wire _entries_T_102; // @[tlb.scala:58:79]
wire _entries_T_101; // @[tlb.scala:58:79]
wire _entries_T_100; // @[tlb.scala:58:79]
wire _entries_T_99; // @[tlb.scala:58:79]
wire _entries_T_98; // @[tlb.scala:58:79]
wire _entries_T_97; // @[tlb.scala:58:79]
assign _entries_T_97 = _entries_WIRE_13[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_97; // @[tlb.scala:58:79]
assign _entries_T_98 = _entries_WIRE_13[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_c = _entries_T_98; // @[tlb.scala:58:79]
assign _entries_T_99 = _entries_WIRE_13[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_eff = _entries_T_99; // @[tlb.scala:58:79]
assign _entries_T_100 = _entries_WIRE_13[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_paa = _entries_T_100; // @[tlb.scala:58:79]
assign _entries_T_101 = _entries_WIRE_13[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_pal = _entries_T_101; // @[tlb.scala:58:79]
assign _entries_T_102 = _entries_WIRE_13[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_pr = _entries_T_102; // @[tlb.scala:58:79]
assign _entries_T_103 = _entries_WIRE_13[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_px = _entries_T_103; // @[tlb.scala:58:79]
assign _entries_T_104 = _entries_WIRE_13[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_pw = _entries_T_104; // @[tlb.scala:58:79]
assign _entries_T_105 = _entries_WIRE_13[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_sr = _entries_T_105; // @[tlb.scala:58:79]
assign _entries_T_106 = _entries_WIRE_13[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_sx = _entries_T_106; // @[tlb.scala:58:79]
assign _entries_T_107 = _entries_WIRE_13[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_sw = _entries_T_107; // @[tlb.scala:58:79]
assign _entries_T_108 = _entries_WIRE_13[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_ae = _entries_T_108; // @[tlb.scala:58:79]
assign _entries_T_109 = _entries_WIRE_13[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_g = _entries_T_109; // @[tlb.scala:58:79]
assign _entries_T_110 = _entries_WIRE_13[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_12_u = _entries_T_110; // @[tlb.scala:58:79]
assign _entries_T_111 = _entries_WIRE_13[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_111; // @[tlb.scala:58:79]
wire [19:0] _entries_T_127; // @[tlb.scala:58:79]
wire _entries_T_126; // @[tlb.scala:58:79]
wire _entries_T_125; // @[tlb.scala:58:79]
wire _entries_T_124; // @[tlb.scala:58:79]
wire _entries_T_123; // @[tlb.scala:58:79]
wire _entries_T_122; // @[tlb.scala:58:79]
wire _entries_T_121; // @[tlb.scala:58:79]
wire _entries_T_120; // @[tlb.scala:58:79]
wire _entries_T_119; // @[tlb.scala:58:79]
wire _entries_T_118; // @[tlb.scala:58:79]
wire _entries_T_117; // @[tlb.scala:58:79]
wire _entries_T_116; // @[tlb.scala:58:79]
wire _entries_T_115; // @[tlb.scala:58:79]
wire _entries_T_114; // @[tlb.scala:58:79]
wire _entries_T_113; // @[tlb.scala:58:79]
assign _entries_T_113 = _entries_WIRE_15[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_113; // @[tlb.scala:58:79]
assign _entries_T_114 = _entries_WIRE_15[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_c = _entries_T_114; // @[tlb.scala:58:79]
assign _entries_T_115 = _entries_WIRE_15[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_eff = _entries_T_115; // @[tlb.scala:58:79]
assign _entries_T_116 = _entries_WIRE_15[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_paa = _entries_T_116; // @[tlb.scala:58:79]
assign _entries_T_117 = _entries_WIRE_15[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_pal = _entries_T_117; // @[tlb.scala:58:79]
assign _entries_T_118 = _entries_WIRE_15[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_pr = _entries_T_118; // @[tlb.scala:58:79]
assign _entries_T_119 = _entries_WIRE_15[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_px = _entries_T_119; // @[tlb.scala:58:79]
assign _entries_T_120 = _entries_WIRE_15[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_pw = _entries_T_120; // @[tlb.scala:58:79]
assign _entries_T_121 = _entries_WIRE_15[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_sr = _entries_T_121; // @[tlb.scala:58:79]
assign _entries_T_122 = _entries_WIRE_15[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_sx = _entries_T_122; // @[tlb.scala:58:79]
assign _entries_T_123 = _entries_WIRE_15[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_sw = _entries_T_123; // @[tlb.scala:58:79]
assign _entries_T_124 = _entries_WIRE_15[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_ae = _entries_T_124; // @[tlb.scala:58:79]
assign _entries_T_125 = _entries_WIRE_15[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_g = _entries_T_125; // @[tlb.scala:58:79]
assign _entries_T_126 = _entries_WIRE_15[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_14_u = _entries_T_126; // @[tlb.scala:58:79]
assign _entries_T_127 = _entries_WIRE_15[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_127; // @[tlb.scala:58:79]
wire [19:0] _entries_T_142; // @[tlb.scala:58:79]
wire _entries_T_141; // @[tlb.scala:58:79]
wire _entries_T_140; // @[tlb.scala:58:79]
wire _entries_T_139; // @[tlb.scala:58:79]
wire _entries_T_138; // @[tlb.scala:58:79]
wire _entries_T_137; // @[tlb.scala:58:79]
wire _entries_T_136; // @[tlb.scala:58:79]
wire _entries_T_135; // @[tlb.scala:58:79]
wire _entries_T_134; // @[tlb.scala:58:79]
wire _entries_T_133; // @[tlb.scala:58:79]
wire _entries_T_132; // @[tlb.scala:58:79]
wire _entries_T_131; // @[tlb.scala:58:79]
wire _entries_T_130; // @[tlb.scala:58:79]
wire _entries_T_129; // @[tlb.scala:58:79]
wire _entries_T_128; // @[tlb.scala:58:79]
assign _entries_T_128 = _entries_WIRE_17[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_128; // @[tlb.scala:58:79]
assign _entries_T_129 = _entries_WIRE_17[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_c = _entries_T_129; // @[tlb.scala:58:79]
assign _entries_T_130 = _entries_WIRE_17[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_eff = _entries_T_130; // @[tlb.scala:58:79]
assign _entries_T_131 = _entries_WIRE_17[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_paa = _entries_T_131; // @[tlb.scala:58:79]
assign _entries_T_132 = _entries_WIRE_17[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_pal = _entries_T_132; // @[tlb.scala:58:79]
assign _entries_T_133 = _entries_WIRE_17[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_pr = _entries_T_133; // @[tlb.scala:58:79]
assign _entries_T_134 = _entries_WIRE_17[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_px = _entries_T_134; // @[tlb.scala:58:79]
assign _entries_T_135 = _entries_WIRE_17[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_pw = _entries_T_135; // @[tlb.scala:58:79]
assign _entries_T_136 = _entries_WIRE_17[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_sr = _entries_T_136; // @[tlb.scala:58:79]
assign _entries_T_137 = _entries_WIRE_17[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_sx = _entries_T_137; // @[tlb.scala:58:79]
assign _entries_T_138 = _entries_WIRE_17[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_sw = _entries_T_138; // @[tlb.scala:58:79]
assign _entries_T_139 = _entries_WIRE_17[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_ae = _entries_T_139; // @[tlb.scala:58:79]
assign _entries_T_140 = _entries_WIRE_17[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_g = _entries_T_140; // @[tlb.scala:58:79]
assign _entries_T_141 = _entries_WIRE_17[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_16_u = _entries_T_141; // @[tlb.scala:58:79]
assign _entries_T_142 = _entries_WIRE_17[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_142; // @[tlb.scala:58:79]
wire [19:0] _entries_T_157; // @[tlb.scala:58:79]
wire _entries_T_156; // @[tlb.scala:58:79]
wire _entries_T_155; // @[tlb.scala:58:79]
wire _entries_T_154; // @[tlb.scala:58:79]
wire _entries_T_153; // @[tlb.scala:58:79]
wire _entries_T_152; // @[tlb.scala:58:79]
wire _entries_T_151; // @[tlb.scala:58:79]
wire _entries_T_150; // @[tlb.scala:58:79]
wire _entries_T_149; // @[tlb.scala:58:79]
wire _entries_T_148; // @[tlb.scala:58:79]
wire _entries_T_147; // @[tlb.scala:58:79]
wire _entries_T_146; // @[tlb.scala:58:79]
wire _entries_T_145; // @[tlb.scala:58:79]
wire _entries_T_144; // @[tlb.scala:58:79]
wire _entries_T_143; // @[tlb.scala:58:79]
assign _entries_T_143 = _entries_WIRE_19[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_143; // @[tlb.scala:58:79]
assign _entries_T_144 = _entries_WIRE_19[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_c = _entries_T_144; // @[tlb.scala:58:79]
assign _entries_T_145 = _entries_WIRE_19[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_eff = _entries_T_145; // @[tlb.scala:58:79]
assign _entries_T_146 = _entries_WIRE_19[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_paa = _entries_T_146; // @[tlb.scala:58:79]
assign _entries_T_147 = _entries_WIRE_19[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_pal = _entries_T_147; // @[tlb.scala:58:79]
assign _entries_T_148 = _entries_WIRE_19[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_pr = _entries_T_148; // @[tlb.scala:58:79]
assign _entries_T_149 = _entries_WIRE_19[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_px = _entries_T_149; // @[tlb.scala:58:79]
assign _entries_T_150 = _entries_WIRE_19[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_pw = _entries_T_150; // @[tlb.scala:58:79]
assign _entries_T_151 = _entries_WIRE_19[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_sr = _entries_T_151; // @[tlb.scala:58:79]
assign _entries_T_152 = _entries_WIRE_19[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_sx = _entries_T_152; // @[tlb.scala:58:79]
assign _entries_T_153 = _entries_WIRE_19[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_sw = _entries_T_153; // @[tlb.scala:58:79]
assign _entries_T_154 = _entries_WIRE_19[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_ae = _entries_T_154; // @[tlb.scala:58:79]
assign _entries_T_155 = _entries_WIRE_19[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_g = _entries_T_155; // @[tlb.scala:58:79]
assign _entries_T_156 = _entries_WIRE_19[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_18_u = _entries_T_156; // @[tlb.scala:58:79]
assign _entries_T_157 = _entries_WIRE_19[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_157; // @[tlb.scala:58:79]
wire [19:0] _entries_T_172; // @[tlb.scala:58:79]
wire _entries_T_171; // @[tlb.scala:58:79]
wire _entries_T_170; // @[tlb.scala:58:79]
wire _entries_T_169; // @[tlb.scala:58:79]
wire _entries_T_168; // @[tlb.scala:58:79]
wire _entries_T_167; // @[tlb.scala:58:79]
wire _entries_T_166; // @[tlb.scala:58:79]
wire _entries_T_165; // @[tlb.scala:58:79]
wire _entries_T_164; // @[tlb.scala:58:79]
wire _entries_T_163; // @[tlb.scala:58:79]
wire _entries_T_162; // @[tlb.scala:58:79]
wire _entries_T_161; // @[tlb.scala:58:79]
wire _entries_T_160; // @[tlb.scala:58:79]
wire _entries_T_159; // @[tlb.scala:58:79]
wire _entries_T_158; // @[tlb.scala:58:79]
assign _entries_T_158 = _entries_WIRE_21[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_158; // @[tlb.scala:58:79]
assign _entries_T_159 = _entries_WIRE_21[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_c = _entries_T_159; // @[tlb.scala:58:79]
assign _entries_T_160 = _entries_WIRE_21[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_eff = _entries_T_160; // @[tlb.scala:58:79]
assign _entries_T_161 = _entries_WIRE_21[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_paa = _entries_T_161; // @[tlb.scala:58:79]
assign _entries_T_162 = _entries_WIRE_21[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_pal = _entries_T_162; // @[tlb.scala:58:79]
assign _entries_T_163 = _entries_WIRE_21[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_pr = _entries_T_163; // @[tlb.scala:58:79]
assign _entries_T_164 = _entries_WIRE_21[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_px = _entries_T_164; // @[tlb.scala:58:79]
assign _entries_T_165 = _entries_WIRE_21[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_pw = _entries_T_165; // @[tlb.scala:58:79]
assign _entries_T_166 = _entries_WIRE_21[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_sr = _entries_T_166; // @[tlb.scala:58:79]
assign _entries_T_167 = _entries_WIRE_21[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_sx = _entries_T_167; // @[tlb.scala:58:79]
assign _entries_T_168 = _entries_WIRE_21[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_sw = _entries_T_168; // @[tlb.scala:58:79]
assign _entries_T_169 = _entries_WIRE_21[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_ae = _entries_T_169; // @[tlb.scala:58:79]
assign _entries_T_170 = _entries_WIRE_21[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_g = _entries_T_170; // @[tlb.scala:58:79]
assign _entries_T_171 = _entries_WIRE_21[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_20_u = _entries_T_171; // @[tlb.scala:58:79]
assign _entries_T_172 = _entries_WIRE_21[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_172; // @[tlb.scala:58:79]
wire [19:0] _entries_T_187; // @[tlb.scala:58:79]
wire _entries_T_186; // @[tlb.scala:58:79]
wire _entries_T_185; // @[tlb.scala:58:79]
wire _entries_T_184; // @[tlb.scala:58:79]
wire _entries_T_183; // @[tlb.scala:58:79]
wire _entries_T_182; // @[tlb.scala:58:79]
wire _entries_T_181; // @[tlb.scala:58:79]
wire _entries_T_180; // @[tlb.scala:58:79]
wire _entries_T_179; // @[tlb.scala:58:79]
wire _entries_T_178; // @[tlb.scala:58:79]
wire _entries_T_177; // @[tlb.scala:58:79]
wire _entries_T_176; // @[tlb.scala:58:79]
wire _entries_T_175; // @[tlb.scala:58:79]
wire _entries_T_174; // @[tlb.scala:58:79]
wire _entries_T_173; // @[tlb.scala:58:79]
assign _entries_T_173 = _entries_WIRE_23[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_173; // @[tlb.scala:58:79]
assign _entries_T_174 = _entries_WIRE_23[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_c = _entries_T_174; // @[tlb.scala:58:79]
assign _entries_T_175 = _entries_WIRE_23[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_eff = _entries_T_175; // @[tlb.scala:58:79]
assign _entries_T_176 = _entries_WIRE_23[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_paa = _entries_T_176; // @[tlb.scala:58:79]
assign _entries_T_177 = _entries_WIRE_23[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_pal = _entries_T_177; // @[tlb.scala:58:79]
assign _entries_T_178 = _entries_WIRE_23[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_pr = _entries_T_178; // @[tlb.scala:58:79]
assign _entries_T_179 = _entries_WIRE_23[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_px = _entries_T_179; // @[tlb.scala:58:79]
assign _entries_T_180 = _entries_WIRE_23[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_pw = _entries_T_180; // @[tlb.scala:58:79]
assign _entries_T_181 = _entries_WIRE_23[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_sr = _entries_T_181; // @[tlb.scala:58:79]
assign _entries_T_182 = _entries_WIRE_23[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_sx = _entries_T_182; // @[tlb.scala:58:79]
assign _entries_T_183 = _entries_WIRE_23[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_sw = _entries_T_183; // @[tlb.scala:58:79]
assign _entries_T_184 = _entries_WIRE_23[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_ae = _entries_T_184; // @[tlb.scala:58:79]
assign _entries_T_185 = _entries_WIRE_23[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_g = _entries_T_185; // @[tlb.scala:58:79]
assign _entries_T_186 = _entries_WIRE_23[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_22_u = _entries_T_186; // @[tlb.scala:58:79]
assign _entries_T_187 = _entries_WIRE_23[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_187; // @[tlb.scala:58:79]
wire [19:0] _entries_T_202; // @[tlb.scala:58:79]
wire _entries_T_201; // @[tlb.scala:58:79]
wire _entries_T_200; // @[tlb.scala:58:79]
wire _entries_T_199; // @[tlb.scala:58:79]
wire _entries_T_198; // @[tlb.scala:58:79]
wire _entries_T_197; // @[tlb.scala:58:79]
wire _entries_T_196; // @[tlb.scala:58:79]
wire _entries_T_195; // @[tlb.scala:58:79]
wire _entries_T_194; // @[tlb.scala:58:79]
wire _entries_T_193; // @[tlb.scala:58:79]
wire _entries_T_192; // @[tlb.scala:58:79]
wire _entries_T_191; // @[tlb.scala:58:79]
wire _entries_T_190; // @[tlb.scala:58:79]
wire _entries_T_189; // @[tlb.scala:58:79]
wire _entries_T_188; // @[tlb.scala:58:79]
assign _entries_T_188 = _entries_WIRE_25[0]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_188; // @[tlb.scala:58:79]
assign _entries_T_189 = _entries_WIRE_25[1]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_c = _entries_T_189; // @[tlb.scala:58:79]
assign _entries_T_190 = _entries_WIRE_25[2]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_eff = _entries_T_190; // @[tlb.scala:58:79]
assign _entries_T_191 = _entries_WIRE_25[3]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_paa = _entries_T_191; // @[tlb.scala:58:79]
assign _entries_T_192 = _entries_WIRE_25[4]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_pal = _entries_T_192; // @[tlb.scala:58:79]
assign _entries_T_193 = _entries_WIRE_25[5]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_pr = _entries_T_193; // @[tlb.scala:58:79]
assign _entries_T_194 = _entries_WIRE_25[6]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_px = _entries_T_194; // @[tlb.scala:58:79]
assign _entries_T_195 = _entries_WIRE_25[7]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_pw = _entries_T_195; // @[tlb.scala:58:79]
assign _entries_T_196 = _entries_WIRE_25[8]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_sr = _entries_T_196; // @[tlb.scala:58:79]
assign _entries_T_197 = _entries_WIRE_25[9]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_sx = _entries_T_197; // @[tlb.scala:58:79]
assign _entries_T_198 = _entries_WIRE_25[10]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_sw = _entries_T_198; // @[tlb.scala:58:79]
assign _entries_T_199 = _entries_WIRE_25[11]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_ae = _entries_T_199; // @[tlb.scala:58:79]
assign _entries_T_200 = _entries_WIRE_25[12]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_g = _entries_T_200; // @[tlb.scala:58:79]
assign _entries_T_201 = _entries_WIRE_25[13]; // @[tlb.scala:58:79]
wire _entries_WIRE_24_u = _entries_T_201; // @[tlb.scala:58:79]
assign _entries_T_202 = _entries_WIRE_25[33:14]; // @[tlb.scala:58:79]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_202; // @[tlb.scala:58:79]
wire [19:0] entries_0_0_ppn = _entries_WIRE_26_0_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_u = _entries_WIRE_26_0_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_g = _entries_WIRE_26_0_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_ae = _entries_WIRE_26_0_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_sw = _entries_WIRE_26_0_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_sx = _entries_WIRE_26_0_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_sr = _entries_WIRE_26_0_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_pw = _entries_WIRE_26_0_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_px = _entries_WIRE_26_0_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_pr = _entries_WIRE_26_0_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_pal = _entries_WIRE_26_0_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_paa = _entries_WIRE_26_0_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_eff = _entries_WIRE_26_0_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_c = _entries_WIRE_26_0_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_0_fragmented_superpage = _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_1_ppn = _entries_WIRE_26_1_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_u = _entries_WIRE_26_1_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_g = _entries_WIRE_26_1_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_ae = _entries_WIRE_26_1_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_sw = _entries_WIRE_26_1_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_sx = _entries_WIRE_26_1_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_sr = _entries_WIRE_26_1_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_pw = _entries_WIRE_26_1_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_px = _entries_WIRE_26_1_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_pr = _entries_WIRE_26_1_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_pal = _entries_WIRE_26_1_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_paa = _entries_WIRE_26_1_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_eff = _entries_WIRE_26_1_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_c = _entries_WIRE_26_1_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_1_fragmented_superpage = _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_2_ppn = _entries_WIRE_26_2_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_u = _entries_WIRE_26_2_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_g = _entries_WIRE_26_2_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_ae = _entries_WIRE_26_2_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_sw = _entries_WIRE_26_2_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_sx = _entries_WIRE_26_2_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_sr = _entries_WIRE_26_2_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_pw = _entries_WIRE_26_2_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_px = _entries_WIRE_26_2_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_pr = _entries_WIRE_26_2_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_pal = _entries_WIRE_26_2_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_paa = _entries_WIRE_26_2_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_eff = _entries_WIRE_26_2_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_c = _entries_WIRE_26_2_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_2_fragmented_superpage = _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_3_ppn = _entries_WIRE_26_3_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_u = _entries_WIRE_26_3_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_g = _entries_WIRE_26_3_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_ae = _entries_WIRE_26_3_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_sw = _entries_WIRE_26_3_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_sx = _entries_WIRE_26_3_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_sr = _entries_WIRE_26_3_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_pw = _entries_WIRE_26_3_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_px = _entries_WIRE_26_3_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_pr = _entries_WIRE_26_3_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_pal = _entries_WIRE_26_3_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_paa = _entries_WIRE_26_3_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_eff = _entries_WIRE_26_3_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_c = _entries_WIRE_26_3_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_3_fragmented_superpage = _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_4_ppn = _entries_WIRE_26_4_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_u = _entries_WIRE_26_4_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_g = _entries_WIRE_26_4_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_ae = _entries_WIRE_26_4_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_sw = _entries_WIRE_26_4_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_sx = _entries_WIRE_26_4_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_sr = _entries_WIRE_26_4_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_pw = _entries_WIRE_26_4_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_px = _entries_WIRE_26_4_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_pr = _entries_WIRE_26_4_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_pal = _entries_WIRE_26_4_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_paa = _entries_WIRE_26_4_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_eff = _entries_WIRE_26_4_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_c = _entries_WIRE_26_4_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_4_fragmented_superpage = _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_5_ppn = _entries_WIRE_26_5_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_u = _entries_WIRE_26_5_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_g = _entries_WIRE_26_5_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_ae = _entries_WIRE_26_5_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_sw = _entries_WIRE_26_5_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_sx = _entries_WIRE_26_5_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_sr = _entries_WIRE_26_5_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_pw = _entries_WIRE_26_5_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_px = _entries_WIRE_26_5_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_pr = _entries_WIRE_26_5_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_pal = _entries_WIRE_26_5_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_paa = _entries_WIRE_26_5_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_eff = _entries_WIRE_26_5_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_c = _entries_WIRE_26_5_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_5_fragmented_superpage = _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_6_ppn = _entries_WIRE_26_6_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_u = _entries_WIRE_26_6_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_g = _entries_WIRE_26_6_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_ae = _entries_WIRE_26_6_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_sw = _entries_WIRE_26_6_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_sx = _entries_WIRE_26_6_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_sr = _entries_WIRE_26_6_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_pw = _entries_WIRE_26_6_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_px = _entries_WIRE_26_6_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_pr = _entries_WIRE_26_6_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_pal = _entries_WIRE_26_6_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_paa = _entries_WIRE_26_6_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_eff = _entries_WIRE_26_6_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_c = _entries_WIRE_26_6_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_6_fragmented_superpage = _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_7_ppn = _entries_WIRE_26_7_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_u = _entries_WIRE_26_7_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_g = _entries_WIRE_26_7_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_ae = _entries_WIRE_26_7_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_sw = _entries_WIRE_26_7_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_sx = _entries_WIRE_26_7_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_sr = _entries_WIRE_26_7_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_pw = _entries_WIRE_26_7_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_px = _entries_WIRE_26_7_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_pr = _entries_WIRE_26_7_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_pal = _entries_WIRE_26_7_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_paa = _entries_WIRE_26_7_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_eff = _entries_WIRE_26_7_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_c = _entries_WIRE_26_7_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_7_fragmented_superpage = _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_8_ppn = _entries_WIRE_26_8_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_u = _entries_WIRE_26_8_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_g = _entries_WIRE_26_8_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_ae = _entries_WIRE_26_8_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_sw = _entries_WIRE_26_8_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_sx = _entries_WIRE_26_8_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_sr = _entries_WIRE_26_8_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_pw = _entries_WIRE_26_8_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_px = _entries_WIRE_26_8_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_pr = _entries_WIRE_26_8_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_pal = _entries_WIRE_26_8_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_paa = _entries_WIRE_26_8_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_eff = _entries_WIRE_26_8_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_c = _entries_WIRE_26_8_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_8_fragmented_superpage = _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_9_ppn = _entries_WIRE_26_9_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_u = _entries_WIRE_26_9_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_g = _entries_WIRE_26_9_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_ae = _entries_WIRE_26_9_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_sw = _entries_WIRE_26_9_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_sx = _entries_WIRE_26_9_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_sr = _entries_WIRE_26_9_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_pw = _entries_WIRE_26_9_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_px = _entries_WIRE_26_9_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_pr = _entries_WIRE_26_9_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_pal = _entries_WIRE_26_9_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_paa = _entries_WIRE_26_9_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_eff = _entries_WIRE_26_9_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_c = _entries_WIRE_26_9_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_9_fragmented_superpage = _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_10_ppn = _entries_WIRE_26_10_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_u = _entries_WIRE_26_10_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_g = _entries_WIRE_26_10_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_ae = _entries_WIRE_26_10_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_sw = _entries_WIRE_26_10_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_sx = _entries_WIRE_26_10_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_sr = _entries_WIRE_26_10_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_pw = _entries_WIRE_26_10_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_px = _entries_WIRE_26_10_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_pr = _entries_WIRE_26_10_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_pal = _entries_WIRE_26_10_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_paa = _entries_WIRE_26_10_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_eff = _entries_WIRE_26_10_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_c = _entries_WIRE_26_10_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_10_fragmented_superpage = _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_11_ppn = _entries_WIRE_26_11_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_u = _entries_WIRE_26_11_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_g = _entries_WIRE_26_11_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_ae = _entries_WIRE_26_11_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_sw = _entries_WIRE_26_11_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_sx = _entries_WIRE_26_11_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_sr = _entries_WIRE_26_11_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_pw = _entries_WIRE_26_11_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_px = _entries_WIRE_26_11_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_pr = _entries_WIRE_26_11_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_pal = _entries_WIRE_26_11_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_paa = _entries_WIRE_26_11_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_eff = _entries_WIRE_26_11_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_c = _entries_WIRE_26_11_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_11_fragmented_superpage = _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] entries_0_12_ppn = _entries_WIRE_26_12_ppn; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_u = _entries_WIRE_26_12_u; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_g = _entries_WIRE_26_12_g; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_ae = _entries_WIRE_26_12_ae; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_sw = _entries_WIRE_26_12_sw; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_sx = _entries_WIRE_26_12_sx; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_sr = _entries_WIRE_26_12_sr; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_pw = _entries_WIRE_26_12_pw; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_px = _entries_WIRE_26_12_px; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_pr = _entries_WIRE_26_12_pr; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_pal = _entries_WIRE_26_12_pal; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_paa = _entries_WIRE_26_12_paa; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_eff = _entries_WIRE_26_12_eff; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_c = _entries_WIRE_26_12_c; // @[tlb.scala:119:49, :211:38]
wire entries_0_12_fragmented_superpage = _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:119:49, :211:38]
wire [19:0] _normal_entries_T_15; // @[tlb.scala:58:79]
wire _normal_entries_T_14; // @[tlb.scala:58:79]
wire _normal_entries_T_13; // @[tlb.scala:58:79]
wire _normal_entries_T_12; // @[tlb.scala:58:79]
wire _normal_entries_T_11; // @[tlb.scala:58:79]
wire _normal_entries_T_10; // @[tlb.scala:58:79]
wire _normal_entries_T_9; // @[tlb.scala:58:79]
wire _normal_entries_T_8; // @[tlb.scala:58:79]
wire _normal_entries_T_7; // @[tlb.scala:58:79]
wire _normal_entries_T_6; // @[tlb.scala:58:79]
wire _normal_entries_T_5; // @[tlb.scala:58:79]
wire _normal_entries_T_4; // @[tlb.scala:58:79]
wire _normal_entries_T_3; // @[tlb.scala:58:79]
wire _normal_entries_T_2; // @[tlb.scala:58:79]
wire _normal_entries_T_1; // @[tlb.scala:58:79]
assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:58:79]
assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:58:79]
assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:58:79]
assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:58:79]
assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:58:79]
assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:58:79]
assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:58:79]
assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:58:79]
assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:58:79]
assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:58:79]
assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:58:79]
assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:58:79]
assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:58:79]
assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:58:79]
assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_31; // @[tlb.scala:58:79]
wire _normal_entries_T_30; // @[tlb.scala:58:79]
wire _normal_entries_T_29; // @[tlb.scala:58:79]
wire _normal_entries_T_28; // @[tlb.scala:58:79]
wire _normal_entries_T_27; // @[tlb.scala:58:79]
wire _normal_entries_T_26; // @[tlb.scala:58:79]
wire _normal_entries_T_25; // @[tlb.scala:58:79]
wire _normal_entries_T_24; // @[tlb.scala:58:79]
wire _normal_entries_T_23; // @[tlb.scala:58:79]
wire _normal_entries_T_22; // @[tlb.scala:58:79]
wire _normal_entries_T_21; // @[tlb.scala:58:79]
wire _normal_entries_T_20; // @[tlb.scala:58:79]
wire _normal_entries_T_19; // @[tlb.scala:58:79]
wire _normal_entries_T_18; // @[tlb.scala:58:79]
wire _normal_entries_T_17; // @[tlb.scala:58:79]
assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:58:79]
assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:58:79]
assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:58:79]
assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:58:79]
assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:58:79]
assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:58:79]
assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:58:79]
assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:58:79]
assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:58:79]
assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:58:79]
assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:58:79]
assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:58:79]
assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:58:79]
assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:58:79]
assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_47; // @[tlb.scala:58:79]
wire _normal_entries_T_46; // @[tlb.scala:58:79]
wire _normal_entries_T_45; // @[tlb.scala:58:79]
wire _normal_entries_T_44; // @[tlb.scala:58:79]
wire _normal_entries_T_43; // @[tlb.scala:58:79]
wire _normal_entries_T_42; // @[tlb.scala:58:79]
wire _normal_entries_T_41; // @[tlb.scala:58:79]
wire _normal_entries_T_40; // @[tlb.scala:58:79]
wire _normal_entries_T_39; // @[tlb.scala:58:79]
wire _normal_entries_T_38; // @[tlb.scala:58:79]
wire _normal_entries_T_37; // @[tlb.scala:58:79]
wire _normal_entries_T_36; // @[tlb.scala:58:79]
wire _normal_entries_T_35; // @[tlb.scala:58:79]
wire _normal_entries_T_34; // @[tlb.scala:58:79]
wire _normal_entries_T_33; // @[tlb.scala:58:79]
assign _normal_entries_T_33 = _normal_entries_WIRE_5[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_33; // @[tlb.scala:58:79]
assign _normal_entries_T_34 = _normal_entries_WIRE_5[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_c = _normal_entries_T_34; // @[tlb.scala:58:79]
assign _normal_entries_T_35 = _normal_entries_WIRE_5[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_eff = _normal_entries_T_35; // @[tlb.scala:58:79]
assign _normal_entries_T_36 = _normal_entries_WIRE_5[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_paa = _normal_entries_T_36; // @[tlb.scala:58:79]
assign _normal_entries_T_37 = _normal_entries_WIRE_5[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_pal = _normal_entries_T_37; // @[tlb.scala:58:79]
assign _normal_entries_T_38 = _normal_entries_WIRE_5[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_pr = _normal_entries_T_38; // @[tlb.scala:58:79]
assign _normal_entries_T_39 = _normal_entries_WIRE_5[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_px = _normal_entries_T_39; // @[tlb.scala:58:79]
assign _normal_entries_T_40 = _normal_entries_WIRE_5[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_pw = _normal_entries_T_40; // @[tlb.scala:58:79]
assign _normal_entries_T_41 = _normal_entries_WIRE_5[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_sr = _normal_entries_T_41; // @[tlb.scala:58:79]
assign _normal_entries_T_42 = _normal_entries_WIRE_5[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_sx = _normal_entries_T_42; // @[tlb.scala:58:79]
assign _normal_entries_T_43 = _normal_entries_WIRE_5[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_sw = _normal_entries_T_43; // @[tlb.scala:58:79]
assign _normal_entries_T_44 = _normal_entries_WIRE_5[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_ae = _normal_entries_T_44; // @[tlb.scala:58:79]
assign _normal_entries_T_45 = _normal_entries_WIRE_5[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_g = _normal_entries_T_45; // @[tlb.scala:58:79]
assign _normal_entries_T_46 = _normal_entries_WIRE_5[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_4_u = _normal_entries_T_46; // @[tlb.scala:58:79]
assign _normal_entries_T_47 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_47; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_63; // @[tlb.scala:58:79]
wire _normal_entries_T_62; // @[tlb.scala:58:79]
wire _normal_entries_T_61; // @[tlb.scala:58:79]
wire _normal_entries_T_60; // @[tlb.scala:58:79]
wire _normal_entries_T_59; // @[tlb.scala:58:79]
wire _normal_entries_T_58; // @[tlb.scala:58:79]
wire _normal_entries_T_57; // @[tlb.scala:58:79]
wire _normal_entries_T_56; // @[tlb.scala:58:79]
wire _normal_entries_T_55; // @[tlb.scala:58:79]
wire _normal_entries_T_54; // @[tlb.scala:58:79]
wire _normal_entries_T_53; // @[tlb.scala:58:79]
wire _normal_entries_T_52; // @[tlb.scala:58:79]
wire _normal_entries_T_51; // @[tlb.scala:58:79]
wire _normal_entries_T_50; // @[tlb.scala:58:79]
wire _normal_entries_T_49; // @[tlb.scala:58:79]
assign _normal_entries_T_49 = _normal_entries_WIRE_7[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_49; // @[tlb.scala:58:79]
assign _normal_entries_T_50 = _normal_entries_WIRE_7[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_c = _normal_entries_T_50; // @[tlb.scala:58:79]
assign _normal_entries_T_51 = _normal_entries_WIRE_7[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_eff = _normal_entries_T_51; // @[tlb.scala:58:79]
assign _normal_entries_T_52 = _normal_entries_WIRE_7[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_paa = _normal_entries_T_52; // @[tlb.scala:58:79]
assign _normal_entries_T_53 = _normal_entries_WIRE_7[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_pal = _normal_entries_T_53; // @[tlb.scala:58:79]
assign _normal_entries_T_54 = _normal_entries_WIRE_7[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_pr = _normal_entries_T_54; // @[tlb.scala:58:79]
assign _normal_entries_T_55 = _normal_entries_WIRE_7[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_px = _normal_entries_T_55; // @[tlb.scala:58:79]
assign _normal_entries_T_56 = _normal_entries_WIRE_7[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_pw = _normal_entries_T_56; // @[tlb.scala:58:79]
assign _normal_entries_T_57 = _normal_entries_WIRE_7[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_sr = _normal_entries_T_57; // @[tlb.scala:58:79]
assign _normal_entries_T_58 = _normal_entries_WIRE_7[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_sx = _normal_entries_T_58; // @[tlb.scala:58:79]
assign _normal_entries_T_59 = _normal_entries_WIRE_7[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_sw = _normal_entries_T_59; // @[tlb.scala:58:79]
assign _normal_entries_T_60 = _normal_entries_WIRE_7[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_ae = _normal_entries_T_60; // @[tlb.scala:58:79]
assign _normal_entries_T_61 = _normal_entries_WIRE_7[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_g = _normal_entries_T_61; // @[tlb.scala:58:79]
assign _normal_entries_T_62 = _normal_entries_WIRE_7[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_6_u = _normal_entries_T_62; // @[tlb.scala:58:79]
assign _normal_entries_T_63 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_63; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_79; // @[tlb.scala:58:79]
wire _normal_entries_T_78; // @[tlb.scala:58:79]
wire _normal_entries_T_77; // @[tlb.scala:58:79]
wire _normal_entries_T_76; // @[tlb.scala:58:79]
wire _normal_entries_T_75; // @[tlb.scala:58:79]
wire _normal_entries_T_74; // @[tlb.scala:58:79]
wire _normal_entries_T_73; // @[tlb.scala:58:79]
wire _normal_entries_T_72; // @[tlb.scala:58:79]
wire _normal_entries_T_71; // @[tlb.scala:58:79]
wire _normal_entries_T_70; // @[tlb.scala:58:79]
wire _normal_entries_T_69; // @[tlb.scala:58:79]
wire _normal_entries_T_68; // @[tlb.scala:58:79]
wire _normal_entries_T_67; // @[tlb.scala:58:79]
wire _normal_entries_T_66; // @[tlb.scala:58:79]
wire _normal_entries_T_65; // @[tlb.scala:58:79]
assign _normal_entries_T_65 = _normal_entries_WIRE_9[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_65; // @[tlb.scala:58:79]
assign _normal_entries_T_66 = _normal_entries_WIRE_9[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_c = _normal_entries_T_66; // @[tlb.scala:58:79]
assign _normal_entries_T_67 = _normal_entries_WIRE_9[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_eff = _normal_entries_T_67; // @[tlb.scala:58:79]
assign _normal_entries_T_68 = _normal_entries_WIRE_9[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_paa = _normal_entries_T_68; // @[tlb.scala:58:79]
assign _normal_entries_T_69 = _normal_entries_WIRE_9[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_pal = _normal_entries_T_69; // @[tlb.scala:58:79]
assign _normal_entries_T_70 = _normal_entries_WIRE_9[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_pr = _normal_entries_T_70; // @[tlb.scala:58:79]
assign _normal_entries_T_71 = _normal_entries_WIRE_9[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_px = _normal_entries_T_71; // @[tlb.scala:58:79]
assign _normal_entries_T_72 = _normal_entries_WIRE_9[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_pw = _normal_entries_T_72; // @[tlb.scala:58:79]
assign _normal_entries_T_73 = _normal_entries_WIRE_9[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_sr = _normal_entries_T_73; // @[tlb.scala:58:79]
assign _normal_entries_T_74 = _normal_entries_WIRE_9[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_sx = _normal_entries_T_74; // @[tlb.scala:58:79]
assign _normal_entries_T_75 = _normal_entries_WIRE_9[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_sw = _normal_entries_T_75; // @[tlb.scala:58:79]
assign _normal_entries_T_76 = _normal_entries_WIRE_9[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_ae = _normal_entries_T_76; // @[tlb.scala:58:79]
assign _normal_entries_T_77 = _normal_entries_WIRE_9[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_g = _normal_entries_T_77; // @[tlb.scala:58:79]
assign _normal_entries_T_78 = _normal_entries_WIRE_9[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_8_u = _normal_entries_T_78; // @[tlb.scala:58:79]
assign _normal_entries_T_79 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_79; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_95; // @[tlb.scala:58:79]
wire _normal_entries_T_94; // @[tlb.scala:58:79]
wire _normal_entries_T_93; // @[tlb.scala:58:79]
wire _normal_entries_T_92; // @[tlb.scala:58:79]
wire _normal_entries_T_91; // @[tlb.scala:58:79]
wire _normal_entries_T_90; // @[tlb.scala:58:79]
wire _normal_entries_T_89; // @[tlb.scala:58:79]
wire _normal_entries_T_88; // @[tlb.scala:58:79]
wire _normal_entries_T_87; // @[tlb.scala:58:79]
wire _normal_entries_T_86; // @[tlb.scala:58:79]
wire _normal_entries_T_85; // @[tlb.scala:58:79]
wire _normal_entries_T_84; // @[tlb.scala:58:79]
wire _normal_entries_T_83; // @[tlb.scala:58:79]
wire _normal_entries_T_82; // @[tlb.scala:58:79]
wire _normal_entries_T_81; // @[tlb.scala:58:79]
assign _normal_entries_T_81 = _normal_entries_WIRE_11[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_81; // @[tlb.scala:58:79]
assign _normal_entries_T_82 = _normal_entries_WIRE_11[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_c = _normal_entries_T_82; // @[tlb.scala:58:79]
assign _normal_entries_T_83 = _normal_entries_WIRE_11[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_eff = _normal_entries_T_83; // @[tlb.scala:58:79]
assign _normal_entries_T_84 = _normal_entries_WIRE_11[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_paa = _normal_entries_T_84; // @[tlb.scala:58:79]
assign _normal_entries_T_85 = _normal_entries_WIRE_11[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_pal = _normal_entries_T_85; // @[tlb.scala:58:79]
assign _normal_entries_T_86 = _normal_entries_WIRE_11[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_pr = _normal_entries_T_86; // @[tlb.scala:58:79]
assign _normal_entries_T_87 = _normal_entries_WIRE_11[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_px = _normal_entries_T_87; // @[tlb.scala:58:79]
assign _normal_entries_T_88 = _normal_entries_WIRE_11[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_pw = _normal_entries_T_88; // @[tlb.scala:58:79]
assign _normal_entries_T_89 = _normal_entries_WIRE_11[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_sr = _normal_entries_T_89; // @[tlb.scala:58:79]
assign _normal_entries_T_90 = _normal_entries_WIRE_11[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_sx = _normal_entries_T_90; // @[tlb.scala:58:79]
assign _normal_entries_T_91 = _normal_entries_WIRE_11[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_sw = _normal_entries_T_91; // @[tlb.scala:58:79]
assign _normal_entries_T_92 = _normal_entries_WIRE_11[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_ae = _normal_entries_T_92; // @[tlb.scala:58:79]
assign _normal_entries_T_93 = _normal_entries_WIRE_11[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_g = _normal_entries_T_93; // @[tlb.scala:58:79]
assign _normal_entries_T_94 = _normal_entries_WIRE_11[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_10_u = _normal_entries_T_94; // @[tlb.scala:58:79]
assign _normal_entries_T_95 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_95; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_111; // @[tlb.scala:58:79]
wire _normal_entries_T_110; // @[tlb.scala:58:79]
wire _normal_entries_T_109; // @[tlb.scala:58:79]
wire _normal_entries_T_108; // @[tlb.scala:58:79]
wire _normal_entries_T_107; // @[tlb.scala:58:79]
wire _normal_entries_T_106; // @[tlb.scala:58:79]
wire _normal_entries_T_105; // @[tlb.scala:58:79]
wire _normal_entries_T_104; // @[tlb.scala:58:79]
wire _normal_entries_T_103; // @[tlb.scala:58:79]
wire _normal_entries_T_102; // @[tlb.scala:58:79]
wire _normal_entries_T_101; // @[tlb.scala:58:79]
wire _normal_entries_T_100; // @[tlb.scala:58:79]
wire _normal_entries_T_99; // @[tlb.scala:58:79]
wire _normal_entries_T_98; // @[tlb.scala:58:79]
wire _normal_entries_T_97; // @[tlb.scala:58:79]
assign _normal_entries_T_97 = _normal_entries_WIRE_13[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_fragmented_superpage = _normal_entries_T_97; // @[tlb.scala:58:79]
assign _normal_entries_T_98 = _normal_entries_WIRE_13[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_c = _normal_entries_T_98; // @[tlb.scala:58:79]
assign _normal_entries_T_99 = _normal_entries_WIRE_13[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_eff = _normal_entries_T_99; // @[tlb.scala:58:79]
assign _normal_entries_T_100 = _normal_entries_WIRE_13[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_paa = _normal_entries_T_100; // @[tlb.scala:58:79]
assign _normal_entries_T_101 = _normal_entries_WIRE_13[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_pal = _normal_entries_T_101; // @[tlb.scala:58:79]
assign _normal_entries_T_102 = _normal_entries_WIRE_13[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_pr = _normal_entries_T_102; // @[tlb.scala:58:79]
assign _normal_entries_T_103 = _normal_entries_WIRE_13[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_px = _normal_entries_T_103; // @[tlb.scala:58:79]
assign _normal_entries_T_104 = _normal_entries_WIRE_13[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_pw = _normal_entries_T_104; // @[tlb.scala:58:79]
assign _normal_entries_T_105 = _normal_entries_WIRE_13[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_sr = _normal_entries_T_105; // @[tlb.scala:58:79]
assign _normal_entries_T_106 = _normal_entries_WIRE_13[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_sx = _normal_entries_T_106; // @[tlb.scala:58:79]
assign _normal_entries_T_107 = _normal_entries_WIRE_13[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_sw = _normal_entries_T_107; // @[tlb.scala:58:79]
assign _normal_entries_T_108 = _normal_entries_WIRE_13[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_ae = _normal_entries_T_108; // @[tlb.scala:58:79]
assign _normal_entries_T_109 = _normal_entries_WIRE_13[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_g = _normal_entries_T_109; // @[tlb.scala:58:79]
assign _normal_entries_T_110 = _normal_entries_WIRE_13[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_12_u = _normal_entries_T_110; // @[tlb.scala:58:79]
assign _normal_entries_T_111 = _normal_entries_WIRE_13[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_12_ppn = _normal_entries_T_111; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_127; // @[tlb.scala:58:79]
wire _normal_entries_T_126; // @[tlb.scala:58:79]
wire _normal_entries_T_125; // @[tlb.scala:58:79]
wire _normal_entries_T_124; // @[tlb.scala:58:79]
wire _normal_entries_T_123; // @[tlb.scala:58:79]
wire _normal_entries_T_122; // @[tlb.scala:58:79]
wire _normal_entries_T_121; // @[tlb.scala:58:79]
wire _normal_entries_T_120; // @[tlb.scala:58:79]
wire _normal_entries_T_119; // @[tlb.scala:58:79]
wire _normal_entries_T_118; // @[tlb.scala:58:79]
wire _normal_entries_T_117; // @[tlb.scala:58:79]
wire _normal_entries_T_116; // @[tlb.scala:58:79]
wire _normal_entries_T_115; // @[tlb.scala:58:79]
wire _normal_entries_T_114; // @[tlb.scala:58:79]
wire _normal_entries_T_113; // @[tlb.scala:58:79]
assign _normal_entries_T_113 = _normal_entries_WIRE_15[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_fragmented_superpage = _normal_entries_T_113; // @[tlb.scala:58:79]
assign _normal_entries_T_114 = _normal_entries_WIRE_15[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_c = _normal_entries_T_114; // @[tlb.scala:58:79]
assign _normal_entries_T_115 = _normal_entries_WIRE_15[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_eff = _normal_entries_T_115; // @[tlb.scala:58:79]
assign _normal_entries_T_116 = _normal_entries_WIRE_15[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_paa = _normal_entries_T_116; // @[tlb.scala:58:79]
assign _normal_entries_T_117 = _normal_entries_WIRE_15[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_pal = _normal_entries_T_117; // @[tlb.scala:58:79]
assign _normal_entries_T_118 = _normal_entries_WIRE_15[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_pr = _normal_entries_T_118; // @[tlb.scala:58:79]
assign _normal_entries_T_119 = _normal_entries_WIRE_15[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_px = _normal_entries_T_119; // @[tlb.scala:58:79]
assign _normal_entries_T_120 = _normal_entries_WIRE_15[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_pw = _normal_entries_T_120; // @[tlb.scala:58:79]
assign _normal_entries_T_121 = _normal_entries_WIRE_15[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_sr = _normal_entries_T_121; // @[tlb.scala:58:79]
assign _normal_entries_T_122 = _normal_entries_WIRE_15[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_sx = _normal_entries_T_122; // @[tlb.scala:58:79]
assign _normal_entries_T_123 = _normal_entries_WIRE_15[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_sw = _normal_entries_T_123; // @[tlb.scala:58:79]
assign _normal_entries_T_124 = _normal_entries_WIRE_15[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_ae = _normal_entries_T_124; // @[tlb.scala:58:79]
assign _normal_entries_T_125 = _normal_entries_WIRE_15[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_g = _normal_entries_T_125; // @[tlb.scala:58:79]
assign _normal_entries_T_126 = _normal_entries_WIRE_15[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_14_u = _normal_entries_T_126; // @[tlb.scala:58:79]
assign _normal_entries_T_127 = _normal_entries_WIRE_15[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_14_ppn = _normal_entries_T_127; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_142; // @[tlb.scala:58:79]
wire _normal_entries_T_141; // @[tlb.scala:58:79]
wire _normal_entries_T_140; // @[tlb.scala:58:79]
wire _normal_entries_T_139; // @[tlb.scala:58:79]
wire _normal_entries_T_138; // @[tlb.scala:58:79]
wire _normal_entries_T_137; // @[tlb.scala:58:79]
wire _normal_entries_T_136; // @[tlb.scala:58:79]
wire _normal_entries_T_135; // @[tlb.scala:58:79]
wire _normal_entries_T_134; // @[tlb.scala:58:79]
wire _normal_entries_T_133; // @[tlb.scala:58:79]
wire _normal_entries_T_132; // @[tlb.scala:58:79]
wire _normal_entries_T_131; // @[tlb.scala:58:79]
wire _normal_entries_T_130; // @[tlb.scala:58:79]
wire _normal_entries_T_129; // @[tlb.scala:58:79]
wire _normal_entries_T_128; // @[tlb.scala:58:79]
assign _normal_entries_T_128 = _normal_entries_WIRE_17[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_fragmented_superpage = _normal_entries_T_128; // @[tlb.scala:58:79]
assign _normal_entries_T_129 = _normal_entries_WIRE_17[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_c = _normal_entries_T_129; // @[tlb.scala:58:79]
assign _normal_entries_T_130 = _normal_entries_WIRE_17[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_eff = _normal_entries_T_130; // @[tlb.scala:58:79]
assign _normal_entries_T_131 = _normal_entries_WIRE_17[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_paa = _normal_entries_T_131; // @[tlb.scala:58:79]
assign _normal_entries_T_132 = _normal_entries_WIRE_17[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_pal = _normal_entries_T_132; // @[tlb.scala:58:79]
assign _normal_entries_T_133 = _normal_entries_WIRE_17[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_pr = _normal_entries_T_133; // @[tlb.scala:58:79]
assign _normal_entries_T_134 = _normal_entries_WIRE_17[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_px = _normal_entries_T_134; // @[tlb.scala:58:79]
assign _normal_entries_T_135 = _normal_entries_WIRE_17[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_pw = _normal_entries_T_135; // @[tlb.scala:58:79]
assign _normal_entries_T_136 = _normal_entries_WIRE_17[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_sr = _normal_entries_T_136; // @[tlb.scala:58:79]
assign _normal_entries_T_137 = _normal_entries_WIRE_17[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_sx = _normal_entries_T_137; // @[tlb.scala:58:79]
assign _normal_entries_T_138 = _normal_entries_WIRE_17[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_sw = _normal_entries_T_138; // @[tlb.scala:58:79]
assign _normal_entries_T_139 = _normal_entries_WIRE_17[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_ae = _normal_entries_T_139; // @[tlb.scala:58:79]
assign _normal_entries_T_140 = _normal_entries_WIRE_17[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_g = _normal_entries_T_140; // @[tlb.scala:58:79]
assign _normal_entries_T_141 = _normal_entries_WIRE_17[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_16_u = _normal_entries_T_141; // @[tlb.scala:58:79]
assign _normal_entries_T_142 = _normal_entries_WIRE_17[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_16_ppn = _normal_entries_T_142; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_157; // @[tlb.scala:58:79]
wire _normal_entries_T_156; // @[tlb.scala:58:79]
wire _normal_entries_T_155; // @[tlb.scala:58:79]
wire _normal_entries_T_154; // @[tlb.scala:58:79]
wire _normal_entries_T_153; // @[tlb.scala:58:79]
wire _normal_entries_T_152; // @[tlb.scala:58:79]
wire _normal_entries_T_151; // @[tlb.scala:58:79]
wire _normal_entries_T_150; // @[tlb.scala:58:79]
wire _normal_entries_T_149; // @[tlb.scala:58:79]
wire _normal_entries_T_148; // @[tlb.scala:58:79]
wire _normal_entries_T_147; // @[tlb.scala:58:79]
wire _normal_entries_T_146; // @[tlb.scala:58:79]
wire _normal_entries_T_145; // @[tlb.scala:58:79]
wire _normal_entries_T_144; // @[tlb.scala:58:79]
wire _normal_entries_T_143; // @[tlb.scala:58:79]
assign _normal_entries_T_143 = _normal_entries_WIRE_19[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_fragmented_superpage = _normal_entries_T_143; // @[tlb.scala:58:79]
assign _normal_entries_T_144 = _normal_entries_WIRE_19[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_c = _normal_entries_T_144; // @[tlb.scala:58:79]
assign _normal_entries_T_145 = _normal_entries_WIRE_19[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_eff = _normal_entries_T_145; // @[tlb.scala:58:79]
assign _normal_entries_T_146 = _normal_entries_WIRE_19[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_paa = _normal_entries_T_146; // @[tlb.scala:58:79]
assign _normal_entries_T_147 = _normal_entries_WIRE_19[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_pal = _normal_entries_T_147; // @[tlb.scala:58:79]
assign _normal_entries_T_148 = _normal_entries_WIRE_19[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_pr = _normal_entries_T_148; // @[tlb.scala:58:79]
assign _normal_entries_T_149 = _normal_entries_WIRE_19[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_px = _normal_entries_T_149; // @[tlb.scala:58:79]
assign _normal_entries_T_150 = _normal_entries_WIRE_19[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_pw = _normal_entries_T_150; // @[tlb.scala:58:79]
assign _normal_entries_T_151 = _normal_entries_WIRE_19[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_sr = _normal_entries_T_151; // @[tlb.scala:58:79]
assign _normal_entries_T_152 = _normal_entries_WIRE_19[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_sx = _normal_entries_T_152; // @[tlb.scala:58:79]
assign _normal_entries_T_153 = _normal_entries_WIRE_19[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_sw = _normal_entries_T_153; // @[tlb.scala:58:79]
assign _normal_entries_T_154 = _normal_entries_WIRE_19[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_ae = _normal_entries_T_154; // @[tlb.scala:58:79]
assign _normal_entries_T_155 = _normal_entries_WIRE_19[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_g = _normal_entries_T_155; // @[tlb.scala:58:79]
assign _normal_entries_T_156 = _normal_entries_WIRE_19[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_18_u = _normal_entries_T_156; // @[tlb.scala:58:79]
assign _normal_entries_T_157 = _normal_entries_WIRE_19[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_18_ppn = _normal_entries_T_157; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_172; // @[tlb.scala:58:79]
wire _normal_entries_T_171; // @[tlb.scala:58:79]
wire _normal_entries_T_170; // @[tlb.scala:58:79]
wire _normal_entries_T_169; // @[tlb.scala:58:79]
wire _normal_entries_T_168; // @[tlb.scala:58:79]
wire _normal_entries_T_167; // @[tlb.scala:58:79]
wire _normal_entries_T_166; // @[tlb.scala:58:79]
wire _normal_entries_T_165; // @[tlb.scala:58:79]
wire _normal_entries_T_164; // @[tlb.scala:58:79]
wire _normal_entries_T_163; // @[tlb.scala:58:79]
wire _normal_entries_T_162; // @[tlb.scala:58:79]
wire _normal_entries_T_161; // @[tlb.scala:58:79]
wire _normal_entries_T_160; // @[tlb.scala:58:79]
wire _normal_entries_T_159; // @[tlb.scala:58:79]
wire _normal_entries_T_158; // @[tlb.scala:58:79]
assign _normal_entries_T_158 = _normal_entries_WIRE_21[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_fragmented_superpage = _normal_entries_T_158; // @[tlb.scala:58:79]
assign _normal_entries_T_159 = _normal_entries_WIRE_21[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_c = _normal_entries_T_159; // @[tlb.scala:58:79]
assign _normal_entries_T_160 = _normal_entries_WIRE_21[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_eff = _normal_entries_T_160; // @[tlb.scala:58:79]
assign _normal_entries_T_161 = _normal_entries_WIRE_21[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_paa = _normal_entries_T_161; // @[tlb.scala:58:79]
assign _normal_entries_T_162 = _normal_entries_WIRE_21[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_pal = _normal_entries_T_162; // @[tlb.scala:58:79]
assign _normal_entries_T_163 = _normal_entries_WIRE_21[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_pr = _normal_entries_T_163; // @[tlb.scala:58:79]
assign _normal_entries_T_164 = _normal_entries_WIRE_21[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_px = _normal_entries_T_164; // @[tlb.scala:58:79]
assign _normal_entries_T_165 = _normal_entries_WIRE_21[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_pw = _normal_entries_T_165; // @[tlb.scala:58:79]
assign _normal_entries_T_166 = _normal_entries_WIRE_21[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_sr = _normal_entries_T_166; // @[tlb.scala:58:79]
assign _normal_entries_T_167 = _normal_entries_WIRE_21[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_sx = _normal_entries_T_167; // @[tlb.scala:58:79]
assign _normal_entries_T_168 = _normal_entries_WIRE_21[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_sw = _normal_entries_T_168; // @[tlb.scala:58:79]
assign _normal_entries_T_169 = _normal_entries_WIRE_21[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_ae = _normal_entries_T_169; // @[tlb.scala:58:79]
assign _normal_entries_T_170 = _normal_entries_WIRE_21[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_g = _normal_entries_T_170; // @[tlb.scala:58:79]
assign _normal_entries_T_171 = _normal_entries_WIRE_21[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_20_u = _normal_entries_T_171; // @[tlb.scala:58:79]
assign _normal_entries_T_172 = _normal_entries_WIRE_21[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_20_ppn = _normal_entries_T_172; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_T_187; // @[tlb.scala:58:79]
wire _normal_entries_T_186; // @[tlb.scala:58:79]
wire _normal_entries_T_185; // @[tlb.scala:58:79]
wire _normal_entries_T_184; // @[tlb.scala:58:79]
wire _normal_entries_T_183; // @[tlb.scala:58:79]
wire _normal_entries_T_182; // @[tlb.scala:58:79]
wire _normal_entries_T_181; // @[tlb.scala:58:79]
wire _normal_entries_T_180; // @[tlb.scala:58:79]
wire _normal_entries_T_179; // @[tlb.scala:58:79]
wire _normal_entries_T_178; // @[tlb.scala:58:79]
wire _normal_entries_T_177; // @[tlb.scala:58:79]
wire _normal_entries_T_176; // @[tlb.scala:58:79]
wire _normal_entries_T_175; // @[tlb.scala:58:79]
wire _normal_entries_T_174; // @[tlb.scala:58:79]
wire _normal_entries_T_173; // @[tlb.scala:58:79]
assign _normal_entries_T_173 = _normal_entries_WIRE_23[0]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_fragmented_superpage = _normal_entries_T_173; // @[tlb.scala:58:79]
assign _normal_entries_T_174 = _normal_entries_WIRE_23[1]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_c = _normal_entries_T_174; // @[tlb.scala:58:79]
assign _normal_entries_T_175 = _normal_entries_WIRE_23[2]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_eff = _normal_entries_T_175; // @[tlb.scala:58:79]
assign _normal_entries_T_176 = _normal_entries_WIRE_23[3]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_paa = _normal_entries_T_176; // @[tlb.scala:58:79]
assign _normal_entries_T_177 = _normal_entries_WIRE_23[4]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_pal = _normal_entries_T_177; // @[tlb.scala:58:79]
assign _normal_entries_T_178 = _normal_entries_WIRE_23[5]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_pr = _normal_entries_T_178; // @[tlb.scala:58:79]
assign _normal_entries_T_179 = _normal_entries_WIRE_23[6]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_px = _normal_entries_T_179; // @[tlb.scala:58:79]
assign _normal_entries_T_180 = _normal_entries_WIRE_23[7]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_pw = _normal_entries_T_180; // @[tlb.scala:58:79]
assign _normal_entries_T_181 = _normal_entries_WIRE_23[8]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_sr = _normal_entries_T_181; // @[tlb.scala:58:79]
assign _normal_entries_T_182 = _normal_entries_WIRE_23[9]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_sx = _normal_entries_T_182; // @[tlb.scala:58:79]
assign _normal_entries_T_183 = _normal_entries_WIRE_23[10]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_sw = _normal_entries_T_183; // @[tlb.scala:58:79]
assign _normal_entries_T_184 = _normal_entries_WIRE_23[11]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_ae = _normal_entries_T_184; // @[tlb.scala:58:79]
assign _normal_entries_T_185 = _normal_entries_WIRE_23[12]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_g = _normal_entries_T_185; // @[tlb.scala:58:79]
assign _normal_entries_T_186 = _normal_entries_WIRE_23[13]; // @[tlb.scala:58:79]
wire _normal_entries_WIRE_22_u = _normal_entries_T_186; // @[tlb.scala:58:79]
assign _normal_entries_T_187 = _normal_entries_WIRE_23[33:14]; // @[tlb.scala:58:79]
wire [19:0] _normal_entries_WIRE_22_ppn = _normal_entries_T_187; // @[tlb.scala:58:79]
wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_u = _normal_entries_WIRE_24_0_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_g = _normal_entries_WIRE_24_0_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_ae = _normal_entries_WIRE_24_0_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_sw = _normal_entries_WIRE_24_0_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_sx = _normal_entries_WIRE_24_0_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_sr = _normal_entries_WIRE_24_0_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_pw = _normal_entries_WIRE_24_0_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_px = _normal_entries_WIRE_24_0_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_pr = _normal_entries_WIRE_24_0_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_pal = _normal_entries_WIRE_24_0_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_paa = _normal_entries_WIRE_24_0_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_eff = _normal_entries_WIRE_24_0_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_c = _normal_entries_WIRE_24_0_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_u = _normal_entries_WIRE_24_1_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_g = _normal_entries_WIRE_24_1_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_ae = _normal_entries_WIRE_24_1_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_sw = _normal_entries_WIRE_24_1_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_sx = _normal_entries_WIRE_24_1_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_sr = _normal_entries_WIRE_24_1_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_pw = _normal_entries_WIRE_24_1_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_px = _normal_entries_WIRE_24_1_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_pr = _normal_entries_WIRE_24_1_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_pal = _normal_entries_WIRE_24_1_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_paa = _normal_entries_WIRE_24_1_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_eff = _normal_entries_WIRE_24_1_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_c = _normal_entries_WIRE_24_1_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_u = _normal_entries_WIRE_24_2_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_g = _normal_entries_WIRE_24_2_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_ae = _normal_entries_WIRE_24_2_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_sw = _normal_entries_WIRE_24_2_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_sx = _normal_entries_WIRE_24_2_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_sr = _normal_entries_WIRE_24_2_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_pw = _normal_entries_WIRE_24_2_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_px = _normal_entries_WIRE_24_2_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_pr = _normal_entries_WIRE_24_2_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_pal = _normal_entries_WIRE_24_2_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_paa = _normal_entries_WIRE_24_2_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_eff = _normal_entries_WIRE_24_2_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_c = _normal_entries_WIRE_24_2_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_u = _normal_entries_WIRE_24_3_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_g = _normal_entries_WIRE_24_3_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_ae = _normal_entries_WIRE_24_3_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_sw = _normal_entries_WIRE_24_3_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_sx = _normal_entries_WIRE_24_3_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_sr = _normal_entries_WIRE_24_3_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_pw = _normal_entries_WIRE_24_3_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_px = _normal_entries_WIRE_24_3_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_pr = _normal_entries_WIRE_24_3_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_pal = _normal_entries_WIRE_24_3_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_paa = _normal_entries_WIRE_24_3_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_eff = _normal_entries_WIRE_24_3_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_c = _normal_entries_WIRE_24_3_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_u = _normal_entries_WIRE_24_4_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_g = _normal_entries_WIRE_24_4_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_ae = _normal_entries_WIRE_24_4_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_sw = _normal_entries_WIRE_24_4_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_sx = _normal_entries_WIRE_24_4_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_sr = _normal_entries_WIRE_24_4_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_pw = _normal_entries_WIRE_24_4_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_px = _normal_entries_WIRE_24_4_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_pr = _normal_entries_WIRE_24_4_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_pal = _normal_entries_WIRE_24_4_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_paa = _normal_entries_WIRE_24_4_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_eff = _normal_entries_WIRE_24_4_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_c = _normal_entries_WIRE_24_4_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_u = _normal_entries_WIRE_24_5_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_g = _normal_entries_WIRE_24_5_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_ae = _normal_entries_WIRE_24_5_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_sw = _normal_entries_WIRE_24_5_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_sx = _normal_entries_WIRE_24_5_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_sr = _normal_entries_WIRE_24_5_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_pw = _normal_entries_WIRE_24_5_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_px = _normal_entries_WIRE_24_5_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_pr = _normal_entries_WIRE_24_5_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_pal = _normal_entries_WIRE_24_5_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_paa = _normal_entries_WIRE_24_5_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_eff = _normal_entries_WIRE_24_5_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_c = _normal_entries_WIRE_24_5_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_6_ppn = _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_u = _normal_entries_WIRE_24_6_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_g = _normal_entries_WIRE_24_6_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_ae = _normal_entries_WIRE_24_6_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_sw = _normal_entries_WIRE_24_6_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_sx = _normal_entries_WIRE_24_6_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_sr = _normal_entries_WIRE_24_6_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_pw = _normal_entries_WIRE_24_6_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_px = _normal_entries_WIRE_24_6_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_pr = _normal_entries_WIRE_24_6_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_pal = _normal_entries_WIRE_24_6_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_paa = _normal_entries_WIRE_24_6_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_eff = _normal_entries_WIRE_24_6_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_c = _normal_entries_WIRE_24_6_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_6_fragmented_superpage = _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_7_ppn = _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_u = _normal_entries_WIRE_24_7_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_g = _normal_entries_WIRE_24_7_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_ae = _normal_entries_WIRE_24_7_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_sw = _normal_entries_WIRE_24_7_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_sx = _normal_entries_WIRE_24_7_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_sr = _normal_entries_WIRE_24_7_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_pw = _normal_entries_WIRE_24_7_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_px = _normal_entries_WIRE_24_7_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_pr = _normal_entries_WIRE_24_7_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_pal = _normal_entries_WIRE_24_7_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_paa = _normal_entries_WIRE_24_7_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_eff = _normal_entries_WIRE_24_7_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_c = _normal_entries_WIRE_24_7_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_7_fragmented_superpage = _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_8_ppn = _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_u = _normal_entries_WIRE_24_8_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_g = _normal_entries_WIRE_24_8_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_ae = _normal_entries_WIRE_24_8_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_sw = _normal_entries_WIRE_24_8_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_sx = _normal_entries_WIRE_24_8_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_sr = _normal_entries_WIRE_24_8_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_pw = _normal_entries_WIRE_24_8_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_px = _normal_entries_WIRE_24_8_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_pr = _normal_entries_WIRE_24_8_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_pal = _normal_entries_WIRE_24_8_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_paa = _normal_entries_WIRE_24_8_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_eff = _normal_entries_WIRE_24_8_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_c = _normal_entries_WIRE_24_8_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_8_fragmented_superpage = _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_9_ppn = _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_u = _normal_entries_WIRE_24_9_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_g = _normal_entries_WIRE_24_9_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_ae = _normal_entries_WIRE_24_9_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_sw = _normal_entries_WIRE_24_9_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_sx = _normal_entries_WIRE_24_9_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_sr = _normal_entries_WIRE_24_9_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_pw = _normal_entries_WIRE_24_9_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_px = _normal_entries_WIRE_24_9_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_pr = _normal_entries_WIRE_24_9_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_pal = _normal_entries_WIRE_24_9_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_paa = _normal_entries_WIRE_24_9_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_eff = _normal_entries_WIRE_24_9_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_c = _normal_entries_WIRE_24_9_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_9_fragmented_superpage = _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_10_ppn = _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_u = _normal_entries_WIRE_24_10_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_g = _normal_entries_WIRE_24_10_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_ae = _normal_entries_WIRE_24_10_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_sw = _normal_entries_WIRE_24_10_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_sx = _normal_entries_WIRE_24_10_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_sr = _normal_entries_WIRE_24_10_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_pw = _normal_entries_WIRE_24_10_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_px = _normal_entries_WIRE_24_10_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_pr = _normal_entries_WIRE_24_10_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_pal = _normal_entries_WIRE_24_10_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_paa = _normal_entries_WIRE_24_10_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_eff = _normal_entries_WIRE_24_10_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_c = _normal_entries_WIRE_24_10_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_10_fragmented_superpage = _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [19:0] normal_entries_0_11_ppn = _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_u = _normal_entries_WIRE_24_11_u; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_g = _normal_entries_WIRE_24_11_g; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_ae = _normal_entries_WIRE_24_11_ae; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_sw = _normal_entries_WIRE_24_11_sw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_sx = _normal_entries_WIRE_24_11_sx; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_sr = _normal_entries_WIRE_24_11_sr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_pw = _normal_entries_WIRE_24_11_pw; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_px = _normal_entries_WIRE_24_11_px; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_pr = _normal_entries_WIRE_24_11_pr; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_pal = _normal_entries_WIRE_24_11_pal; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_paa = _normal_entries_WIRE_24_11_paa; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_eff = _normal_entries_WIRE_24_11_eff; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_c = _normal_entries_WIRE_24_11_c; // @[tlb.scala:119:49, :212:45]
wire normal_entries_0_11_fragmented_superpage = _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:119:49, :212:45]
wire [1:0] ptw_ae_array_lo_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, entries_0_0_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_lo_hi_hi = {entries_0_5_ae, entries_0_4_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, entries_0_3_ae}; // @[package.scala:45:27]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {entries_0_8_ae, entries_0_7_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, entries_0_6_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_hi_lo = {entries_0_10_ae, entries_0_9_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_hi_hi = {entries_0_12_ae, entries_0_11_ae}; // @[package.scala:45:27]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:119:49, :214:39]
wire [1:0] _GEN_9 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27]
wire [1:0] _GEN_10 = {entries_0_5_u, entries_0_4_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_11 = {entries_0_8_u, entries_0_7_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {entries_0_10_u, entries_0_9_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] _GEN_13 = {entries_0_12_u, entries_0_11_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3; // @[tlb.scala:215:{39,103}]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:119:49, :215:103]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_3 = _priv_x_ok_T_2; // @[package.scala:45:27]
wire [12:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:119:49, :216:39]
wire [1:0] r_array_lo_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, entries_0_0_sr}; // @[package.scala:45:27]
wire [1:0] r_array_lo_hi_hi = {entries_0_5_sr, entries_0_4_sr}; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, entries_0_3_sr}; // @[package.scala:45:27]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {entries_0_8_sr, entries_0_7_sr}; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, entries_0_6_sr}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_lo = {entries_0_10_sr, entries_0_9_sr}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_hi = {entries_0_12_sr, entries_0_11_sr}; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_14 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_14; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {entries_0_5_sx, entries_0_4_sx}; // @[package.scala:45:27]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_15; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, entries_0_3_sx}; // @[package.scala:45:27]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_16 = {entries_0_8_sx, entries_0_7_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_16; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, entries_0_6_sx}; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {entries_0_10_sx, entries_0_9_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_17; // @[package.scala:45:27]
wire [1:0] _GEN_18 = {entries_0_12_sx, entries_0_11_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_18; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:119:49, :217:{62,93}]
wire [13:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:217:{39,62}]
wire [13:0] r_array_0 = _r_array_T_5; // @[tlb.scala:119:49, :217:39]
wire [1:0] w_array_lo_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, entries_0_0_sw}; // @[package.scala:45:27]
wire [1:0] w_array_lo_hi_hi = {entries_0_5_sw, entries_0_4_sw}; // @[package.scala:45:27]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, entries_0_3_sw}; // @[package.scala:45:27]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {entries_0_8_sw, entries_0_7_sw}; // @[package.scala:45:27]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, entries_0_6_sw}; // @[package.scala:45:27]
wire [1:0] w_array_hi_hi_lo = {entries_0_10_sw, entries_0_9_sw}; // @[package.scala:45:27]
wire [1:0] w_array_hi_hi_hi = {entries_0_12_sw, entries_0_11_sw}; // @[package.scala:45:27]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27]
wire [13:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:218:{39,62}]
wire [13:0] w_array_0 = _w_array_T_2; // @[tlb.scala:119:49, :218:39]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, entries_0_0_sx}; // @[package.scala:45:27]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, entries_0_3_sx}; // @[package.scala:45:27]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, entries_0_6_sx}; // @[package.scala:45:27]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27]
wire [13:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:219:{39,62}]
wire [13:0] x_array_0 = _x_array_T_2; // @[tlb.scala:119:49, :219:39]
wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:119:49, :220:44]
wire [1:0] pr_array_lo_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27]
wire [1:0] pr_array_lo_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {normal_entries_0_8_pr, normal_entries_0_7_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, normal_entries_0_6_pr}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_hi_hi = {normal_entries_0_11_pr, normal_entries_0_10_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, normal_entries_0_9_pr}; // @[package.scala:45:27]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116]
wire [13:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:220:{39,114,116}]
wire [13:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:119:49, :220:114]
wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:119:49, :221:44]
wire [1:0] pw_array_lo_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27]
wire [1:0] pw_array_lo_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {normal_entries_0_8_pw, normal_entries_0_7_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, normal_entries_0_6_pw}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_hi_hi = {normal_entries_0_11_pw, normal_entries_0_10_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, normal_entries_0_9_pw}; // @[package.scala:45:27]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :221:116]
wire [13:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:221:{39,114,116}]
wire [13:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:119:49, :221:114]
wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:119:49, :222:44]
wire [1:0] px_array_lo_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27]
wire [1:0] px_array_lo_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {normal_entries_0_8_px, normal_entries_0_7_px}; // @[package.scala:45:27]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, normal_entries_0_6_px}; // @[package.scala:45:27]
wire [1:0] px_array_hi_hi_hi = {normal_entries_0_11_px, normal_entries_0_10_px}; // @[package.scala:45:27]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, normal_entries_0_9_px}; // @[package.scala:45:27]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:119:49, :220:116, :222:116]
wire [13:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:222:{39,114,116}]
wire [13:0] px_array_0 = _px_array_T_4; // @[tlb.scala:119:49, :222:114]
wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:119:49, :223:44]
wire [1:0] eff_array_lo_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27]
wire [1:0] eff_array_lo_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {normal_entries_0_8_eff, normal_entries_0_7_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, normal_entries_0_6_eff}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_hi_hi = {normal_entries_0_11_eff, normal_entries_0_10_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, normal_entries_0_9_eff}; // @[package.scala:45:27]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [13:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:119:49, :223:39]
wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:119:49, :224:44]
wire [1:0] _GEN_19 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_21 = {normal_entries_0_8_c, normal_entries_0_7_c}; // @[package.scala:45:27]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {normal_entries_0_11_c, normal_entries_0_10_c}; // @[package.scala:45:27]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] c_array_0 = _c_array_T_2; // @[tlb.scala:119:49, :224:39]
wire [13:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :227:61]
wire [13:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:119:49, :228:61]
wire [13:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:119:49, :250:38]
wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:119:49, :225:44]
wire [1:0] paa_array_lo_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27]
wire [1:0] paa_array_lo_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {normal_entries_0_8_paa, normal_entries_0_7_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, normal_entries_0_6_paa}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_hi_hi = {normal_entries_0_11_paa, normal_entries_0_10_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, normal_entries_0_9_paa}; // @[package.scala:45:27]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [13:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:119:49, :225:39]
wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:119:49, :226:44]
wire [1:0] pal_array_lo_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27]
wire [1:0] pal_array_lo_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {normal_entries_0_8_pal, normal_entries_0_7_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, normal_entries_0_6_pal}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_hi_hi = {normal_entries_0_11_pal, normal_entries_0_10_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, normal_entries_0_9_pal}; // @[package.scala:45:27]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:119:49, :226:39]
wire [13:0] _paa_array_if_cached_T_1 = paa_array_0 | _paa_array_if_cached_T; // @[tlb.scala:119:49, :227:{56,61}]
wire [13:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:119:49, :227:56]
wire [13:0] _pal_array_if_cached_T_1 = pal_array_0 | _pal_array_if_cached_T; // @[tlb.scala:119:49, :228:{56,61}]
wire [13:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:119:49, :228:56]
wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:119:49, :229:61]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:229:{61,80}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [13:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:119:49, :229:46]
wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:231:89]
wire [33:0] _misaligned_T_3 = {30'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :19:14, :231:{56,89}]
wire _misaligned_T_4 = |_misaligned_T_3; // @[tlb.scala:231:{56,97}]
wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:119:49, :231:97]
wire _GEN_23 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_23; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_24; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_24; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_24; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:119:49, :242:57]
wire _GEN_25 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_25; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_25; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_25; // @[package.scala:16:47]
wire _GEN_26 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_26; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_26; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_26; // @[package.scala:16:47]
wire _GEN_27 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_27; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_27; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_27; // @[package.scala:16:47]
wire _GEN_28 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_28; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_28; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_28; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:119:49, :243:57]
wire _GEN_29 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_29; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_29; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_29; // @[package.scala:16:47]
wire _GEN_30 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_30; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_30; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_31; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_31; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_31; // @[package.scala:16:47]
wire _GEN_32 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_32; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_32; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_33; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_33; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_33; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:119:49, :244:57]
wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire _cmd_read_T_24 = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68]
wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire _cmd_write_T_22 = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76]
wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:119:49, :247:55]
wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :248:51]
wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:119:49, :247:55]
wire [13:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:119:49, :250:38]
wire [13:0] _ae_array_T = misaligned_0 ? eff_array_0 : 14'h0; // @[tlb.scala:119:49, :252:8]
wire [13:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:119:49, :253:24]
wire [13:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 14'h0; // @[tlb.scala:119:49, :253:{8,24}]
wire [13:0] _ae_array_T_3 = _ae_array_T | _ae_array_T_2; // @[tlb.scala:252:{8,43}, :253:8]
wire [13:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:119:49, :252:43]
wire [13:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:119:49, :256:66]
wire [13:0] _ae_ld_array_T_1 = ae_array_0 | _ae_ld_array_T; // @[tlb.scala:119:49, :256:{64,66}]
wire [13:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 14'h0; // @[tlb.scala:119:49, :256:{38,64}]
wire [13:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:119:49, :256:38]
wire [13:0] _io_resp_0_ae_ld_T = ae_ld_array_0; // @[tlb.scala:119:49, :301:46]
wire [13:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:119:49, :258:46]
wire [13:0] _ae_st_array_T_1 = ae_array_0 | _ae_st_array_T; // @[tlb.scala:119:49, :258:{44,46}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 14'h0; // @[tlb.scala:119:49, :258:{8,44}]
wire [13:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:119:49, :259:32]
wire [13:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 14'h0; // @[tlb.scala:119:49, :259:{8,32}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[tlb.scala:258:{8,65}, :259:8]
wire [13:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:119:49, :260:32]
wire [13:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 14'h0; // @[tlb.scala:119:49, :260:{8,32}]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[tlb.scala:258:65, :259:62, :260:8]
wire [13:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:119:49, :259:62]
wire [13:0] _io_resp_0_ae_st_T = ae_st_array_0; // @[tlb.scala:119:49, :302:46]
wire [13:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:119:49, :262:32]
wire [13:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 14'h0; // @[tlb.scala:119:49, :262:{8,32}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:119:49, :263:32]
wire [13:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 14'h0; // @[tlb.scala:119:49, :263:{8,32}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[tlb.scala:262:{8,52}, :263:8]
wire [13:0] _must_alloc_array_T_6 = {14{cmd_lrsc_0}}; // @[tlb.scala:119:49, :264:8]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[tlb.scala:262:52, :263:52, :264:8]
wire [13:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:119:49, :263:52]
wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:119:49, :265:53]
wire [13:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70]
wire [13:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 14'h0; // @[tlb.scala:265:{38,53,70}]
wire [13:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:119:49, :265:38]
wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:119:49, :266:53]
wire [13:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:119:49, :265:70, :266:70]
wire [13:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 14'h0; // @[tlb.scala:266:{38,53,70}]
wire [13:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:119:49, :266:38]
wire [13:0] _pf_ld_array_T = r_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :267:72]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:267:{59,72}]
wire [13:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 14'h0; // @[tlb.scala:119:49, :267:{38,59}]
wire [13:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:119:49, :267:38]
wire [13:0] _pf_st_array_T = w_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :268:72]
wire [13:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:268:{59,72}]
wire [13:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 14'h0; // @[tlb.scala:119:49, :268:{38,59}]
wire [13:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:119:49, :268:38]
wire [13:0] _pf_inst_array_T = x_array_0 | ptw_ae_array_0; // @[tlb.scala:119:49, :269:50]
wire [13:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:269:{37,50}]
wire [13:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:119:49, :269:37]
wire [1:0] lo_lo = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45]
wire [1:0] lo_hi = {sector_hits_0_3, sector_hits_0_2}; // @[OneHot.scala:22:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:22:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18]
wire [1:0] hi_lo = {sector_hits_0_5, sector_hits_0_4}; // @[OneHot.scala:22:45]
wire [1:0] hi_hi = {sector_hits_0_7, sector_hits_0_6}; // @[OneHot.scala:22:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:22:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = ~state_reg_set_left_older_1 & _state_reg_T_3; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 & _state_reg_T_7; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? 3'h0 : _state_reg_T_9; // @[Replacement.scala:196:33, :202:12, :203:16]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = ~state_reg_set_left_older_2 & _state_reg_T_14; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 & _state_reg_T_18; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] lo_3 = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:22:45, :31:18]
wire [1:0] hi_3 = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:22:45, :30:18]
wire [1:0] state_reg_touch_way_sized_1 = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_23 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13]
wire _state_reg_T_27 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23; // @[package.scala:163:13]
wire _state_reg_T_25 = ~_state_reg_T_24; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_26 = ~state_reg_set_left_older_3 & _state_reg_T_25; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_28 = _state_reg_T_27; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_29 = ~_state_reg_T_28; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_30 = state_reg_set_left_older_3 & _state_reg_T_29; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_26}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_31 = {state_reg_hi_3, _state_reg_T_30}; // @[Replacement.scala:202:12, :206:16]
wire [13:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :298:73]
wire _io_resp_0_pf_ld_T_2 = |_io_resp_0_pf_ld_T_1; // @[tlb.scala:298:{73,84}]
assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T_2; // @[tlb.scala:298:{54,84}]
assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :298:54]
wire [13:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :299:80]
wire _io_resp_0_pf_st_T_2 = |_io_resp_0_pf_st_T_1; // @[tlb.scala:299:{80,91}]
assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T_2; // @[tlb.scala:299:{61,91}]
assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :299:61]
wire [13:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :300:58]
wire _io_resp_0_pf_inst_T_1 = |_io_resp_0_pf_inst_T; // @[tlb.scala:300:{58,69}]
assign _io_resp_0_pf_inst_T_2 = _io_resp_0_pf_inst_T_1; // @[tlb.scala:300:{37,69}]
assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :300:37]
wire [13:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & 14'h2000; // @[tlb.scala:119:49, :173:31, :301:{46,63}]
assign _io_resp_0_ae_ld_T_2 = |_io_resp_0_ae_ld_T_1; // @[tlb.scala:301:{63,74}]
assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :301:74]
wire [13:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & 14'h2000; // @[tlb.scala:119:49, :173:31, :302:{46,63}]
assign _io_resp_0_ae_st_T_2 = |_io_resp_0_ae_st_T_1; // @[tlb.scala:302:{63,74}]
assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :302:74]
wire [13:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:119:49, :303:48]
wire [13:0] _io_resp_0_ae_inst_T_1 = _io_resp_0_ae_inst_T; // @[tlb.scala:303:{46,48}]
wire [13:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & 14'h2000; // @[tlb.scala:119:49, :173:31, :303:{46,63}]
assign _io_resp_0_ae_inst_T_3 = |_io_resp_0_ae_inst_T_2; // @[tlb.scala:303:{63,74}]
assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :303:74]
wire [13:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :304:43]
assign _io_resp_0_ma_ld_T_1 = |_io_resp_0_ma_ld_T; // @[tlb.scala:304:{43,54}]
assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :304:54]
wire [13:0] _io_resp_0_ma_st_T = ma_st_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :305:43]
assign _io_resp_0_ma_st_T_1 = |_io_resp_0_ma_st_T; // @[tlb.scala:305:{43,54}]
assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :305:54]
wire [13:0] _io_resp_0_cacheable_T = c_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :307:44]
assign _io_resp_0_cacheable_T_1 = |_io_resp_0_cacheable_T; // @[tlb.scala:307:{44,55}]
assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :307:55]
wire [13:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :308:53]
assign _io_resp_0_must_alloc_T_1 = |_io_resp_0_must_alloc_T; // @[tlb.scala:308:{53,64}]
assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :308:64]
wire [13:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & 14'h2000; // @[tlb.scala:119:49, :173:31, :309:55]
wire _io_resp_0_prefetchable_T_1 = |_io_resp_0_prefetchable_T; // @[tlb.scala:309:{55,66}]
assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:309:{66,70}]
assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :309:70]
assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:119:49, :311:{28,57}]
assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :311:28]
OptimizationBarrier_EntryData_39 mpu_ppn_data_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_mpu_ppn_data_WIRE_ppn), // @[tlb.scala:58:79]
.io_x_u (_mpu_ppn_data_WIRE_u), // @[tlb.scala:58:79]
.io_x_g (_mpu_ppn_data_WIRE_g), // @[tlb.scala:58:79]
.io_x_ae (_mpu_ppn_data_WIRE_ae), // @[tlb.scala:58:79]
.io_x_sw (_mpu_ppn_data_WIRE_sw), // @[tlb.scala:58:79]
.io_x_sx (_mpu_ppn_data_WIRE_sx), // @[tlb.scala:58:79]
.io_x_sr (_mpu_ppn_data_WIRE_sr), // @[tlb.scala:58:79]
.io_x_pw (_mpu_ppn_data_WIRE_pw), // @[tlb.scala:58:79]
.io_x_px (_mpu_ppn_data_WIRE_px), // @[tlb.scala:58:79]
.io_x_pr (_mpu_ppn_data_WIRE_pr), // @[tlb.scala:58:79]
.io_x_pal (_mpu_ppn_data_WIRE_pal), // @[tlb.scala:58:79]
.io_x_paa (_mpu_ppn_data_WIRE_paa), // @[tlb.scala:58:79]
.io_x_eff (_mpu_ppn_data_WIRE_eff), // @[tlb.scala:58:79]
.io_x_c (_mpu_ppn_data_WIRE_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_mpu_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
PMPChecker_s3_1 pmp_0 ( // @[tlb.scala:150:40]
.clock (clock),
.reset (reset),
.io_addr (mpu_physaddr_0[31:0]), // @[tlb.scala:119:49, :152:20]
.io_size (io_req_0_bits_size_0) // @[tlb.scala:17:7]
); // @[tlb.scala:150:40]
OptimizationBarrier_EntryData_40 ppn_data_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_41 ppn_data_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_2_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_2_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_2_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_2_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_2_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_2_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_2_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_2_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_2_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_2_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_2_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_2_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_2_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_2_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_2_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_42 ppn_data_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_4_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_4_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_4_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_4_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_4_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_4_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_4_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_4_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_4_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_4_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_4_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_4_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_4_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_4_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_4_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_43 ppn_data_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_6_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_6_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_6_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_6_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_6_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_6_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_6_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_6_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_6_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_6_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_6_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_6_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_6_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_6_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_6_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_44 ppn_data_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_8_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_8_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_8_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_8_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_8_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_8_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_8_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_8_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_8_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_8_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_8_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_8_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_8_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_8_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_8_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_45 ppn_data_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_10_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_10_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_10_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_10_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_10_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_10_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_10_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_10_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_10_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_10_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_10_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_10_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_10_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_10_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_10_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_46 ppn_data_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_12_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_12_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_12_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_12_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_12_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_12_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_12_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_12_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_12_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_12_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_12_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_12_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_12_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_12_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_12_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_47 ppn_data_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_14_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_14_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_14_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_14_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_14_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_14_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_14_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_14_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_14_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_14_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_14_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_14_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_14_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_14_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_14_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_48 ppn_data_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_16_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_16_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_16_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_16_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_16_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_16_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_16_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_16_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_16_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_16_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_16_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_16_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_16_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_16_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_16_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_49 ppn_data_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_18_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_18_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_18_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_18_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_18_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_18_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_18_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_18_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_18_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_18_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_18_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_18_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_18_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_18_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_18_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_50 ppn_data_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_20_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_20_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_20_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_20_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_20_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_20_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_20_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_20_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_20_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_20_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_20_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_20_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_20_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_20_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_20_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_51 ppn_data_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_22_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_22_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_22_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_22_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_22_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_22_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_22_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_22_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_22_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_22_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_22_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_22_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_22_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_22_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_22_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_52 ppn_data_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_24_ppn), // @[tlb.scala:58:79]
.io_x_u (_ppn_data_WIRE_24_u), // @[tlb.scala:58:79]
.io_x_g (_ppn_data_WIRE_24_g), // @[tlb.scala:58:79]
.io_x_ae (_ppn_data_WIRE_24_ae), // @[tlb.scala:58:79]
.io_x_sw (_ppn_data_WIRE_24_sw), // @[tlb.scala:58:79]
.io_x_sx (_ppn_data_WIRE_24_sx), // @[tlb.scala:58:79]
.io_x_sr (_ppn_data_WIRE_24_sr), // @[tlb.scala:58:79]
.io_x_pw (_ppn_data_WIRE_24_pw), // @[tlb.scala:58:79]
.io_x_px (_ppn_data_WIRE_24_px), // @[tlb.scala:58:79]
.io_x_pr (_ppn_data_WIRE_24_pr), // @[tlb.scala:58:79]
.io_x_pal (_ppn_data_WIRE_24_pal), // @[tlb.scala:58:79]
.io_x_paa (_ppn_data_WIRE_24_paa), // @[tlb.scala:58:79]
.io_x_eff (_ppn_data_WIRE_24_eff), // @[tlb.scala:58:79]
.io_x_c (_ppn_data_WIRE_24_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_24_fragmented_superpage) // @[tlb.scala:58:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_53 entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_0_ppn),
.io_y_u (_entries_WIRE_26_0_u),
.io_y_g (_entries_WIRE_26_0_g),
.io_y_ae (_entries_WIRE_26_0_ae),
.io_y_sw (_entries_WIRE_26_0_sw),
.io_y_sx (_entries_WIRE_26_0_sx),
.io_y_sr (_entries_WIRE_26_0_sr),
.io_y_pw (_entries_WIRE_26_0_pw),
.io_y_px (_entries_WIRE_26_0_px),
.io_y_pr (_entries_WIRE_26_0_pr),
.io_y_pal (_entries_WIRE_26_0_pal),
.io_y_paa (_entries_WIRE_26_0_paa),
.io_y_eff (_entries_WIRE_26_0_eff),
.io_y_c (_entries_WIRE_26_0_c),
.io_y_fragmented_superpage (_entries_WIRE_26_0_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_54 entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_2_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_2_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_2_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_2_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_2_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_2_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_2_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_2_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_2_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_2_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_2_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_2_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_2_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_2_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_1_ppn),
.io_y_u (_entries_WIRE_26_1_u),
.io_y_g (_entries_WIRE_26_1_g),
.io_y_ae (_entries_WIRE_26_1_ae),
.io_y_sw (_entries_WIRE_26_1_sw),
.io_y_sx (_entries_WIRE_26_1_sx),
.io_y_sr (_entries_WIRE_26_1_sr),
.io_y_pw (_entries_WIRE_26_1_pw),
.io_y_px (_entries_WIRE_26_1_px),
.io_y_pr (_entries_WIRE_26_1_pr),
.io_y_pal (_entries_WIRE_26_1_pal),
.io_y_paa (_entries_WIRE_26_1_paa),
.io_y_eff (_entries_WIRE_26_1_eff),
.io_y_c (_entries_WIRE_26_1_c),
.io_y_fragmented_superpage (_entries_WIRE_26_1_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_55 entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_4_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_4_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_4_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_4_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_4_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_4_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_4_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_4_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_4_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_4_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_4_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_4_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_4_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_4_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_2_ppn),
.io_y_u (_entries_WIRE_26_2_u),
.io_y_g (_entries_WIRE_26_2_g),
.io_y_ae (_entries_WIRE_26_2_ae),
.io_y_sw (_entries_WIRE_26_2_sw),
.io_y_sx (_entries_WIRE_26_2_sx),
.io_y_sr (_entries_WIRE_26_2_sr),
.io_y_pw (_entries_WIRE_26_2_pw),
.io_y_px (_entries_WIRE_26_2_px),
.io_y_pr (_entries_WIRE_26_2_pr),
.io_y_pal (_entries_WIRE_26_2_pal),
.io_y_paa (_entries_WIRE_26_2_paa),
.io_y_eff (_entries_WIRE_26_2_eff),
.io_y_c (_entries_WIRE_26_2_c),
.io_y_fragmented_superpage (_entries_WIRE_26_2_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_56 entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_6_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_6_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_6_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_6_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_6_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_6_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_6_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_6_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_6_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_6_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_6_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_6_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_6_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_6_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_3_ppn),
.io_y_u (_entries_WIRE_26_3_u),
.io_y_g (_entries_WIRE_26_3_g),
.io_y_ae (_entries_WIRE_26_3_ae),
.io_y_sw (_entries_WIRE_26_3_sw),
.io_y_sx (_entries_WIRE_26_3_sx),
.io_y_sr (_entries_WIRE_26_3_sr),
.io_y_pw (_entries_WIRE_26_3_pw),
.io_y_px (_entries_WIRE_26_3_px),
.io_y_pr (_entries_WIRE_26_3_pr),
.io_y_pal (_entries_WIRE_26_3_pal),
.io_y_paa (_entries_WIRE_26_3_paa),
.io_y_eff (_entries_WIRE_26_3_eff),
.io_y_c (_entries_WIRE_26_3_c),
.io_y_fragmented_superpage (_entries_WIRE_26_3_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_57 entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_8_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_8_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_8_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_8_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_8_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_8_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_8_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_8_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_8_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_8_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_8_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_8_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_8_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_8_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_4_ppn),
.io_y_u (_entries_WIRE_26_4_u),
.io_y_g (_entries_WIRE_26_4_g),
.io_y_ae (_entries_WIRE_26_4_ae),
.io_y_sw (_entries_WIRE_26_4_sw),
.io_y_sx (_entries_WIRE_26_4_sx),
.io_y_sr (_entries_WIRE_26_4_sr),
.io_y_pw (_entries_WIRE_26_4_pw),
.io_y_px (_entries_WIRE_26_4_px),
.io_y_pr (_entries_WIRE_26_4_pr),
.io_y_pal (_entries_WIRE_26_4_pal),
.io_y_paa (_entries_WIRE_26_4_paa),
.io_y_eff (_entries_WIRE_26_4_eff),
.io_y_c (_entries_WIRE_26_4_c),
.io_y_fragmented_superpage (_entries_WIRE_26_4_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_58 entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_10_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_10_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_10_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_10_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_10_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_10_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_10_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_10_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_10_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_10_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_10_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_10_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_10_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_10_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_5_ppn),
.io_y_u (_entries_WIRE_26_5_u),
.io_y_g (_entries_WIRE_26_5_g),
.io_y_ae (_entries_WIRE_26_5_ae),
.io_y_sw (_entries_WIRE_26_5_sw),
.io_y_sx (_entries_WIRE_26_5_sx),
.io_y_sr (_entries_WIRE_26_5_sr),
.io_y_pw (_entries_WIRE_26_5_pw),
.io_y_px (_entries_WIRE_26_5_px),
.io_y_pr (_entries_WIRE_26_5_pr),
.io_y_pal (_entries_WIRE_26_5_pal),
.io_y_paa (_entries_WIRE_26_5_paa),
.io_y_eff (_entries_WIRE_26_5_eff),
.io_y_c (_entries_WIRE_26_5_c),
.io_y_fragmented_superpage (_entries_WIRE_26_5_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_59 entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_12_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_12_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_12_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_12_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_12_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_12_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_12_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_12_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_12_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_12_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_12_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_12_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_12_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_12_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_6_ppn),
.io_y_u (_entries_WIRE_26_6_u),
.io_y_g (_entries_WIRE_26_6_g),
.io_y_ae (_entries_WIRE_26_6_ae),
.io_y_sw (_entries_WIRE_26_6_sw),
.io_y_sx (_entries_WIRE_26_6_sx),
.io_y_sr (_entries_WIRE_26_6_sr),
.io_y_pw (_entries_WIRE_26_6_pw),
.io_y_px (_entries_WIRE_26_6_px),
.io_y_pr (_entries_WIRE_26_6_pr),
.io_y_pal (_entries_WIRE_26_6_pal),
.io_y_paa (_entries_WIRE_26_6_paa),
.io_y_eff (_entries_WIRE_26_6_eff),
.io_y_c (_entries_WIRE_26_6_c),
.io_y_fragmented_superpage (_entries_WIRE_26_6_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_60 entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_14_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_14_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_14_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_14_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_14_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_14_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_14_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_14_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_14_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_14_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_14_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_14_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_14_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_14_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_7_ppn),
.io_y_u (_entries_WIRE_26_7_u),
.io_y_g (_entries_WIRE_26_7_g),
.io_y_ae (_entries_WIRE_26_7_ae),
.io_y_sw (_entries_WIRE_26_7_sw),
.io_y_sx (_entries_WIRE_26_7_sx),
.io_y_sr (_entries_WIRE_26_7_sr),
.io_y_pw (_entries_WIRE_26_7_pw),
.io_y_px (_entries_WIRE_26_7_px),
.io_y_pr (_entries_WIRE_26_7_pr),
.io_y_pal (_entries_WIRE_26_7_pal),
.io_y_paa (_entries_WIRE_26_7_paa),
.io_y_eff (_entries_WIRE_26_7_eff),
.io_y_c (_entries_WIRE_26_7_c),
.io_y_fragmented_superpage (_entries_WIRE_26_7_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_61 entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_16_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_16_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_16_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_16_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_16_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_16_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_16_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_16_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_16_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_16_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_16_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_16_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_16_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_16_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_8_ppn),
.io_y_u (_entries_WIRE_26_8_u),
.io_y_g (_entries_WIRE_26_8_g),
.io_y_ae (_entries_WIRE_26_8_ae),
.io_y_sw (_entries_WIRE_26_8_sw),
.io_y_sx (_entries_WIRE_26_8_sx),
.io_y_sr (_entries_WIRE_26_8_sr),
.io_y_pw (_entries_WIRE_26_8_pw),
.io_y_px (_entries_WIRE_26_8_px),
.io_y_pr (_entries_WIRE_26_8_pr),
.io_y_pal (_entries_WIRE_26_8_pal),
.io_y_paa (_entries_WIRE_26_8_paa),
.io_y_eff (_entries_WIRE_26_8_eff),
.io_y_c (_entries_WIRE_26_8_c),
.io_y_fragmented_superpage (_entries_WIRE_26_8_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_62 entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_18_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_18_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_18_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_18_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_18_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_18_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_18_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_18_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_18_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_18_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_18_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_18_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_18_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_18_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_9_ppn),
.io_y_u (_entries_WIRE_26_9_u),
.io_y_g (_entries_WIRE_26_9_g),
.io_y_ae (_entries_WIRE_26_9_ae),
.io_y_sw (_entries_WIRE_26_9_sw),
.io_y_sx (_entries_WIRE_26_9_sx),
.io_y_sr (_entries_WIRE_26_9_sr),
.io_y_pw (_entries_WIRE_26_9_pw),
.io_y_px (_entries_WIRE_26_9_px),
.io_y_pr (_entries_WIRE_26_9_pr),
.io_y_pal (_entries_WIRE_26_9_pal),
.io_y_paa (_entries_WIRE_26_9_paa),
.io_y_eff (_entries_WIRE_26_9_eff),
.io_y_c (_entries_WIRE_26_9_c),
.io_y_fragmented_superpage (_entries_WIRE_26_9_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_63 entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_20_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_20_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_20_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_20_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_20_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_20_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_20_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_20_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_20_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_20_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_20_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_20_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_20_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_20_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_10_ppn),
.io_y_u (_entries_WIRE_26_10_u),
.io_y_g (_entries_WIRE_26_10_g),
.io_y_ae (_entries_WIRE_26_10_ae),
.io_y_sw (_entries_WIRE_26_10_sw),
.io_y_sx (_entries_WIRE_26_10_sx),
.io_y_sr (_entries_WIRE_26_10_sr),
.io_y_pw (_entries_WIRE_26_10_pw),
.io_y_px (_entries_WIRE_26_10_px),
.io_y_pr (_entries_WIRE_26_10_pr),
.io_y_pal (_entries_WIRE_26_10_pal),
.io_y_paa (_entries_WIRE_26_10_paa),
.io_y_eff (_entries_WIRE_26_10_eff),
.io_y_c (_entries_WIRE_26_10_c),
.io_y_fragmented_superpage (_entries_WIRE_26_10_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_64 entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_22_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_22_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_22_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_22_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_22_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_22_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_22_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_22_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_22_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_22_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_22_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_22_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_22_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_22_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_11_ppn),
.io_y_u (_entries_WIRE_26_11_u),
.io_y_g (_entries_WIRE_26_11_g),
.io_y_ae (_entries_WIRE_26_11_ae),
.io_y_sw (_entries_WIRE_26_11_sw),
.io_y_sx (_entries_WIRE_26_11_sx),
.io_y_sr (_entries_WIRE_26_11_sr),
.io_y_pw (_entries_WIRE_26_11_pw),
.io_y_px (_entries_WIRE_26_11_px),
.io_y_pr (_entries_WIRE_26_11_pr),
.io_y_pal (_entries_WIRE_26_11_pal),
.io_y_paa (_entries_WIRE_26_11_paa),
.io_y_eff (_entries_WIRE_26_11_eff),
.io_y_c (_entries_WIRE_26_11_c),
.io_y_fragmented_superpage (_entries_WIRE_26_11_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_65 entries_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_24_ppn), // @[tlb.scala:58:79]
.io_x_u (_entries_WIRE_24_u), // @[tlb.scala:58:79]
.io_x_g (_entries_WIRE_24_g), // @[tlb.scala:58:79]
.io_x_ae (_entries_WIRE_24_ae), // @[tlb.scala:58:79]
.io_x_sw (_entries_WIRE_24_sw), // @[tlb.scala:58:79]
.io_x_sx (_entries_WIRE_24_sx), // @[tlb.scala:58:79]
.io_x_sr (_entries_WIRE_24_sr), // @[tlb.scala:58:79]
.io_x_pw (_entries_WIRE_24_pw), // @[tlb.scala:58:79]
.io_x_px (_entries_WIRE_24_px), // @[tlb.scala:58:79]
.io_x_pr (_entries_WIRE_24_pr), // @[tlb.scala:58:79]
.io_x_pal (_entries_WIRE_24_pal), // @[tlb.scala:58:79]
.io_x_paa (_entries_WIRE_24_paa), // @[tlb.scala:58:79]
.io_x_eff (_entries_WIRE_24_eff), // @[tlb.scala:58:79]
.io_x_c (_entries_WIRE_24_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_entries_WIRE_26_12_ppn),
.io_y_u (_entries_WIRE_26_12_u),
.io_y_g (_entries_WIRE_26_12_g),
.io_y_ae (_entries_WIRE_26_12_ae),
.io_y_sw (_entries_WIRE_26_12_sw),
.io_y_sx (_entries_WIRE_26_12_sx),
.io_y_sr (_entries_WIRE_26_12_sr),
.io_y_pw (_entries_WIRE_26_12_pw),
.io_y_px (_entries_WIRE_26_12_px),
.io_y_pr (_entries_WIRE_26_12_pr),
.io_y_pal (_entries_WIRE_26_12_pal),
.io_y_paa (_entries_WIRE_26_12_paa),
.io_y_eff (_entries_WIRE_26_12_eff),
.io_y_c (_entries_WIRE_26_12_c),
.io_y_fragmented_superpage (_entries_WIRE_26_12_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_66 normal_entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_0_ppn),
.io_y_u (_normal_entries_WIRE_24_0_u),
.io_y_g (_normal_entries_WIRE_24_0_g),
.io_y_ae (_normal_entries_WIRE_24_0_ae),
.io_y_sw (_normal_entries_WIRE_24_0_sw),
.io_y_sx (_normal_entries_WIRE_24_0_sx),
.io_y_sr (_normal_entries_WIRE_24_0_sr),
.io_y_pw (_normal_entries_WIRE_24_0_pw),
.io_y_px (_normal_entries_WIRE_24_0_px),
.io_y_pr (_normal_entries_WIRE_24_0_pr),
.io_y_pal (_normal_entries_WIRE_24_0_pal),
.io_y_paa (_normal_entries_WIRE_24_0_paa),
.io_y_eff (_normal_entries_WIRE_24_0_eff),
.io_y_c (_normal_entries_WIRE_24_0_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_0_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_67 normal_entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_2_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_2_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_2_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_2_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_2_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_2_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_2_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_2_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_2_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_2_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_2_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_2_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_2_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_2_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_1_ppn),
.io_y_u (_normal_entries_WIRE_24_1_u),
.io_y_g (_normal_entries_WIRE_24_1_g),
.io_y_ae (_normal_entries_WIRE_24_1_ae),
.io_y_sw (_normal_entries_WIRE_24_1_sw),
.io_y_sx (_normal_entries_WIRE_24_1_sx),
.io_y_sr (_normal_entries_WIRE_24_1_sr),
.io_y_pw (_normal_entries_WIRE_24_1_pw),
.io_y_px (_normal_entries_WIRE_24_1_px),
.io_y_pr (_normal_entries_WIRE_24_1_pr),
.io_y_pal (_normal_entries_WIRE_24_1_pal),
.io_y_paa (_normal_entries_WIRE_24_1_paa),
.io_y_eff (_normal_entries_WIRE_24_1_eff),
.io_y_c (_normal_entries_WIRE_24_1_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_1_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_68 normal_entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_4_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_4_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_4_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_4_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_4_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_4_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_4_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_4_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_4_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_4_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_4_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_4_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_4_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_4_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_2_ppn),
.io_y_u (_normal_entries_WIRE_24_2_u),
.io_y_g (_normal_entries_WIRE_24_2_g),
.io_y_ae (_normal_entries_WIRE_24_2_ae),
.io_y_sw (_normal_entries_WIRE_24_2_sw),
.io_y_sx (_normal_entries_WIRE_24_2_sx),
.io_y_sr (_normal_entries_WIRE_24_2_sr),
.io_y_pw (_normal_entries_WIRE_24_2_pw),
.io_y_px (_normal_entries_WIRE_24_2_px),
.io_y_pr (_normal_entries_WIRE_24_2_pr),
.io_y_pal (_normal_entries_WIRE_24_2_pal),
.io_y_paa (_normal_entries_WIRE_24_2_paa),
.io_y_eff (_normal_entries_WIRE_24_2_eff),
.io_y_c (_normal_entries_WIRE_24_2_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_2_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_69 normal_entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_6_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_6_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_6_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_6_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_6_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_6_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_6_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_6_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_6_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_6_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_6_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_6_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_6_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_6_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_3_ppn),
.io_y_u (_normal_entries_WIRE_24_3_u),
.io_y_g (_normal_entries_WIRE_24_3_g),
.io_y_ae (_normal_entries_WIRE_24_3_ae),
.io_y_sw (_normal_entries_WIRE_24_3_sw),
.io_y_sx (_normal_entries_WIRE_24_3_sx),
.io_y_sr (_normal_entries_WIRE_24_3_sr),
.io_y_pw (_normal_entries_WIRE_24_3_pw),
.io_y_px (_normal_entries_WIRE_24_3_px),
.io_y_pr (_normal_entries_WIRE_24_3_pr),
.io_y_pal (_normal_entries_WIRE_24_3_pal),
.io_y_paa (_normal_entries_WIRE_24_3_paa),
.io_y_eff (_normal_entries_WIRE_24_3_eff),
.io_y_c (_normal_entries_WIRE_24_3_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_3_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_70 normal_entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_8_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_8_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_8_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_8_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_8_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_8_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_8_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_8_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_8_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_8_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_8_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_8_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_8_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_8_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_4_ppn),
.io_y_u (_normal_entries_WIRE_24_4_u),
.io_y_g (_normal_entries_WIRE_24_4_g),
.io_y_ae (_normal_entries_WIRE_24_4_ae),
.io_y_sw (_normal_entries_WIRE_24_4_sw),
.io_y_sx (_normal_entries_WIRE_24_4_sx),
.io_y_sr (_normal_entries_WIRE_24_4_sr),
.io_y_pw (_normal_entries_WIRE_24_4_pw),
.io_y_px (_normal_entries_WIRE_24_4_px),
.io_y_pr (_normal_entries_WIRE_24_4_pr),
.io_y_pal (_normal_entries_WIRE_24_4_pal),
.io_y_paa (_normal_entries_WIRE_24_4_paa),
.io_y_eff (_normal_entries_WIRE_24_4_eff),
.io_y_c (_normal_entries_WIRE_24_4_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_4_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_71 normal_entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_10_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_10_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_10_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_10_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_10_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_10_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_10_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_10_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_10_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_10_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_10_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_10_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_10_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_10_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_5_ppn),
.io_y_u (_normal_entries_WIRE_24_5_u),
.io_y_g (_normal_entries_WIRE_24_5_g),
.io_y_ae (_normal_entries_WIRE_24_5_ae),
.io_y_sw (_normal_entries_WIRE_24_5_sw),
.io_y_sx (_normal_entries_WIRE_24_5_sx),
.io_y_sr (_normal_entries_WIRE_24_5_sr),
.io_y_pw (_normal_entries_WIRE_24_5_pw),
.io_y_px (_normal_entries_WIRE_24_5_px),
.io_y_pr (_normal_entries_WIRE_24_5_pr),
.io_y_pal (_normal_entries_WIRE_24_5_pal),
.io_y_paa (_normal_entries_WIRE_24_5_paa),
.io_y_eff (_normal_entries_WIRE_24_5_eff),
.io_y_c (_normal_entries_WIRE_24_5_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_5_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_72 normal_entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_12_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_12_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_12_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_12_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_12_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_12_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_12_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_12_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_12_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_12_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_12_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_12_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_12_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_12_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_6_ppn),
.io_y_u (_normal_entries_WIRE_24_6_u),
.io_y_g (_normal_entries_WIRE_24_6_g),
.io_y_ae (_normal_entries_WIRE_24_6_ae),
.io_y_sw (_normal_entries_WIRE_24_6_sw),
.io_y_sx (_normal_entries_WIRE_24_6_sx),
.io_y_sr (_normal_entries_WIRE_24_6_sr),
.io_y_pw (_normal_entries_WIRE_24_6_pw),
.io_y_px (_normal_entries_WIRE_24_6_px),
.io_y_pr (_normal_entries_WIRE_24_6_pr),
.io_y_pal (_normal_entries_WIRE_24_6_pal),
.io_y_paa (_normal_entries_WIRE_24_6_paa),
.io_y_eff (_normal_entries_WIRE_24_6_eff),
.io_y_c (_normal_entries_WIRE_24_6_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_6_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_73 normal_entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_14_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_14_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_14_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_14_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_14_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_14_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_14_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_14_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_14_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_14_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_14_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_14_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_14_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_14_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_7_ppn),
.io_y_u (_normal_entries_WIRE_24_7_u),
.io_y_g (_normal_entries_WIRE_24_7_g),
.io_y_ae (_normal_entries_WIRE_24_7_ae),
.io_y_sw (_normal_entries_WIRE_24_7_sw),
.io_y_sx (_normal_entries_WIRE_24_7_sx),
.io_y_sr (_normal_entries_WIRE_24_7_sr),
.io_y_pw (_normal_entries_WIRE_24_7_pw),
.io_y_px (_normal_entries_WIRE_24_7_px),
.io_y_pr (_normal_entries_WIRE_24_7_pr),
.io_y_pal (_normal_entries_WIRE_24_7_pal),
.io_y_paa (_normal_entries_WIRE_24_7_paa),
.io_y_eff (_normal_entries_WIRE_24_7_eff),
.io_y_c (_normal_entries_WIRE_24_7_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_7_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_74 normal_entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_16_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_16_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_16_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_16_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_16_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_16_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_16_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_16_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_16_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_16_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_16_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_16_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_16_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_16_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_8_ppn),
.io_y_u (_normal_entries_WIRE_24_8_u),
.io_y_g (_normal_entries_WIRE_24_8_g),
.io_y_ae (_normal_entries_WIRE_24_8_ae),
.io_y_sw (_normal_entries_WIRE_24_8_sw),
.io_y_sx (_normal_entries_WIRE_24_8_sx),
.io_y_sr (_normal_entries_WIRE_24_8_sr),
.io_y_pw (_normal_entries_WIRE_24_8_pw),
.io_y_px (_normal_entries_WIRE_24_8_px),
.io_y_pr (_normal_entries_WIRE_24_8_pr),
.io_y_pal (_normal_entries_WIRE_24_8_pal),
.io_y_paa (_normal_entries_WIRE_24_8_paa),
.io_y_eff (_normal_entries_WIRE_24_8_eff),
.io_y_c (_normal_entries_WIRE_24_8_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_8_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_75 normal_entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_18_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_18_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_18_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_18_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_18_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_18_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_18_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_18_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_18_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_18_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_18_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_18_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_18_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_18_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_9_ppn),
.io_y_u (_normal_entries_WIRE_24_9_u),
.io_y_g (_normal_entries_WIRE_24_9_g),
.io_y_ae (_normal_entries_WIRE_24_9_ae),
.io_y_sw (_normal_entries_WIRE_24_9_sw),
.io_y_sx (_normal_entries_WIRE_24_9_sx),
.io_y_sr (_normal_entries_WIRE_24_9_sr),
.io_y_pw (_normal_entries_WIRE_24_9_pw),
.io_y_px (_normal_entries_WIRE_24_9_px),
.io_y_pr (_normal_entries_WIRE_24_9_pr),
.io_y_pal (_normal_entries_WIRE_24_9_pal),
.io_y_paa (_normal_entries_WIRE_24_9_paa),
.io_y_eff (_normal_entries_WIRE_24_9_eff),
.io_y_c (_normal_entries_WIRE_24_9_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_9_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_76 normal_entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_20_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_20_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_20_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_20_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_20_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_20_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_20_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_20_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_20_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_20_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_20_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_20_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_20_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_20_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_10_ppn),
.io_y_u (_normal_entries_WIRE_24_10_u),
.io_y_g (_normal_entries_WIRE_24_10_g),
.io_y_ae (_normal_entries_WIRE_24_10_ae),
.io_y_sw (_normal_entries_WIRE_24_10_sw),
.io_y_sx (_normal_entries_WIRE_24_10_sx),
.io_y_sr (_normal_entries_WIRE_24_10_sr),
.io_y_pw (_normal_entries_WIRE_24_10_pw),
.io_y_px (_normal_entries_WIRE_24_10_px),
.io_y_pr (_normal_entries_WIRE_24_10_pr),
.io_y_pal (_normal_entries_WIRE_24_10_pal),
.io_y_paa (_normal_entries_WIRE_24_10_paa),
.io_y_eff (_normal_entries_WIRE_24_10_eff),
.io_y_c (_normal_entries_WIRE_24_10_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_10_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_77 normal_entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_22_ppn), // @[tlb.scala:58:79]
.io_x_u (_normal_entries_WIRE_22_u), // @[tlb.scala:58:79]
.io_x_g (_normal_entries_WIRE_22_g), // @[tlb.scala:58:79]
.io_x_ae (_normal_entries_WIRE_22_ae), // @[tlb.scala:58:79]
.io_x_sw (_normal_entries_WIRE_22_sw), // @[tlb.scala:58:79]
.io_x_sx (_normal_entries_WIRE_22_sx), // @[tlb.scala:58:79]
.io_x_sr (_normal_entries_WIRE_22_sr), // @[tlb.scala:58:79]
.io_x_pw (_normal_entries_WIRE_22_pw), // @[tlb.scala:58:79]
.io_x_px (_normal_entries_WIRE_22_px), // @[tlb.scala:58:79]
.io_x_pr (_normal_entries_WIRE_22_pr), // @[tlb.scala:58:79]
.io_x_pal (_normal_entries_WIRE_22_pal), // @[tlb.scala:58:79]
.io_x_paa (_normal_entries_WIRE_22_paa), // @[tlb.scala:58:79]
.io_x_eff (_normal_entries_WIRE_22_eff), // @[tlb.scala:58:79]
.io_x_c (_normal_entries_WIRE_22_c), // @[tlb.scala:58:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:58:79]
.io_y_ppn (_normal_entries_WIRE_24_11_ppn),
.io_y_u (_normal_entries_WIRE_24_11_u),
.io_y_g (_normal_entries_WIRE_24_11_g),
.io_y_ae (_normal_entries_WIRE_24_11_ae),
.io_y_sw (_normal_entries_WIRE_24_11_sw),
.io_y_sx (_normal_entries_WIRE_24_11_sx),
.io_y_sr (_normal_entries_WIRE_24_11_sr),
.io_y_pw (_normal_entries_WIRE_24_11_pw),
.io_y_px (_normal_entries_WIRE_24_11_px),
.io_y_pr (_normal_entries_WIRE_24_11_pr),
.io_y_pal (_normal_entries_WIRE_24_11_pal),
.io_y_paa (_normal_entries_WIRE_24_11_paa),
.io_y_eff (_normal_entries_WIRE_24_11_eff),
.io_y_c (_normal_entries_WIRE_24_11_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_11_fragmented_superpage)
); // @[package.scala:267:25]
assign io_resp_0_paddr = io_resp_0_paddr_0; // @[tlb.scala:17:7]
assign io_resp_0_pf_ld = io_resp_0_pf_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_pf_st = io_resp_0_pf_st_0; // @[tlb.scala:17:7]
assign io_resp_0_ae_ld = io_resp_0_ae_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_ae_st = io_resp_0_ae_st_0; // @[tlb.scala:17:7]
assign io_resp_0_ma_ld = io_resp_0_ma_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_ma_st = io_resp_0_ma_st_0; // @[tlb.scala:17:7]
assign io_resp_0_cacheable = io_resp_0_cacheable_0; // @[tlb.scala:17:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_63( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File SRAM.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{Device, DeviceRegName, DiplomaticSRAM, HasJustOneSeqMem}
import freechips.rocketchip.util.{CanHaveErrors, ECCParams, property, SECDEDCode}
import freechips.rocketchip.util.DataToAugmentedData
import freechips.rocketchip.util.BooleanToAugmentedBoolean
class TLRAMErrors(val params: ECCParams, val addrBits: Int) extends Bundle with CanHaveErrors {
val correctable = (params.code.canCorrect && params.notifyErrors).option(Valid(UInt(addrBits.W)))
val uncorrectable = (params.code.canDetect && params.notifyErrors).option(Valid(UInt(addrBits.W)))
}
class TLRAM(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
atomics: Boolean = false,
beatBytes: Int = 4,
ecc: ECCParams = ECCParams(),
sramReg: Boolean = false, // drive SRAM data output directly into a register => 1 cycle longer response
val devName: Option[String] = None,
val dtsCompat: Option[Seq[String]] = None,
val devOverride: Option[Device with DeviceRegName] = None
)(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName, dtsCompat, devOverride)
{
val eccBytes = ecc.bytes
val code = ecc.code
require (eccBytes >= 1 && isPow2(eccBytes))
require (beatBytes >= 1 && isPow2(beatBytes))
require (eccBytes <= beatBytes, s"TLRAM eccBytes (${eccBytes}) > beatBytes (${beatBytes}). Use a WidthWidget=>Fragmenter=>SRAM if you need high density and narrow ECC; it will do bursts efficiently")
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = List(address),
resources = resources,
regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
supportsArithmetic = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none,
supportsLogical = if (atomics) TransferSizes(1, beatBytes) else TransferSizes.none,
fifoId = Some(0)).v2copy(name=devName)), // requests are handled in order
beatBytes = beatBytes,
minLatency = 1))) // no bypass needed for this device
val notifyNode = ecc.notifyErrors.option(BundleBridgeSource(() => new TLRAMErrors(ecc, log2Ceil(address.max)).cloneType))
private val outer = this
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with HasJustOneSeqMem {
val (in, edge) = node.in(0)
val indexBits = (outer.address.mask & ~(beatBytes-1)).bitCount
val width = code.width(eccBytes*8)
val lanes = beatBytes/eccBytes
val mem = makeSinglePortedByteWriteSeqMem(
size = BigInt(1) << indexBits,
lanes = lanes,
bits = width)
val eccCode = Some(ecc.code)
val address = outer.address
val laneDataBits = eccBytes * 8
/* This block has a three-stage pipeline
* Stage A is the combinational request from TileLink A channel
* Stage R corresponds to an accepted request
* Stage D registers the result of an SRAM read (if any)
*
* The TileLink D channel response comes from
* - stage D for corected reads or AMOs
* - stage R for everything else
* - However, to increase maximum operating frequency, the
* stage R responses can be configured to come from stage D
*
* For sub-ECC granule writes and atomic operations:
* - stage A sets up the read for the old data value
* - stage R is used to gather the result from SRAM to registers
* - stage D corrects ECC, applies the ALU, and sets up SRAM write
*
* For super-ECC granule writes:
* - stage A sets up the write
*
* For reads:
* - stage A sets up the read
* - stage R drives the uncorrected data with valid based on ECC validity
* - stage D sets up the correction, if any
*
* When stage D needs to perform a write (AMO, sub-ECC write, or ECC correction):
* - there is a WaW or WaR hazard vs. the operation in stage R
* - for sub-ECC writes and atomics, we ensure stage R has a bubble
* - for ECC correction, we cause stage R to be replayed (and reject stage A twice)
* - there is a structural hazard competing with stage A for SRAM access
* - stage D always wins (stage A is rejected)
* - on ECC correction, there is a structural hazard competing with stage R for the response channel
* - stage D always wins (stage R is replayed)
*/
// D stage registers from R
val d_full = RegInit(false.B)
val d_respond = Reg(Bool())
val d_opcode = Reg(UInt(3.W))
val d_param = Reg(UInt(3.W))
val d_size = Reg(UInt(edge.bundle.sizeBits.W))
val d_source = Reg(UInt(edge.bundle.sourceBits.W))
val d_read = Reg(Bool())
val d_atomic = Reg(Bool())
val d_sublane = Reg(Bool())
val d_address = Reg(UInt(edge.bundle.addressBits.W))
val d_mask = Reg(UInt(beatBytes.W))
val d_rmw_data = Reg(UInt((8*beatBytes).W))
val d_poison = Reg(Bool())
val d_raw_data = Reg(Vec(lanes, Bits(width.W)))
// R stage registers from A
val r_full = RegInit(false.B)
val r_opcode = Reg(UInt(3.W))
val r_param = Reg(UInt(3.W))
val r_size = Reg(UInt(edge.bundle.sizeBits.W))
val r_source = Reg(UInt(edge.bundle.sourceBits.W))
val r_read = Reg(Bool())
val r_atomic = Reg(Bool())
val r_sublane = Reg(Bool())
val r_address = Reg(UInt(edge.bundle.addressBits.W))
val r_mask = Reg(UInt(beatBytes.W))
val r_rmw_data = Reg(UInt((8*beatBytes).W))
val r_poison = Reg(Bool())
val r_raw_data = Wire(Vec(lanes, Bits(width.W)))
// Decode raw SRAM output
val d_decoded = d_raw_data.map(lane => code.decode(lane))
val d_corrected = Cat(d_decoded.map(_.corrected).reverse)
val d_uncorrected = Cat(d_decoded.map(_.uncorrected).reverse)
val d_correctable = d_decoded.map(_.correctable)
val d_uncorrectable = d_decoded.map(_.uncorrectable)
val d_need_fix = d_correctable.reduce(_ || _)
val d_lanes = Cat(Seq.tabulate(lanes) { i => d_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse)
val d_lane_error = Cat(d_uncorrectable.reverse) & d_lanes
val d_error = d_lane_error.orR
val r_decoded = r_raw_data.map(lane => code.decode(lane))
val r_corrected = Cat(r_decoded.map(_.corrected).reverse)
val r_uncorrected = Cat(r_decoded.map(_.uncorrected).reverse)
val r_correctable = r_decoded.map(_.correctable)
val r_uncorrectable = r_decoded.map(_.uncorrectable)
val r_need_fix = r_correctable.reduce(_ || _)
val r_lanes = Cat(Seq.tabulate(lanes) { i => r_mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse)
val r_lane_error = Cat(r_uncorrectable.reverse) & r_lanes
val r_error = r_lane_error.orR
// Out-of-band notification of any faults
notifyNode.foreach { nnode =>
nnode.bundle.correctable.foreach { c =>
c.valid := d_need_fix && d_full && (d_atomic || d_read || d_sublane)
c.bits := d_address
}
nnode.bundle.uncorrectable.foreach { u =>
u.valid := d_error && d_full && (d_atomic || d_read || d_sublane)
u.bits := d_address
}
}
// What does D-stage want to write-back?
// Make an ALU if we need one
val d_updated = if (atomics) {
val alu = Module(new Atomics(edge.bundle))
alu.io.write := false.B
alu.io.a.opcode := d_opcode
alu.io.a.param := d_param
alu.io.a.size := d_size
alu.io.a.source := 0.U
alu.io.a.address := 0.U
alu.io.a.data := d_rmw_data
alu.io.a.mask := d_mask
alu.io.a.corrupt := false.B
alu.io.data_in := d_corrected
alu.io.data_out
} else {
Cat(Seq.tabulate(beatBytes) { i =>
val upd = d_mask(i) && !d_read
val rmw = d_rmw_data (8*(i+1)-1, 8*i)
val fix = d_corrected(8*(i+1)-1, 8*i) // safe to use, because D-stage write-back always wins arbitration
Mux(upd, rmw, fix)
}.reverse)
}
// Stage D always wins control of the response channel
val d_win = d_full && d_respond
val d_mux = if (sramReg) true.B else d_win
val out_aad = Mux(d_mux, d_read || d_atomic, r_read || r_atomic)
in.d.bits.opcode := Mux(out_aad, TLMessages.AccessAckData, TLMessages.AccessAck)
in.d.bits.param := 0.U
in.d.bits.size := Mux(d_mux, d_size, r_size)
in.d.bits.source := Mux(d_mux, d_source, r_source)
in.d.bits.sink := 0.U
in.d.bits.denied := false.B
in.d.bits.data := Mux(d_mux, d_corrected, r_uncorrected)
in.d.bits.corrupt := Mux(d_mux, d_error, r_error) && out_aad
val mem_active_valid = Seq(property.CoverBoolean(in.d.valid, Seq("mem_active")))
val data_error = Seq(
property.CoverBoolean(!d_need_fix && !d_error , Seq("no_data_error")),
property.CoverBoolean(d_need_fix && !in.d.bits.corrupt, Seq("data_correctable_error_not_reported")),
property.CoverBoolean(d_error && in.d.bits.corrupt, Seq("data_uncorrectable_error_reported")))
val error_cross_covers = new property.CrossProperty(Seq(mem_active_valid, data_error), Seq(), "Ecc Covers")
property.cover(error_cross_covers)
// Does the D stage want to perform a write?
// It's important this reduce to false.B when eccBytes=1 && atomics=false && canCorrect=false
val d_wb = d_full && (d_sublane || d_atomic || (d_read && d_need_fix))
// Formulate an R response unless there is a data output fix to perform
// It's important this reduce to false.B for sramReg and true.B for !code.canCorrect
val r_respond = !sramReg.B && (!r_need_fix || !(r_read || r_atomic))
// Resolve WaW and WaR hazard when D performs an update (only happens on ECC correction)
// It's important this reduce to false.B unless code.canDetect
val r_replay = RegNext(r_full && d_full && d_read && d_need_fix)
// r_full && d_wb => read ecc fault (we insert a buble for atomic/sublane)
assert (!(r_full && d_wb) || (d_full && d_read && d_need_fix))
// Pipeline control
in.d.valid := (d_full && d_respond) || (r_full && r_respond && !d_wb && !r_replay)
val d_ready = !d_respond || in.d.ready
val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready))
in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane))
// ignore sublane if it is a read or mask is all set
val a_read = in.a.bits.opcode === TLMessages.Get
val a_sublane = if (eccBytes == 1) false.B else
~a_read &&
(((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) ||
in.a.bits.size < log2Ceil(eccBytes).U)
val a_atomic = if (!atomics) false.B else
in.a.bits.opcode === TLMessages.ArithmeticData ||
in.a.bits.opcode === TLMessages.LogicalData
// Forward pipeline stage from R to D
when (d_ready) { d_full := false.B }
when (r_full && r_ready) {
d_full := true.B
d_respond := !r_respond
d_opcode := r_opcode
d_param := r_param
d_size := r_size
d_source := r_source
d_read := r_read
d_atomic := r_atomic
d_sublane := r_sublane
d_address := r_address
d_mask := r_mask
d_rmw_data := r_rmw_data
d_poison := r_poison
d_raw_data := r_raw_data
}
// Forward pipeline stage from A to R
when (r_ready) { r_full := false.B }
when (in.a.fire) {
r_full := true.B
r_sublane := a_sublane
r_opcode := in.a.bits.opcode
r_param := in.a.bits.param
r_size := in.a.bits.size
r_source := in.a.bits.source
r_read := a_read
r_atomic := a_atomic
r_sublane := a_sublane
r_address := in.a.bits.address
r_poison := in.a.bits.corrupt
r_mask := in.a.bits.mask
when (!a_read) { r_rmw_data := in.a.bits.data }
}
// Split data into eccBytes-sized chunks:
val a_data = VecInit(Seq.tabulate(lanes) { i => in.a.bits.data(eccBytes*8*(i+1)-1, eccBytes*8*i) })
val r_data = VecInit(Seq.tabulate(lanes) { i => r_rmw_data(eccBytes*8*(i+1)-1, eccBytes*8*i) })
val d_data = VecInit(Seq.tabulate(lanes) { i => d_updated(8*eccBytes*(i+1)-1, 8*eccBytes*i) })
// Which data chunks get poisoned
val a_poisonv = VecInit(Seq.fill(lanes) { in.a.bits.corrupt })
val r_poisonv = VecInit(Seq.fill(lanes) { r_poison })
val d_poisonv = VecInit(Seq.tabulate(lanes) { i =>
val upd = d_mask(eccBytes*(i+1)-1, eccBytes*i)
(!upd.andR && d_uncorrectable(i)) || d_poison // sub-lane writes should not correct uncorrectable
})
val a_lanes = Cat(Seq.tabulate(lanes) { i => in.a.bits.mask(eccBytes*(i+1)-1, eccBytes*i).orR }.reverse)
// SRAM arbitration
val a_fire = in.a.fire
val a_ren = a_read || a_atomic || a_sublane
val r_ren = r_read || r_atomic || r_sublane
val wen = d_wb || Mux(r_replay, !r_ren, a_fire && !a_ren)
val ren = !wen && (a_fire || r_replay) // help Chisel infer a RW-port
val addr = Mux(d_wb, d_address, Mux(r_replay, r_address, in.a.bits.address))
val sel = Mux(d_wb, d_lanes, Mux(r_replay, r_lanes, a_lanes))
val dat = Mux(d_wb, d_data, Mux(r_replay, r_data, a_data))
val poison = Mux(d_wb, d_poisonv, Mux(r_replay, r_poisonv, a_poisonv))
val coded = VecInit((dat zip poison) map { case (d, p) =>
if (code.canDetect) code.encode(d, p) else code.encode(d)
})
val index = Cat(mask.zip((addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)
r_raw_data := mem.read(index, ren) holdUnless RegNext(ren)
when (wen) { mem.write(index, coded, sel.asBools) }
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
object TLRAM
{
def apply(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
atomics: Boolean = false,
beatBytes: Int = 4,
ecc: ECCParams = ECCParams(),
sramReg: Boolean = false,
devName: Option[String] = None,
)(implicit p: Parameters): TLInwardNode =
{
val ram = LazyModule(new TLRAM(address, cacheable, executable, atomics, beatBytes, ecc, sramReg, devName))
ram.node
}
}
// Synthesizable unit testing
import freechips.rocketchip.unittest._
class TLRAMSimple(ramBeatBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("SRAMSimple"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes, sramReg = sramReg))
ram.node := TLDelayer(0.25) := model.node := fuzz.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMSimpleTest(ramBeatBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMSimple(ramBeatBytes, sramReg, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLRAMECC(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("SRAMSimple"))
val ram = LazyModule(new TLRAM(
AddressSet(0x0, 0x3ff),
atomics = true,
beatBytes = ramBeatBytes,
ecc = ECCParams(bytes = eccBytes, code = new SECDEDCode),
sramReg = sramReg))
ram.node := TLDelayer(0.25) := model.node := fuzz.node
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMECCTest(ramBeatBytes: Int, eccBytes: Int, sramReg: Boolean, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMECC(ramBeatBytes, eccBytes, sramReg, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module TLRAM_ScratchpadBank( // @[SRAM.scala:63:9]
input clock, // @[SRAM.scala:63:9]
input reset, // @[SRAM.scala:63:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [7:0] r_raw_data_7; // @[package.scala:88:63]
wire [7:0] r_raw_data_6; // @[package.scala:88:63]
wire [7:0] r_raw_data_5; // @[package.scala:88:63]
wire [7:0] r_raw_data_4; // @[package.scala:88:63]
wire [7:0] r_raw_data_3; // @[package.scala:88:63]
wire [7:0] r_raw_data_2; // @[package.scala:88:63]
wire [7:0] r_raw_data_1; // @[package.scala:88:63]
wire [7:0] r_raw_data_0; // @[package.scala:88:63]
wire ren; // @[SRAM.scala:306:20]
wire mem_MPORT_1_en; // @[SRAM.scala:305:52]
wire [63:0] _mem_RW0_rdata; // @[DescribedSRAM.scala:17:26]
reg r_full; // @[SRAM.scala:128:30]
reg [1:0] r_size; // @[SRAM.scala:131:26]
reg [9:0] r_source; // @[SRAM.scala:132:26]
reg r_read; // @[SRAM.scala:133:26]
wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_read}; // @[SRAM.scala:133:26, :203:23]
wire nodeIn_a_ready = ~r_full | auto_in_d_ready; // @[SRAM.scala:128:30, :237:{41,49}]
wire a_fire = nodeIn_a_ready & auto_in_a_valid; // @[Decoupled.scala:51:35]
assign mem_MPORT_1_en = a_fire & auto_in_a_bits_opcode != 3'h4; // @[Decoupled.scala:51:35]
assign ren = ~mem_MPORT_1_en & a_fire; // @[Decoupled.scala:51:35]
reg REG; // @[SRAM.scala:317:58]
reg [7:0] r_0; // @[package.scala:88:63]
reg [7:0] r_1; // @[package.scala:88:63]
reg [7:0] r_2; // @[package.scala:88:63]
reg [7:0] r_3; // @[package.scala:88:63]
reg [7:0] r_4; // @[package.scala:88:63]
reg [7:0] r_5; // @[package.scala:88:63]
reg [7:0] r_6; // @[package.scala:88:63]
reg [7:0] r_7; // @[package.scala:88:63]
assign r_raw_data_0 = REG ? _mem_RW0_rdata[7:0] : r_0; // @[package.scala:88:63]
assign r_raw_data_1 = REG ? _mem_RW0_rdata[15:8] : r_1; // @[package.scala:88:63]
assign r_raw_data_2 = REG ? _mem_RW0_rdata[23:16] : r_2; // @[package.scala:88:63]
assign r_raw_data_3 = REG ? _mem_RW0_rdata[31:24] : r_3; // @[package.scala:88:63]
assign r_raw_data_4 = REG ? _mem_RW0_rdata[39:32] : r_4; // @[package.scala:88:63]
assign r_raw_data_5 = REG ? _mem_RW0_rdata[47:40] : r_5; // @[package.scala:88:63]
assign r_raw_data_6 = REG ? _mem_RW0_rdata[55:48] : r_6; // @[package.scala:88:63]
assign r_raw_data_7 = REG ? _mem_RW0_rdata[63:56] : r_7; // @[package.scala:88:63]
always @(posedge clock) begin // @[SRAM.scala:63:9]
if (reset) // @[SRAM.scala:63:9]
r_full <= 1'h0; // @[SRAM.scala:128:30]
else // @[SRAM.scala:63:9]
r_full <= a_fire | ~auto_in_d_ready & r_full; // @[Decoupled.scala:51:35]
if (a_fire) begin // @[Decoupled.scala:51:35]
r_size <= auto_in_a_bits_size; // @[SRAM.scala:131:26]
r_source <= auto_in_a_bits_source; // @[SRAM.scala:132:26]
r_read <= auto_in_a_bits_opcode == 3'h4; // @[SRAM.scala:133:26, :240:35]
end
REG <= ren; // @[SRAM.scala:306:20, :317:58]
if (REG) begin // @[SRAM.scala:317:58]
r_0 <= _mem_RW0_rdata[7:0]; // @[package.scala:88:63]
r_1 <= _mem_RW0_rdata[15:8]; // @[package.scala:88:63]
r_2 <= _mem_RW0_rdata[23:16]; // @[package.scala:88:63]
r_3 <= _mem_RW0_rdata[31:24]; // @[package.scala:88:63]
r_4 <= _mem_RW0_rdata[39:32]; // @[package.scala:88:63]
r_5 <= _mem_RW0_rdata[47:40]; // @[package.scala:88:63]
r_6 <= _mem_RW0_rdata[55:48]; // @[package.scala:88:63]
r_7 <= _mem_RW0_rdata[63:56]; // @[package.scala:88:63]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Scratchpad.scala:
package testchipip.soc
import chisel3._
import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.resources.{DiplomacyUtils}
import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters}
import scala.collection.immutable.{ListMap}
case class BankedScratchpadParams(
base: BigInt,
size: BigInt,
busWhere: TLBusWrapperLocation = SBUS,
banks: Int = 4,
subBanks: Int = 2,
name: String = "banked-scratchpad",
disableMonitors: Boolean = false,
buffer: BufferParams = BufferParams.none,
outerBuffer: BufferParams = BufferParams.none,
dtsEnabled: Boolean = false
)
case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil)
class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
val mask = (subBanks - 1) * p(CacheBlockBytes)
val xbar = TLXbar()
(0 until subBanks).map { sb =>
val ram = LazyModule(new TLRAM(
address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask),
beatBytes = beatBytes,
devOverride = Some(devOverride)) {
override lazy val desiredName = s"TLRAM_ScratchpadBank"
})
ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar
}
override lazy val desiredName = "ScratchpadBank"
}
trait CanHaveBankedScratchpad { this: BaseSubsystem =>
p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) =>
val bus = locateTLBusWrapper(params.busWhere)
require (params.subBanks >= 1)
val name = params.name
val banks = params.banks
val bankStripe = p(CacheBlockBytes)*params.subBanks
val mask = (params.banks-1)*bankStripe
val device = new MemoryDevice {
override def describe(resources: ResourceBindings): Description = {
Description(describeName("memory", resources), ListMap(
"reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList,
"device_type" -> Seq(ResourceString("memory")),
"status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled"))
))
}
}
def genBanks()(implicit p: Parameters) = (0 until banks).map { b =>
val bank = LazyModule(new ScratchpadBank(
params.subBanks,
AddressSet(params.base + bankStripe * b, params.size - 1 - mask),
bus.beatBytes,
device,
params.buffer))
bank.clockNode := bus.fixedClockNode
bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ }
}
if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module ScratchpadBank( // @[ClockDomain.scala:14:9]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_xbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [3:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [27:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [3:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [27:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _ram_auto_in_a_ready; // @[Scratchpad.scala:33:25]
wire _ram_auto_in_d_valid; // @[Scratchpad.scala:33:25]
wire [2:0] _ram_auto_in_d_bits_opcode; // @[Scratchpad.scala:33:25]
wire [1:0] _ram_auto_in_d_bits_size; // @[Scratchpad.scala:33:25]
wire [7:0] _ram_auto_in_d_bits_source; // @[Scratchpad.scala:33:25]
wire [63:0] _ram_auto_in_d_bits_data; // @[Scratchpad.scala:33:25]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__addressC_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__addressC_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__requestCIO_T = 28'h0; // @[Parameters.scala:137:31]
wire [27:0] xbar__requestBOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__requestBOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsBO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__beatsBO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsCI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__beatsCI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__portsBIO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__portsBIO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar_portsBIO_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__portsCOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__portsCOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar_portsCOI_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [3:0] xbar__addressC_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] xbar__addressC_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] xbar__requestBOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] xbar__requestBOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] xbar__requestBOI_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] xbar_requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] xbar__beatsBO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] xbar__beatsBO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] xbar__beatsCI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] xbar__beatsCI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] xbar__portsBIO_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] xbar__portsBIO_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] xbar_portsBIO_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] xbar__portsCOI_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] xbar__portsCOI_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] xbar_portsCOI_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [28:0] xbar__requestAIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestAIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_1 = 29'h0; // @[Parameters.scala:137:41]
wire [28:0] xbar__requestCIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire xbar_auto_anon_in_a_valid = auto_xbar_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_opcode = auto_xbar_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_param = auto_xbar_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_size = auto_xbar_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_a_bits_source = auto_xbar_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_in_a_bits_address = auto_xbar_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_mask = auto_xbar_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_a_bits_data = auto_xbar_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_bits_corrupt = auto_xbar_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_ready = auto_xbar_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_a_ready_0 = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_valid_0 = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_opcode_0 = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_param_0 = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_size_0 = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_source_0 = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_sink_0 = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_denied_0 = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_data_0 = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_corrupt_0 = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [3:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [27:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [27:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [27:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [3:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [28:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [3:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLRAM_ScratchpadBank ram ( // @[Scratchpad.scala:33:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_ram_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_ram_auto_in_d_valid),
.auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_ram_auto_in_d_bits_size),
.auto_in_d_bits_source (_ram_auto_in_d_bits_source),
.auto_in_d_bits_data (_ram_auto_in_d_bits_data)
); // @[Scratchpad.scala:33:25]
TLFragmenter_ScratchpadBank fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_ram_auto_in_a_ready), // @[Scratchpad.scala:33:25]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_ram_auto_in_d_valid), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data) // @[Scratchpad.scala:33:25]
); // @[Fragmenter.scala:345:34]
TLBuffer_a28d64s4k1z3u_1 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (xbar_auto_anon_out_a_ready),
.auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Buffer.scala:75:28]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_param = auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_sink = auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_denied = auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_corrupt = auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_13( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_3( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [24:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [11:0] _expOut_T_6 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [11:0] _expOut_T_9 = 12'hFFF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [11:0] _expOut_T_5 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [11:0] _expOut_T_8 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [11:0] _expOut_T_14 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [11:0] _expOut_T_16 = 12'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [51:0] _fractOut_T_4 = 52'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [12:0] _sAdjustedExp_T = {{3{io_in_sExp_0[9]}}, io_in_sExp_0} + 13'h700; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [11:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[11:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [12:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [55:0] adjustedSig = {io_in_sig_0, 31'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [11:0] _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:136:55]
wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:138:16]
wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire [11:0] _common_expOut_T = sAdjustedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:38]
wire [12:0] _common_expOut_T_1 = {1'h0, _common_expOut_T}; // @[RoundAnyRawFNToRecFN.scala:136:{38,55}]
assign _common_expOut_T_2 = _common_expOut_T_1[11:0]; // @[RoundAnyRawFNToRecFN.scala:136:55]
assign common_expOut = _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :136:55]
wire [51:0] _common_fractOut_T = adjustedSig[54:3]; // @[RoundAnyRawFNToRecFN.scala:114:22, :139:28]
wire [51:0] _common_fractOut_T_1 = adjustedSig[53:2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :140:28]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:138:16, :140:28]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isInfOut = notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:32]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [11:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [11:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [11:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [11:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [11:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [11:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [51:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_55( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_75 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RegMapFIFO.scala:
package sifive.blocks.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.regmapper._
// MSB indicates full status
object NonBlockingEnqueue {
def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val enqWidth = enq.bits.getWidth
val quash = Wire(Bool())
require(enqWidth > 0)
require(regWidth > enqWidth)
Seq(
RegField(enqWidth,
RegReadFn(0.U),
RegWriteFn((valid, data) => {
enq.valid := valid && !quash
enq.bits := data
true.B
}), RegFieldDesc("data", "Transmit data", access=RegFieldAccessType.W)),
RegField(regWidth - enqWidth - 1),
RegField(1,
!enq.ready,
RegWriteFn((valid, data) => {
quash := valid && data(0)
true.B
}), RegFieldDesc("full", "Transmit FIFO full", access=RegFieldAccessType.R, volatile=true)))
}
}
// MSB indicates empty status
object NonBlockingDequeue {
def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val deqWidth = deq.bits.getWidth
require(deqWidth > 0)
require(regWidth > deqWidth)
Seq(
RegField.r(deqWidth,
RegReadFn(ready => {
deq.ready := ready
(true.B, deq.bits)
}), RegFieldDesc("data", "Receive data", volatile=true)),
RegField(regWidth - deqWidth - 1),
RegField.r(1, !deq.valid,
RegFieldDesc("empty", "Receive FIFO empty", volatile=true)))
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File UART.scala:
package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.prci._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util._
/** UART parameters
*
* @param address uart device TL base address
* @param dataBits number of bits in data frame
* @param stopBits number of stop bits
* @param divisorBits width of baud rate divisor
* @param oversample constructs the times of sampling for every data bit
* @param nSamples number of reserved Rx sampling result for decide one data bit
* @param nTxEntries number of entries in fifo between TL bus and Tx
* @param nRxEntries number of entries in fifo between TL bus and Rx
* @param includeFourWire additional CTS/RTS ports for flow control
* @param includeParity parity support
* @param includeIndependentParity Tx and Rx have opposite parity modes
* @param initBaudRate initial baud rate
*
* @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit.
* Calculated in [[UARTAttachParams.attachTo()]]
*
* @example To configure a 8N1 UART with features below:
* {{{
* 8 entries of Tx and Rx fifo
* Baud rate = 115200
* Rx samples each data bit 16 times
* Uses 3 sample result for each data bit
* }}}
* Set the stopBits as below and keep the other parameter unchanged
* {{{
* stopBits = 1
* }}}
*
*/
case class UARTParams(
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
divisorBits: Int = 16,
oversample: Int = 4,
nSamples: Int = 3,
nTxEntries: Int = 8,
nRxEntries: Int = 8,
includeFourWire: Boolean = false,
includeParity: Boolean = false,
includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes
initBaudRate: BigInt = BigInt(115200),
) extends DeviceParams
{
def oversampleFactor = 1 << oversample
require(divisorBits > oversample)
require(oversampleFactor > nSamples)
require((dataBits == 8) || (dataBits == 9))
}
class UARTPortIO(val c: UARTParams) extends Bundle {
val txd = Output(Bool())
val rxd = Input(Bool())
val cts_n = c.includeFourWire.option(Input(Bool()))
val rts_n = c.includeFourWire.option(Output(Bool()))
}
class UARTInterrupts extends Bundle {
val rxwm = Bool()
val txwm = Bool()
}
//abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
/** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters.
*
* ==Component==
* - Tx
* - Tx fifo
* - Rx
* - Rx fifo
* - TL bus to soc
*
* ==IO==
* [[UARTPortIO]]
*
* ==Datapass==
* {{{
* TL bus -> Tx fifo -> Tx
* TL bus <- Rx fifo <- Rx
* }}}
*
* @param divisorInit: number of clk period for one data bit
*/
class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
(implicit p: Parameters)
extends IORegisterRouter(
RegisterRouterParams(
name = "serial",
compat = Seq("sifive,uart0"),
base = c.address,
beatBytes = busWidthBytes),
new UARTPortIO(c))
//with HasInterruptSources {
with HasInterruptSources with HasTLControlRegMap {
def nInterrupts = 1 + c.includeParity.toInt
ResourceBinding {
Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label))
}
require(divisorInit != 0, "UART divisor wasn't initialized during instantiation")
require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit")
lazy val module = new LazyModuleImp(this) {
val txm = Module(new UARTTx(c))
val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries))
val rxm = Module(new UARTRx(c))
val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries))
val div = RegInit(divisorInit.U(c.divisorBits.W))
private val stopCountBits = log2Up(c.stopBits)
private val txCountBits = log2Floor(c.nTxEntries) + 1
private val rxCountBits = log2Floor(c.nRxEntries) + 1
val txen = RegInit(false.B)
val rxen = RegInit(false.B)
val enwire4 = RegInit(false.B)
val invpol = RegInit(false.B)
val enparity = RegInit(false.B)
val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0
val errorparity = RegInit(false.B)
val errie = RegInit(false.B)
val txwm = RegInit(0.U(txCountBits.W))
val rxwm = RegInit(0.U(rxCountBits.W))
val nstop = RegInit(0.U(stopCountBits.W))
val data8or9 = RegInit(true.B)
if (c.includeFourWire){
txm.io.en := txen && (!port.cts_n.get || !enwire4)
txm.io.cts_n.get := port.cts_n.get
}
else
txm.io.en := txen
txm.io.in <> txq.io.deq
txm.io.div := div
txm.io.nstop := nstop
port.txd := txm.io.out
if (c.dataBits == 9) {
txm.io.data8or9.get := data8or9
rxm.io.data8or9.get := data8or9
}
rxm.io.en := rxen
rxm.io.in := port.rxd
rxq.io.enq.valid := rxm.io.out.valid
rxq.io.enq.bits := rxm.io.out.bits
rxm.io.div := div
val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen
port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) }
if (c.includeParity) {
txm.io.enparity.get := enparity
txm.io.parity.get := parity
rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx
rxm.io.enparity.get := enparity
errorparity := rxm.io.errorparity.get || errorparity
interrupts(1) := errorparity && errie
}
val ie = RegInit(0.U.asTypeOf(new UARTInterrupts()))
val ip = Wire(new UARTInterrupts)
ip.txwm := (txq.io.count < txwm)
ip.rxwm := (rxq.io.count > rxwm)
interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
val mapping = Seq(
UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"),
NonBlockingEnqueue(txq.io.enq)),
UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"),
NonBlockingDequeue(rxq.io.deq)),
UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq(
RegField(1, txen,
RegFieldDesc("txen","Transmit enable", reset=Some(0))),
RegField(stopCountBits, nstop,
RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))),
UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen,
RegFieldDesc("rxen","Receive enable", reset=Some(0)))),
UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm,
RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))),
UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm,
RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))),
UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq(
RegField(1, ie.txwm,
RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))),
RegField(1, ie.rxwm,
RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))),
UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq(
RegField.r(1, ip.txwm,
RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)),
RegField.r(1, ip.rxwm,
RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))),
UARTCtrlRegs.div -> Seq(
RegField(c.divisorBits, div,
RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit))))
)
val optionalparity = if (c.includeParity) Seq(
UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq(
RegField(1, enparity,
RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))),
RegField(1, parity,
RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))),
RegField(1, errorparity,
RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))),
RegField(1, errie,
RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil
val optionalwire4 = if (c.includeFourWire) Seq(
UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq(
RegField(1, enwire4,
RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))),
RegField(1, invpol,
RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0)))
))) else Nil
val optional8or9 = if (c.dataBits == 9) Seq(
UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq(
RegField(1, data8or9,
RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil
regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*)
}
}
class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters)
extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap
case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil)
case class UARTAttachParams(
device: UARTParams,
controlWhere: TLBusWrapperLocation = PBUS,
blockerAddr: Option[BigInt] = None,
controlXType: ClockCrossingType = NoCrossing,
intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams
{
def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where {
val name = s"uart_${UART.nextId()}"
val tlbus = where.locateTLBusWrapper(controlWhere)
val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt
val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART")))
val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) }
uart.suggestName(name)
tlbus.coupleTo(s"device_named_$name") { bus =>
val blockerOpt = blockerAddr.map { a =>
val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes)))
tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ }
blocker
}
uartClockDomainWrapper.clockNode := (controlXType match {
case _: SynchronousCrossing =>
tlbus.dtsClk.map(_.bind(uart.device))
tlbus.fixedClockNode
case _: RationalCrossing =>
tlbus.clockNode
case _: AsynchronousCrossing =>
val uartClockGroup = ClockGroup()
uartClockGroup := where.allClockGroupsNode
blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup }
})
(uart.controlXing(controlXType)
:= TLFragmenter(tlbus, Some("UART"))
:= blockerOpt.map { _.node := bus } .getOrElse { bus })
}
(intXType match {
case _: SynchronousCrossing => where.ibus.fromSync
case _: RationalCrossing => where.ibus.fromRational
case _: AsynchronousCrossing => where.ibus.fromAsync
}) := uart.intXing(intXType)
uart
}
}
object UART {
val nextId = { var i = -1; () => { i += 1; i} }
def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = {
val uartNode = node.makeSink()
InModuleBody { uartNode.makeIO()(ValName(name)) }
}
def tieoff(port: UARTPortIO) {
port.rxd := 1.U
if (port.c.includeFourWire) {
port.cts_n.foreach { ct => ct := false.B } // active-low
}
}
def loopback(port: UARTPortIO) {
port.rxd := port.txd
if (port.c.includeFourWire) {
port.cts_n.get := port.rts_n.get
}
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLUART( // @[UART.scala:127:25]
input clock, // @[UART.scala:127:25]
input reset, // @[UART.scala:127:25]
output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_io_out_txd, // @[LazyModuleImp.scala:107:25]
input auto_io_out_rxd // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [12:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire _rxq_io_deq_valid; // @[UART.scala:133:19]
wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19]
wire [3:0] _rxq_io_count; // @[UART.scala:133:19]
wire _rxm_io_out_valid; // @[UART.scala:132:19]
wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19]
wire _txq_io_enq_ready; // @[UART.scala:130:19]
wire _txq_io_deq_valid; // @[UART.scala:130:19]
wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19]
wire [3:0] _txq_io_count; // @[UART.scala:130:19]
wire _txm_io_in_ready; // @[UART.scala:129:19]
wire _txm_io_tx_busy; // @[UART.scala:129:19]
wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25]
wire [12:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25]
wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25]
wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25]
wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25]
wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25]
wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25]
wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25]
wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32]
wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25]
wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire controlXingIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25]
wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25]
wire [12:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25]
wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25]
wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25]
wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25]
wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25]
wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25]
wire controlXingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire ioNodeOut_txd; // @[MixedNode.scala:542:17]
wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25]
wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
wire [12:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
wire auto_io_out_txd_0; // @[UART.scala:127:25]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [12:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [12:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [12:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [12:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [12:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25]
wire _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9]
wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [12:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9]
wire [12:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9]
assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
reg [15:0] div; // @[UART.scala:135:20]
wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24]
reg txen; // @[UART.scala:141:21]
wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24]
reg rxen; // @[UART.scala:142:21]
reg [3:0] txwm; // @[UART.scala:149:21]
reg [3:0] rxwm; // @[UART.scala:150:21]
reg nstop; // @[UART.scala:151:22]
wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49]
wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}]
wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}]
reg ie_rxwm; // @[UART.scala:186:19]
reg ie_txwm; // @[UART.scala:186:19]
wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24]
wire _ip_rxwm_T; // @[UART.scala:190:28]
wire _ip_txwm_T; // @[UART.scala:189:28]
wire ip_rxwm; // @[UART.scala:187:16]
wire ip_txwm; // @[UART.scala:187:16]
assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28]
assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28]
assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28]
assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28]
wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29]
wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53]
assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}]
assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26]
wire quash; // @[RegMapFIFO.scala:11:21]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33]
wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24]
assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26]
wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24]
wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[UART.scala:127:25]
if (reset) begin // @[UART.scala:127:25]
div <= 16'h10F4; // @[UART.scala:135:20]
txen <= 1'h0; // @[UART.scala:141:21]
rxen <= 1'h0; // @[UART.scala:142:21]
txwm <= 4'h0; // @[UART.scala:149:21]
rxwm <= 4'h0; // @[UART.scala:150:21]
nstop <= 1'h0; // @[UART.scala:151:22]
ie_rxwm <= 1'h0; // @[UART.scala:186:19]
ie_txwm <= 1'h0; // @[UART.scala:186:19]
end
else begin // @[UART.scala:127:25]
if (out_f_woready_15) // @[RegisterRouter.scala:87:24]
div <= _out_T_157; // @[RegisterRouter.scala:87:24]
if (out_f_woready_6) // @[RegisterRouter.scala:87:24]
txen <= _out_T_62; // @[RegisterRouter.scala:87:24]
if (out_f_woready_9) // @[RegisterRouter.scala:87:24]
rxen <= _out_T_95; // @[RegisterRouter.scala:87:24]
if (out_f_woready_8) // @[RegisterRouter.scala:87:24]
txwm <= _out_T_84; // @[RegisterRouter.scala:87:24]
if (out_f_woready_10) // @[RegisterRouter.scala:87:24]
rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24]
if (out_f_woready_7) // @[RegisterRouter.scala:87:24]
nstop <= _out_T_73; // @[RegisterRouter.scala:87:24]
if (out_f_woready_12) // @[RegisterRouter.scala:87:24]
ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24]
if (out_f_woready_11) // @[RegisterRouter.scala:87:24]
ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24]
end
always @(posedge)
IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31]
.clock (clock),
.reset (reset),
.auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17]
.auto_out_sync_0 (intXingIn_sync_0)
); // @[Crossing.scala:29:31]
TLMonitor_63 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
UARTTx txm ( // @[UART.scala:129:19]
.clock (clock),
.reset (reset),
.io_en (txen), // @[UART.scala:141:21]
.io_in_ready (_txm_io_in_ready),
.io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19]
.io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19]
.io_out (ioNodeOut_txd),
.io_div (div), // @[UART.scala:135:20]
.io_nstop (nstop), // @[UART.scala:151:22]
.io_tx_busy (_txm_io_tx_busy)
); // @[UART.scala:129:19]
Queue8_UInt8 txq ( // @[UART.scala:130:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30]
.io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19]
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (_txq_io_count)
); // @[UART.scala:130:19]
UARTRx rxm ( // @[UART.scala:132:19]
.clock (clock),
.reset (reset),
.io_en (rxen), // @[UART.scala:142:21]
.io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17]
.io_out_valid (_rxm_io_out_valid),
.io_out_bits (_rxm_io_out_bits),
.io_div (div) // @[UART.scala:135:20]
); // @[UART.scala:132:19]
Queue8_UInt8_1 rxq ( // @[UART.scala:133:19]
.clock (clock),
.reset (reset),
.io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19]
.io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19]
.io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
); // @[UART.scala:133:19]
assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLDToNoC_1( // @[TilelinkAdapters.scala:171:7]
input clock, // @[TilelinkAdapters.scala:171:7]
input reset, // @[TilelinkAdapters.scala:171:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}]
reg [2:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 3'h1 | tail_beats1 == 3'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7]
if (reset) begin // @[TilelinkAdapters.scala:171:7]
head_counter <= 3'h0; // @[Edges.scala:229:27]
tail_counter <= 3'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7]
end
else begin // @[TilelinkAdapters.scala:171:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File DivSqrtRecFN_small.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2017 SiFive, Inc. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of SiFive nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*
s = sigWidth
c_i = newBit
Division:
width of a is (s+2)
Normal
------
(qi + ci * 2^(-i))*b <= a
q0 = 0
r0 = a
q(i+1) = qi + ci*2^(-i)
ri = a - qi*b
r(i+1) = a - q(i+1)*b
= a - qi*b - ci*2^(-i)*b
r(i+1) = ri - ci*2^(-i)*b
ci = ri >= 2^(-i)*b
summary_i = ri != 0
i = 0 to s+1
(s+1)th bit plus summary_(i+1) gives enough information for rounding
If (a < b), then we need to calculate (s+2)th bit and summary_(i+1)
because we need s bits ignoring the leading zero. (This is skipCycle2
part of Hauser's code.)
Hauser
------
sig_i = qi
rem_i = 2^(i-2)*ri
cycle_i = s+3-i
sig_0 = 0
rem_0 = a/4
cycle_0 = s+3
bit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)
sig(i+1) = sig(i) + ci*bit_i
rem(i+1) = 2rem_i - ci*b/2
ci = 2rem_i >= b/2
bit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)
cycle(i+1) = cycle_i-1
summary_1 = a <> b
summary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0
Proof:
2^i*r(i+1) = 2^i*ri - ci*b. Qed
ci = 2^i*ri >= b. Qed
summary(i+1) = if ci then rem(i+1) else summary_i, i <> 0
Now, note that all of ck's cannot be 0, since that means
a is 0. So when you traverse through a chain of 0 ck's,
from the end,
eventually, you reach a non-zero cj. That is exactly the
value of ri as the reminder remains the same. When all ck's
are 0 except c0 (which must be 1) then summary_1 is set
correctly according
to r1 = a-b != 0. So summary(i+1) is always set correctly
according to r(i+1)
Square root:
width of a is (s+1)
Normal
------
(xi + ci*2^(-i))^2 <= a
xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a
x0 = 0
x(i+1) = xi + ci*2^(-i)
ri = a - xi^2
r(i+1) = a - x(i+1)^2
= a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))
= ri - ci*2^(-i)*(2xi+ci*2^(-i))
= ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1
ci = ri >= 2^(-i)*(2xi + 2^(-i))
summary_i = ri != 0
i = 0 to s+1
For odd expression, do 2 steps initially.
(s+1)th bit plus summary_(i+1) gives enough information for rounding.
Hauser
------
sig_i = xi
rem_i = ri*2^(i-1)
cycle_i = s+2-i
bit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)
sig_0 = 0
rem_0 = a/2
cycle_0 = s+2
bit_0 = 1 (= 2^s in terms of bit representation)
sig(i+1) = sig_i + ci * bit_i
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
ci = 2*sig_i + bit_i <= 2*rem_i
bit_i = 2^(cycle_i-2) (in terms of bit representation)
cycle(i+1) = cycle_i-1
summary_1 = a - (2^s) (in terms of bit representation)
summary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0
Proof:
ci = 2*sig_i + bit_i <= 2*rem_i
ci = 2xi + 2^(-i) <= ri*2^i. Qed
sig(i+1) = sig_i + ci * bit_i
x(i+1) = xi + ci*2^(-i). Qed
rem(i+1) = 2rem_i - ci*(2sig_i + bit_i)
r(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))
r(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed
Same argument as before for summary.
------------------------------
Note that all registers are updated normally until cycle == 2.
At cycle == 2, rem is not updated, but all other registers are updated normally.
But, cycle == 1 does not read rem to calculate anything (note that final summary
is calculated using the values at cycle = 2).
*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
/*----------------------------------------------------------------------------
| Computes a division or square root for floating-point in recoded form.
| Multiple clock cycles are needed for each division or square-root operation,
| except possibly in special cases.
*----------------------------------------------------------------------------*/
class
DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))
val inReady = RegInit(true.B) // <-> (cycleNum <= 1)
val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)
val sqrtOp_Z = Reg(Bool())
val majorExc_Z = Reg(Bool())
//*** REDUCE 3 BITS TO 2-BIT CODE:
val isNaN_Z = Reg(Bool())
val isInf_Z = Reg(Bool())
val isZero_Z = Reg(Bool())
val sign_Z = Reg(Bool())
val sExp_Z = Reg(SInt((expWidth + 2).W))
val fractB_Z = Reg(UInt(sigWidth.W))
val roundingMode_Z = Reg(UInt(3.W))
/*------------------------------------------------------------------------
| (The most-significant and least-significant bits of 'rem_Z' are needed
| only for square roots.)
*------------------------------------------------------------------------*/
val rem_Z = Reg(UInt((sigWidth + 2).W))
val notZeroRem_Z = Reg(Bool())
val sigX_Z = Reg(UInt((sigWidth + 2).W))
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rawA_S = io.a
val rawB_S = io.b
//*** IMPROVE THESE:
val notSigNaNIn_invalidExc_S_div =
(rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)
val notSigNaNIn_invalidExc_S_sqrt =
! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign
val majorExc_S =
Mux(io.sqrtOp,
isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,
isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||
notSigNaNIn_invalidExc_S_div ||
(! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)
)
val isNaN_S =
Mux(io.sqrtOp,
rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,
rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div
)
val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)
val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)
val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)
val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero
val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero
val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S
val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign
val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
val sExpQuot_S_div =
rawA_S.sExp +&
Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt
//*** IS THIS OPTIMAL?:
val sSatExpQuot_S_div =
Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),
6.U,
sExpQuot_S_div(expWidth + 1, expWidth - 2)
),
sExpQuot_S_div(expWidth - 3, 0)
).asSInt
val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)
val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val idle = cycleNum === 0.U
val entering = inReady && io.inValid
val entering_normalCase = entering && normalCase_S
val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B
val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B
when (! idle || entering) {
def computeCycleNum(f: UInt => UInt): UInt = {
Mux(entering & ! normalCase_S, f(1.U), 0.U) |
Mux(entering_normalCase,
Mux(io.sqrtOp,
Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),
f((sigWidth + 2).U)
),
0.U
) |
Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |
Mux(skipCycle2, f(1.U), 0.U)
}
inReady := computeCycleNum(_ <= 1.U).asBool
rawOutValid := computeCycleNum(_ === 1.U).asBool
cycleNum := computeCycleNum(x => x)
}
io.inReady := inReady
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
when (entering) {
sqrtOp_Z := io.sqrtOp
majorExc_Z := majorExc_S
isNaN_Z := isNaN_S
isInf_Z := isInf_S
isZero_Z := isZero_S
sign_Z := sign_S
sExp_Z :=
Mux(io.sqrtOp,
(rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,
sSatExpQuot_S_div
)
roundingMode_Z := io.roundingMode
}
when (entering || ! inReady && sqrtOp_Z) {
fractB_Z :=
Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |
Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |
Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |
Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val rem =
Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |
Mux(inReady && oddSqrt_S,
Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,
rawA_S.sig(sigWidth - 3, 0)<<3
),
0.U
) |
Mux(! inReady, rem_Z<<1, 0.U)
val bitMask = (1.U<<cycleNum)>>2
val trialTerm =
Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |
Mux(inReady && evenSqrt_S, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, (BigInt(5)<<(sigWidth - 1)).U, 0.U) |
Mux(! inReady, fractB_Z, 0.U) |
Mux(! inReady && ! sqrtOp_Z, 1.U << sigWidth, 0.U) |
Mux(! inReady && sqrtOp_Z, sigX_Z<<1, 0.U)
val trialRem = rem.zext -& trialTerm.zext
val newBit = (0.S <= trialRem)
val nextRem_Z = Mux(newBit, trialRem.asUInt, rem)(sigWidth + 1, 0)
val rem2 = nextRem_Z<<1
val trialTerm2_newBit0 = Mux(sqrtOp_Z, fractB_Z>>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))
val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)
val trialRem2 =
Mux(newBit,
(trialRem<<1) - trialTerm2_newBit1.zext,
(rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)
val newBit2 = (0.S <= trialRem2)
val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)
val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)
processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||
processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||
!(processTwoBits && newBit2) && nextNotZeroRem_Z
val nextRem_Z_2 =
Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |
Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |
Mux(!processTwoBits, nextRem_Z, 0.U)
when (entering || ! inReady) {
notZeroRem_Z := nextNotZeroRem_Z_2
rem_Z := nextRem_Z_2
sigX_Z :=
Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |
Mux(inReady && io.sqrtOp, (BigInt(1)<<sigWidth).U, 0.U) |
Mux(inReady && oddSqrt_S, newBit<<(sigWidth - 1), 0.U) |
Mux(! inReady, sigX_Z, 0.U) |
Mux(! inReady && newBit, bitMask, 0.U) |
Mux(processTwoBits && newBit2, bitMask>>1, 0.U)
}
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.rawOutValid_div := rawOutValid && ! sqrtOp_Z
io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z
io.roundingModeOut := roundingMode_Z
io.invalidExc := majorExc_Z && isNaN_Z
io.infiniteExc := majorExc_Z && ! isNaN_Z
io.rawOut.isNaN := isNaN_Z
io.rawOut.isInf := isInf_Z
io.rawOut.isZero := isZero_Z
io.rawOut.sign := sign_Z
io.rawOut.sExp := sExp_Z
io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val rawOutValid_div = Output(Bool())
val rawOutValid_sqrt = Output(Bool())
val roundingModeOut = Output(UInt(3.W))
val invalidExc = Output(Bool())
val infiniteExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val divSqrtRawFN =
Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))
io.inReady := divSqrtRawFN.io.inReady
divSqrtRawFN.io.inValid := io.inValid
divSqrtRawFN.io.sqrtOp := io.sqrtOp
divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
divSqrtRawFN.io.roundingMode := io.roundingMode
io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div
io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt
io.roundingModeOut := divSqrtRawFN.io.roundingModeOut
io.invalidExc := divSqrtRawFN.io.invalidExc
io.infiniteExc := divSqrtRawFN.io.infiniteExc
io.rawOut := divSqrtRawFN.io.rawOut
}
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
class
DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)
extends Module
{
override def desiredName = s"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val inReady = Output(Bool())
val inValid = Input(Bool())
val sqrtOp = Input(Bool())
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
val outValid_div = Output(Bool())
val outValid_sqrt = Output(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val divSqrtRecFNToRaw =
Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))
io.inReady := divSqrtRecFNToRaw.io.inReady
divSqrtRecFNToRaw.io.inValid := io.inValid
divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp
divSqrtRecFNToRaw.io.a := io.a
divSqrtRecFNToRaw.io.b := io.b
divSqrtRecFNToRaw.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div
io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc
roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut
roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module DivSqrtRawFN_small_e5_s11( // @[DivSqrtRecFN_small.scala:199:5]
input clock, // @[DivSqrtRecFN_small.scala:199:5]
input reset, // @[DivSqrtRecFN_small.scala:199:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:203:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:203:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16]
output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16]
output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16]
);
reg [3:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33]
reg inReady; // @[DivSqrtRecFN_small.scala:225:33]
reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33]
reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29]
reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29]
reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29]
reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29]
reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29]
reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29]
reg [6:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29]
reg [10:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29]
reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29]
reg [12:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29]
reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29]
reg [12:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29]
wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero; // @[DivSqrtRecFN_small.scala:273:{39,55}]
wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero); // @[DivSqrtRecFN_small.scala:273:{39,55}, :274:{39,55}, :275:{28,45,48}, :276:{46,49}, :277:27]
wire skipCycle2 = cycleNum == 4'h3 & sigX_Z[12]; // @[DivSqrtRecFN_small.scala:224:33, :245:29, :301:{31,39,48}]
wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf; // @[DivSqrtRecFN_small.scala:254:{24,42,59}]
wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign; // @[DivSqrtRecFN_small.scala:256:{9,24,27,43}]
wire [7:0] sExpQuot_S_div = {io_a_sExp[6], io_a_sExp} + {{3{io_b_sExp[5]}}, ~(io_b_sExp[4:0])}; // @[DivSqrtRecFN_small.scala:280:21, :281:{28,40,52}]
wire [10:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[9:0], 1'h0} : 11'h0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :271:33, :342:{16,25,73,90}]
wire _fractB_Z_T_10 = inReady & io_sqrtOp; // @[DivSqrtRecFN_small.scala:225:33, :343:25]
wire [15:0] _bitMask_T = 16'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23]
wire oddSqrt_S = io_sqrtOp & io_a_sExp[0]; // @[DivSqrtRecFN_small.scala:291:48, :292:32]
wire entering = inReady & io_inValid; // @[DivSqrtRecFN_small.scala:225:33, :297:28]
wire _sigX_Z_T_7 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21]
wire [13:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 13'h0} | (_sigX_Z_T_7 ? {io_a_sig[10:9] - 2'h1, io_a_sig[8:0], 3'h0} : 14'h0) | (inReady ? 14'h0 : {rem_Z, 1'h0}); // @[DivSqrtRecFN_small.scala:199:5, :225:33, :243:29, :292:32, :313:56, :352:{12,21,24,47,57}, :353:{12,21}, :354:{16,27,56}, :355:27, :358:11, :359:{12,29}]
wire [12:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 13'h0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :271:33, :362:{12,21,48}]
wire [12:0] _trialTerm_T_9 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 11'h0}} | (_sigX_Z_T_7 ? 13'h1400 : 13'h0); // @[DivSqrtRecFN_small.scala:225:33, :291:{32,35,48}, :353:21, :362:{12,74}, :363:{12,21,74}, :364:12]
wire [15:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[12], _trialTerm_T_9[11] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[10:0] | (inReady ? 11'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 14'h0)}; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :228:29, :236:29, :245:29, :340:23, :352:57, :358:11, :363:74, :364:74, :365:{12,74}, :366:{23,26,74}, :367:{12,23,44}, :368:29]
wire newBit = $signed(trialRem) > -16'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23]
wire _GEN = entering | ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20]
wire [3:0] _cycleNum_T_15 = {3'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? (io_a_sExp[0] ? 4'hB : 4'hC) : 4'hD) : 4'h0) | (entering | skipCycle2 ? 4'h0 : cycleNum - 4'h1); // @[DivSqrtRecFN_small.scala:224:33, :277:27, :291:48, :297:28, :298:40, :301:39, :305:{26,28,57}, :306:16, :307:20, :308:24, :312:15, :313:{16,56}]
wire [12:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 12'h0} : 13'h0; // @[DivSqrtRecFN_small.scala:225:33, :271:33, :369:23, :394:{16,25,50}]
wire [11:0] _GEN_0 = _sigX_Z_T_3[11:0] | {inReady & io_sqrtOp, 11'h0}; // @[DivSqrtRecFN_small.scala:225:33, :394:{16,74}, :395:{16,25}]
always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5]
if (reset) begin // @[DivSqrtRecFN_small.scala:199:5]
cycleNum <= 4'h0; // @[DivSqrtRecFN_small.scala:224:33]
inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:199:5, :225:33]
rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:199:5, :226:33]
end
else if ((|cycleNum) | entering) begin // @[DivSqrtRecFN_small.scala:224:33, :296:25, :297:28, :303:18]
cycleNum <= {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | skipCycle2}; // @[DivSqrtRecFN_small.scala:224:33, :301:39, :305:57, :312:15, :313:95]
inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 < 4'h2 | skipCycle2; // @[DivSqrtRecFN_small.scala:224:33, :225:33, :277:27, :297:28, :301:39, :305:{26,28}, :312:15, :313:{16,17,28,31,56,95}, :317:38]
rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 == 4'h1 | skipCycle2; // @[DivSqrtRecFN_small.scala:224:33, :226:33, :277:27, :297:28, :301:39, :305:{26,28}, :312:15, :313:{16,17,28,31,56,95}, :318:42]
end
if (entering) begin // @[DivSqrtRecFN_small.scala:297:28]
sqrtOp_Z <= io_sqrtOp; // @[DivSqrtRecFN_small.scala:228:29]
majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[9]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[9]) | io_b_isNaN & ~(io_b_sig[9]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero; // @[common.scala:82:{46,49,56}]
isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:231:29, :254:42, :256:{24,43}, :265:12, :266:26, :267:{26,42}]
isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf; // @[DivSqrtRecFN_small.scala:232:29, :269:23]
isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero; // @[DivSqrtRecFN_small.scala:233:29, :269:23, :270:23]
sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign; // @[DivSqrtRecFN_small.scala:234:29, :271:{30,33,45}]
sExp_Z <= io_sqrtOp ? {io_a_sExp[6], io_a_sExp[6:1]} + 7'h10 : {$signed(sExpQuot_S_div) > 8'sh37 ? 4'h6 : sExpQuot_S_div[6:3], sExpQuot_S_div[2:0]}; // @[DivSqrtRecFN_small.scala:235:29, :280:21, :284:{12,16,48}, :286:31, :288:27, :334:16, :335:{29,34}]
roundingMode_Z <= io_roundingMode; // @[DivSqrtRecFN_small.scala:237:29]
end
if (entering | ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}]
fractB_Z <= {_fractB_Z_T_4[10] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[9:0] | {_fractB_Z_T_10 & io_a_sExp[0], 9'h0} | (inReady ? 10'h0 : fractB_Z[10:1])}; // @[DivSqrtRecFN_small.scala:225:33, :236:29, :291:48, :342:{16,100}, :343:{16,25,38,100}, :344:{38,41}, :345:100, :346:{16,71}]
if (_GEN) begin // @[DivSqrtRecFN_small.scala:390:20]
rem_Z <= newBit ? trialRem[12:0] : rem[12:0]; // @[DivSqrtRecFN_small.scala:243:29, :352:57, :358:11, :368:29, :369:23, :371:24]
sigX_Z <= {_sigX_Z_T_3[12], _GEN_0[11], _GEN_0[10:0] | (_sigX_Z_T_7 ? {newBit, 10'h0} : 11'h0)} | (inReady ? 13'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[14:2] : 13'h0); // @[DivSqrtRecFN_small.scala:225:33, :245:29, :340:23, :353:21, :360:{23,34}, :369:23, :394:{16,74}, :395:74, :396:{16,50,74}, :397:{16,74}, :398:{16,27}]
end
if (_GEN & (inReady | newBit)) // @[DivSqrtRecFN_small.scala:225:33, :244:29, :369:23, :380:{31,40}, :390:{20,34}, :391:22]
notZeroRem_Z <= |trialRem; // @[DivSqrtRecFN_small.scala:244:29, :368:29, :380:60]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_31( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module ClockCrossingReg_w82( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input reset, // @[SynchronizerReg.scala:191:7]
input [81:0] io_d, // @[SynchronizerReg.scala:195:14]
output [81:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
wire [81:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7]
wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7]
wire [81:0] io_q_0; // @[SynchronizerReg.scala:191:7]
reg [81:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en_0) // @[SynchronizerReg.scala:191:7]
cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge)
assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_42( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_42 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File CLINT.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.Annotated
object CLINTConsts
{
def msipOffset(hart: Int) = hart * msipBytes
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes
def timeOffset = 0xbff8
def msipBytes = 4
def timecmpBytes = 8
def size = 0x10000
def timeWidth = 64
def ipiWidth = 32
def ints = 2
}
case class CLINTParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
{
def address = AddressSet(baseAddress, CLINTConsts.size-1)
}
case object CLINTKey extends Field[Option[CLINTParams]](None)
case class CLINTAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object CLINTAttachKey extends Field(CLINTAttachParams())
class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
import CLINTConsts._
// clint0 => at most 4095 devices
val device = new SimpleDevice("clint", Seq("riscv,clint0")) {
override val alwaysExtended = true
}
val node: TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes)
val intnode : IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
require (intnode.edges.in.size == 0, "CLINT only produces interrupts; it does not accept them")
val io = IO(new Bundle {
val rtcTick = Input(Bool())
})
val time = RegInit(0.U(timeWidth.W))
when (io.rtcTick) { time := time + 1.U }
val nTiles = intnode.out.size
val timecmp = Seq.fill(nTiles) { Reg(UInt(timeWidth.W)) }
val ipi = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
val (intnode_out, _) = intnode.out.unzip
intnode_out.zipWithIndex.foreach { case (int, i) =>
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}
/* 0000 msip hart 0
* 0004 msip hart 1
* 4000 mtimecmp hart 0 lo
* 4004 mtimecmp hart 0 hi
* 4008 mtimecmp hart 1 lo
* 400c mtimecmp hart 1 hi
* bff8 mtime lo
* bffc mtime hi
*/
node.regmap(
0 -> RegFieldGroup ("msip", Some("MSIP Bits"), ipi.zipWithIndex.flatMap{ case (r, i) =>
RegField(1, r, RegFieldDesc(s"msip_$i", s"MSIP bit for Hart $i", reset=Some(0))) :: RegField(ipiWidth - 1) :: Nil }),
timecmpOffset(0) -> timecmp.zipWithIndex.flatMap{ case (t, i) => RegFieldGroup(s"mtimecmp_$i", Some(s"MTIMECMP for hart $i"),
RegField.bytes(t, Some(RegFieldDesc(s"mtimecmp_$i", "", reset=None))))},
timeOffset -> RegFieldGroup("mtime", Some("Timer Register"),
RegField.bytes(time, Some(RegFieldDesc("mtime", "", reset=Some(0), volatile=true))))
)
}
}
/** Trait that will connect a CLINT to a subsystem */
trait CanHavePeripheryCLINT { this: BaseSubsystem =>
val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
val clintDomainWrapper = tlbus.generateSynchronousDomain("CLINT").suggestName("clint_domain")
val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus, Some("CLINT")) := _ } }
val clintTick = clintDomainWrapper { InModuleBody {
val tick = IO(Input(Bool()))
clint.module.io.rtcTick := tick
tick
}}
(clint, clintDomainWrapper, clintTick)
}.unzip3
}
| module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9]
output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_int_in_clock_xing_out_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25]
input tick, // @[CLINT.scala:115:20]
output clock, // @[ClockDomain.scala:21:19]
output reset // @[ClockDomain.scala:22:19]
);
wire _clint_auto_int_out_0; // @[CLINT.scala:112:48]
wire _clint_auto_int_out_1; // @[CLINT.scala:112:48]
wire auto_clint_in_a_valid_0 = auto_clint_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_a_bits_opcode_0 = auto_clint_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_a_bits_param_0 = auto_clint_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_a_bits_size_0 = auto_clint_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_clint_in_a_bits_source_0 = auto_clint_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_clint_in_a_bits_address_0 = auto_clint_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_clint_in_a_bits_mask_0 = auto_clint_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_clint_in_a_bits_data_0 = auto_clint_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_clint_in_a_bits_corrupt_0 = auto_clint_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_ready_0 = auto_clint_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_out_sync_1_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1; // @[MixedNode.scala:551:17]
assign auto_int_in_clock_xing_out_sync_1_0 = intInClockXingOut_sync_1; // @[ClockDomain.scala:14:9]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
CLINT clint ( // @[CLINT.scala:112:48]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_int_out_0 (_clint_auto_int_out_0),
.auto_int_out_1 (_clint_auto_int_out_1),
.auto_in_a_ready (auto_clint_in_a_ready_0),
.auto_in_a_valid (auto_clint_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (auto_clint_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (auto_clint_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (auto_clint_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (auto_clint_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (auto_clint_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (auto_clint_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (auto_clint_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (auto_clint_in_d_valid_0),
.auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode_0),
.auto_in_d_bits_size (auto_clint_in_d_bits_size_0),
.auto_in_d_bits_source (auto_clint_in_d_bits_source_0),
.auto_in_d_bits_data (auto_clint_in_d_bits_data_0),
.io_rtcTick (tick)
); // @[CLINT.scala:112:48]
IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (_clint_auto_int_out_0), // @[CLINT.scala:112:48]
.auto_in_1 (_clint_auto_int_out_1), // @[CLINT.scala:112:48]
.auto_out_sync_0 (intInClockXingIn_sync_0),
.auto_out_sync_1 (intInClockXingIn_sync_1)
); // @[Crossing.scala:29:31]
assign auto_clint_in_a_ready = auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_valid = auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_opcode = auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_size = auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_source = auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_clint_in_d_bits_data = auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_0 = auto_int_in_clock_xing_out_sync_0_0; // @[ClockDomain.scala:14:9]
assign auto_int_in_clock_xing_out_sync_1 = auto_int_in_clock_xing_out_sync_1_0; // @[ClockDomain.scala:14:9]
assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9]
assign reset = clockNodeIn_reset; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_1( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_set = 128'h0; // @[Monitor.scala:738:34]
wire [127:0] c_set_wo_ready = 128'h0; // @[Monitor.scala:739:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [1023:0] c_sizes_set = 1024'h0; // @[Monitor.scala:741:34]
wire [511:0] c_opcodes_set = 512'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [5:0] uncommonBits = _uncommonBits_T[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_1 = _uncommonBits_T_1[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_2 = _uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_3 = _uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_6 = _uncommonBits_T_6[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_7 = _uncommonBits_T_7[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_8 = _uncommonBits_T_8[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_9 = _uncommonBits_T_9[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_12 = _uncommonBits_T_12[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_13 = _uncommonBits_T_13[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_14 = _uncommonBits_T_14[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_15 = _uncommonBits_T_15[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[6]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [127:0] inflight; // @[Monitor.scala:614:27]
reg [511:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1023:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [127:0] a_set; // @[Monitor.scala:626:34]
wire [127:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [511:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1023:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [511:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [511:0] _a_opcode_lookup_T_6 = {508'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [511:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1023:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1023:0] _a_size_lookup_T_6 = {1016'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1023:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1023:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = {121'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_4 = 128'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1263 ? _a_set_T : 128'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[511:0] : 512'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[1023:0] : 1024'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [127:0] d_clr; // @[Monitor.scala:664:34]
wire [127:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [511:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1023:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_6 = {121'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_7 = 128'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 128'h0; // @[OneHot.scala:58:35]
wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1278 ? _d_clr_T : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[511:0] : 512'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[1023:0] : 1024'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [127:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [127:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [127:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [511:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [511:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [511:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1023:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1023:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1023:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [127:0] inflight_1; // @[Monitor.scala:726:35]
wire [127:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [511:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [511:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1023:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1023:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [511:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [511:0] _c_opcode_lookup_T_6 = {508'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [511:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[511:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1023:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1023:0] _c_size_lookup_T_6 = {1016'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1023:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1023:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [127:0] d_clr_1; // @[Monitor.scala:774:34]
wire [127:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [511:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1023:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 128'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[511:0] : 512'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[1023:0] : 1024'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [127:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [127:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [511:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [511:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1023:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1023:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v3.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v3.common._
import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))
val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f3_resp(w).valid := RegNext(s2_req_rhits(w))
io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))
io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
table.write(
Mux(doing_reset, reset_idx , update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools
)
val update_hi_wdata = Wire(Vec(bankWidth, Bool()))
hi_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),
Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val update_lo_wdata = Wire(Vec(bankWidth, Bool()))
lo_us.write(
Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),
Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),
Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools
)
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
update_hi_wdata(w) := io.update_u(w)(1)
update_lo_wdata(w) := io.update_u(w)(0)
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(io.f0_pc)
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f3_resps = VecInit(tables.map(_.io.f3_resp))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var altpred = io.resp_in(0).f3(w).taken
val final_altpred = WireInit(io.resp_in(0).f3(w).taken)
var provided = false.B
var provider = 0.U
io.resp.f3(w).taken := io.resp_in(0).f3(w).taken
for (i <- 0 until tageNTables) {
val hit = f3_resps(i)(w).valid
val ctr = f3_resps(i)(w).bits.ctr
when (hit) {
io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))
final_altpred := altpred
}
provided = provided || hit
provider = Mux(hit, i.U, provider)
altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)
}
f3_meta.provider(w).valid := provided
f3_meta.provider(w).bits := provider
f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u
f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module table_8( // @[tage.scala:91:27]
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [47:0] R0_data,
input [7:0] W0_addr,
input W0_clk,
input [47:0] W0_data,
input [3:0] W0_mask
);
table_0_ext table_0_ext ( // @[tage.scala:91:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (1'h1), // @[tage.scala:91:27]
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:91:27]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_50( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_91( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_102 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
| module BranchKillableQueue_8( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [7:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [63:0] io_enq_bits_data, // @[util.scala:453:14]
input io_enq_bits_is_hella, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [7:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [63:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_is_hella, // @[util.scala:453:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_br, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14]
input io_brupdate_b2_uop_taken, // @[util.scala:453:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14]
input io_brupdate_b2_uop_exception, // @[util.scala:453:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14]
input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14]
input io_brupdate_b2_valid, // @[util.scala:453:14]
input io_brupdate_b2_mispredict, // @[util.scala:453:14]
input io_brupdate_b2_taken, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14]
input io_flush // @[util.scala:453:14]
);
wire [64:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [7:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7]
wire io_flush_0 = io_flush; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire _io_deq_valid_T_8; // @[util.scala:509:108]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [39:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [7:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [2:0] out_uop_br_tag; // @[util.scala:506:17]
wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [4:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [2:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [2:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [5:0] out_uop_pdst; // @[util.scala:506:17]
wire [5:0] out_uop_prs1; // @[util.scala:506:17]
wire [5:0] out_uop_prs2; // @[util.scala:506:17]
wire [5:0] out_uop_prs3; // @[util.scala:506:17]
wire [3:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [5:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [63:0] out_data; // @[util.scala:506:17]
wire out_is_hella; // @[util.scala:506:17]
wire _io_empty_T_1; // @[util.scala:473:25]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [7:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_is_hella_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty; // @[util.scala:448:7]
wire [1:0] io_count; // @[util.scala:448:7]
assign out_data = _ram_ext_R0_data[63:0]; // @[util.scala:464:20, :506:17]
assign out_is_hella = _ram_ext_R0_data[64]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
reg valids_1; // @[util.scala:465:24]
reg valids_2; // @[util.scala:465:24]
reg valids_3; // @[util.scala:465:24]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [7:0] uops_0_br_mask; // @[util.scala:466:20]
reg [2:0] uops_0_br_tag; // @[util.scala:466:20]
reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [4:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [2:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [2:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [5:0] uops_0_pdst; // @[util.scala:466:20]
reg [5:0] uops_0_prs1; // @[util.scala:466:20]
reg [5:0] uops_0_prs2; // @[util.scala:466:20]
reg [5:0] uops_0_prs3; // @[util.scala:466:20]
reg [3:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [5:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [7:0] uops_1_br_mask; // @[util.scala:466:20]
reg [2:0] uops_1_br_tag; // @[util.scala:466:20]
reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [4:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [2:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [2:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [5:0] uops_1_pdst; // @[util.scala:466:20]
reg [5:0] uops_1_prs1; // @[util.scala:466:20]
reg [5:0] uops_1_prs2; // @[util.scala:466:20]
reg [5:0] uops_1_prs3; // @[util.scala:466:20]
reg [3:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [5:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [7:0] uops_2_br_mask; // @[util.scala:466:20]
reg [2:0] uops_2_br_tag; // @[util.scala:466:20]
reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [4:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [2:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [2:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [5:0] uops_2_pdst; // @[util.scala:466:20]
reg [5:0] uops_2_prs1; // @[util.scala:466:20]
reg [5:0] uops_2_prs2; // @[util.scala:466:20]
reg [5:0] uops_2_prs3; // @[util.scala:466:20]
reg [3:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [5:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_3_uopc; // @[util.scala:466:20]
reg [31:0] uops_3_inst; // @[util.scala:466:20]
reg [31:0] uops_3_debug_inst; // @[util.scala:466:20]
reg uops_3_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_3_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_3_iq_type; // @[util.scala:466:20]
reg [9:0] uops_3_fu_code; // @[util.scala:466:20]
reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_3_ctrl_is_load; // @[util.scala:466:20]
reg uops_3_ctrl_is_sta; // @[util.scala:466:20]
reg uops_3_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_3_iw_state; // @[util.scala:466:20]
reg uops_3_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_3_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_3_is_br; // @[util.scala:466:20]
reg uops_3_is_jalr; // @[util.scala:466:20]
reg uops_3_is_jal; // @[util.scala:466:20]
reg uops_3_is_sfb; // @[util.scala:466:20]
reg [7:0] uops_3_br_mask; // @[util.scala:466:20]
reg [2:0] uops_3_br_tag; // @[util.scala:466:20]
reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20]
reg uops_3_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_3_pc_lob; // @[util.scala:466:20]
reg uops_3_taken; // @[util.scala:466:20]
reg [19:0] uops_3_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_3_csr_addr; // @[util.scala:466:20]
reg [4:0] uops_3_rob_idx; // @[util.scala:466:20]
reg [2:0] uops_3_ldq_idx; // @[util.scala:466:20]
reg [2:0] uops_3_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20]
reg [5:0] uops_3_pdst; // @[util.scala:466:20]
reg [5:0] uops_3_prs1; // @[util.scala:466:20]
reg [5:0] uops_3_prs2; // @[util.scala:466:20]
reg [5:0] uops_3_prs3; // @[util.scala:466:20]
reg [3:0] uops_3_ppred; // @[util.scala:466:20]
reg uops_3_prs1_busy; // @[util.scala:466:20]
reg uops_3_prs2_busy; // @[util.scala:466:20]
reg uops_3_prs3_busy; // @[util.scala:466:20]
reg uops_3_ppred_busy; // @[util.scala:466:20]
reg [5:0] uops_3_stale_pdst; // @[util.scala:466:20]
reg uops_3_exception; // @[util.scala:466:20]
reg [63:0] uops_3_exc_cause; // @[util.scala:466:20]
reg uops_3_bypassable; // @[util.scala:466:20]
reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_3_mem_size; // @[util.scala:466:20]
reg uops_3_mem_signed; // @[util.scala:466:20]
reg uops_3_is_fence; // @[util.scala:466:20]
reg uops_3_is_fencei; // @[util.scala:466:20]
reg uops_3_is_amo; // @[util.scala:466:20]
reg uops_3_uses_ldq; // @[util.scala:466:20]
reg uops_3_uses_stq; // @[util.scala:466:20]
reg uops_3_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_3_is_unique; // @[util.scala:466:20]
reg uops_3_flush_on_commit; // @[util.scala:466:20]
reg uops_3_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_3_ldst; // @[util.scala:466:20]
reg [5:0] uops_3_lrs1; // @[util.scala:466:20]
reg [5:0] uops_3_lrs2; // @[util.scala:466:20]
reg [5:0] uops_3_lrs3; // @[util.scala:466:20]
reg uops_3_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20]
reg uops_3_frs3_en; // @[util.scala:466:20]
reg uops_3_fp_val; // @[util.scala:466:20]
reg uops_3_fp_single; // @[util.scala:466:20]
reg uops_3_xcpt_pf_if; // @[util.scala:466:20]
reg uops_3_xcpt_ae_if; // @[util.scala:466:20]
reg uops_3_xcpt_ma_if; // @[util.scala:466:20]
reg uops_3_bp_debug_if; // @[util.scala:466:20]
reg uops_3_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20]
reg [1:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [1:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire full; // @[util.scala:474:24]
assign full = _GEN; // @[util.scala:474:24]
wire _io_count_T; // @[util.scala:526:32]
assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_0 = {{valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}]
wire [7:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}]
wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32]
wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}]
wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}]
wire [7:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [7:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [7:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}]
wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32]
wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}]
wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}]
wire [7:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [7:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [7:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}]
wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32]
wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}]
wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}]
wire [7:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [7:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [7:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}]
wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32]
wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}]
wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}]
wire [7:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [7:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [7:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [2:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T = _GEN_2 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_1 = _value_T[1:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [2:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T_2 = _GEN_3 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_3 = _value_T_2[1:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17]
wire [7:0] out_uop_br_mask; // @[util.scala:506:17]
wire [3:0][6:0] _GEN_4 = {{uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][31:0] _GEN_5 = {{uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][31:0] _GEN_6 = {{uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_7 = {{uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][39:0] _GEN_8 = {{uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_9 = {{uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][9:0] _GEN_10 = {{uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_11 = {{uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_12 = {{uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_13 = {{uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_14 = {{uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_15 = {{uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_16 = {{uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_17 = {{uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_18 = {{uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_19 = {{uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_20 = {{uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_21 = {{uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_22 = {{uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_23 = {{uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_24 = {{uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_25 = {{uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_26 = {{uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_27 = {{uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][7:0] _GEN_28 = {{uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_29 = {{uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_30 = {{uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_31 = {{uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_32 = {{uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_33 = {{uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][19:0] _GEN_34 = {{uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][11:0] _GEN_35 = {{uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_36 = {{uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_37 = {{uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_38 = {{uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_39 = {{uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_40 = {{uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_41 = {{uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_42 = {{uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_43 = {{uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_44 = {{uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_45 = {{uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_46 = {{uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_47 = {{uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_48 = {{uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_49 = {{uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_50 = {{uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][63:0] _GEN_51 = {{uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_52 = {{uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_53 = {{uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_54 = {{uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_55 = {{uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_56 = {{uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_57 = {{uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_58 = {{uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_59 = {{uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_60 = {{uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_61 = {{uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_62 = {{uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_63 = {{uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_64 = {{uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_65 = {{uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_66 = {{uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_67 = {{uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_68 = {{uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_69 = {{uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_70 = {{uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_71 = {{uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_72 = {{uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_73 = {{uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_74 = {{uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_75 = {{uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_76 = {{uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_77 = {{uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_78 = {{uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_79 = {{uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_80 = {{uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_81 = {{uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_82 = {{uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}]
wire [7:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17]
wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}]
wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}]
wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122]
wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}]
assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}]
assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108]
wire [7:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17]
assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7]
wire [2:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [1:0] ptr_diff = _ptr_diff_T[1:0]; // @[util.scala:524:40]
wire [2:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}]
assign io_count = _io_count_T_1[1:0]; // @[util.scala:448:7, :526:{14,20}]
wire _GEN_83 = enq_ptr_value == 2'h0; // @[Counter.scala:61:40]
wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_85 = enq_ptr_value == 2'h1; // @[Counter.scala:61:40]
wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_87 = enq_ptr_value == 2'h2; // @[Counter.scala:61:40]
wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_89 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
valids_3 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 2'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_89 | _valids_3_T_6); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_89) begin // @[util.scala:481:16, :487:17, :489:33]
uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_3) // @[util.scala:465:24]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_4x65 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({io_enq_bits_is_hella_0, io_enq_bits_data_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d64s4k3z4c_2( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Decoupled.scala:362:21]
wire [7:0] auto_out_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [7:0] nodeOut_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_source = 4'h0; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_source = 4'h0; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_42 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s4k3z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s4k3z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s4k3z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s4k3z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s4k3z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Frontend.scala:
package saturn.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
import saturn.common._
import saturn.backend.{VectorBackend}
import saturn.mem.{ScalarMemOrderCheckIO, TLSplitInterface}
import saturn.frontend.{EarlyTrapCheck, IterativeTrapCheck}
class SaturnRocketFrontend(edge: TLEdge)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val core = new VectorCoreIO
val tlb = Flipped(new DCacheTLBPort)
val issue = Decoupled(new VectorIssueInst)
val index_access = Flipped(new VectorIndexAccessIO)
val mask_access = Flipped(new VectorMaskAccessIO)
val scalar_check = Flipped(new ScalarMemOrderCheckIO)
})
val ptc = Module(new EarlyTrapCheck(edge, None))
val itc = Module(new IterativeTrapCheck)
ptc.io.sg_base := DontCare
ptc.io.s0.in.valid := io.core.ex.valid && !itc.io.busy
ptc.io.s0.in.bits.inst := io.core.ex.inst
ptc.io.s0.in.bits.pc := io.core.ex.pc
ptc.io.s0.in.bits.status := io.core.status
ptc.io.s0.in.bits.vconfig := io.core.ex.vconfig
ptc.io.s0.in.bits.vstart := io.core.ex.vstart
ptc.io.s0.in.bits.rs1 := io.core.ex.rs1
ptc.io.s0.in.bits.rs2 := io.core.ex.rs2
ptc.io.s0.in.bits.phys := false.B
io.core.ex.ready := !itc.io.busy
ptc.io.s1.rs1.valid := ptc.io.s1.inst.isOpf && !ptc.io.s1.inst.vmu
ptc.io.s1.rs1.bits := io.core.mem.frs1
ptc.io.s1.kill := io.core.killm
io.core.mem.block_all := itc.io.busy || ptc.io.s2.internal_replay.valid
io.core.mem.block_mem := (ptc.io.s2.inst.valid && ptc.io.s2.inst.bits.vmu) || io.scalar_check.conflict
io.tlb.req.valid := Mux(itc.io.busy, itc.io.s0_tlb_req.valid, ptc.io.s0.tlb_req.valid)
io.tlb.req.bits := Mux(itc.io.busy, itc.io.s0_tlb_req.bits , ptc.io.s0.tlb_req.bits)
ptc.io.s1.tlb_resp := io.tlb.s1_resp
when (RegEnable(itc.io.busy || !io.tlb.req.ready, ptc.io.s0.tlb_req.valid)) { ptc.io.s1.tlb_resp.miss := true.B }
itc.io.tlb_resp := io.tlb.s1_resp
when (RegEnable(!io.tlb.req.ready, itc.io.s0_tlb_req.valid)) { itc.io.tlb_resp.miss := true.B }
io.tlb.s2_kill := false.B
ptc.io.s2.scalar_store_pending := io.core.wb.store_pending
io.core.wb.replay := ptc.io.s2.replay
io.core.wb.xcpt := Mux(itc.io.busy, itc.io.xcpt.valid , ptc.io.s2.xcpt.valid)
io.core.wb.cause := Mux(itc.io.busy, itc.io.xcpt.bits.cause, ptc.io.s2.xcpt.bits.cause)
io.core.wb.pc := Mux(itc.io.busy, itc.io.pc , ptc.io.s2.pc)
io.core.wb.retire := Mux(itc.io.busy, itc.io.retire , ptc.io.s2.retire)
io.core.wb.inst := Mux(itc.io.busy, itc.io.inst.bits , ptc.io.s2.inst.bits.bits)
io.core.wb.tval := Mux(itc.io.busy, itc.io.xcpt.bits.tval , ptc.io.s2.xcpt.bits.tval)
io.core.wb.rob_should_wb := Mux(itc.io.busy, itc.io.inst.writes_xrf, ptc.io.s2.inst.bits.writes_xrf)
io.core.wb.rob_should_wb_fp := Mux(itc.io.busy, itc.io.inst.writes_frf, ptc.io.s2.inst.bits.writes_frf)
io.core.set_vstart := Mux(itc.io.busy, itc.io.vstart , ptc.io.s2.vstart)
io.core.set_vconfig := itc.io.vconfig
ptc.io.s2.vxrm := io.core.wb.vxrm
ptc.io.s2.frm := io.core.wb.frm
itc.io.in := ptc.io.s2.internal_replay
io.issue.valid := Mux(itc.io.busy, itc.io.issue.valid, ptc.io.s2.issue.valid)
io.issue.bits := Mux(itc.io.busy, itc.io.issue.bits , ptc.io.s2.issue.bits)
itc.io.issue.ready := io.issue.ready
ptc.io.s2.issue.ready := !itc.io.busy && io.issue.ready
io.core.trap_check_busy := ptc.io.busy || itc.io.busy
itc.io.status := io.core.status
itc.io.index_access <> io.index_access
itc.io.mask_access <> io.mask_access
io.scalar_check.addr := io.tlb.s1_resp.paddr
io.scalar_check.size := io.tlb.s1_resp.size
io.scalar_check.store := isWrite(io.tlb.s1_resp.cmd)
io.core.backend_busy := false.B // set externally
io.core.set_vxsat := false.B // set externally
io.core.set_fflags := DontCare // set externally
io.core.resp := DontCare
}
| module SaturnRocketFrontend( // @[Frontend.scala:17:7]
input clock, // @[Frontend.scala:17:7]
input reset, // @[Frontend.scala:17:7]
input [1:0] io_core_status_prv, // @[Frontend.scala:18:14]
input io_core_ex_valid, // @[Frontend.scala:18:14]
output io_core_ex_ready, // @[Frontend.scala:18:14]
input [31:0] io_core_ex_inst, // @[Frontend.scala:18:14]
input [39:0] io_core_ex_pc, // @[Frontend.scala:18:14]
input [7:0] io_core_ex_vconfig_vl, // @[Frontend.scala:18:14]
input io_core_ex_vconfig_vtype_vill, // @[Frontend.scala:18:14]
input [54:0] io_core_ex_vconfig_vtype_reserved, // @[Frontend.scala:18:14]
input io_core_ex_vconfig_vtype_vma, // @[Frontend.scala:18:14]
input io_core_ex_vconfig_vtype_vta, // @[Frontend.scala:18:14]
input [2:0] io_core_ex_vconfig_vtype_vsew, // @[Frontend.scala:18:14]
input io_core_ex_vconfig_vtype_vlmul_sign, // @[Frontend.scala:18:14]
input [1:0] io_core_ex_vconfig_vtype_vlmul_mag, // @[Frontend.scala:18:14]
input [6:0] io_core_ex_vstart, // @[Frontend.scala:18:14]
input [63:0] io_core_ex_rs1, // @[Frontend.scala:18:14]
input [63:0] io_core_ex_rs2, // @[Frontend.scala:18:14]
input io_core_killm, // @[Frontend.scala:18:14]
input [63:0] io_core_mem_frs1, // @[Frontend.scala:18:14]
output io_core_mem_block_mem, // @[Frontend.scala:18:14]
output io_core_mem_block_all, // @[Frontend.scala:18:14]
input io_core_wb_store_pending, // @[Frontend.scala:18:14]
output io_core_wb_replay, // @[Frontend.scala:18:14]
output io_core_wb_retire, // @[Frontend.scala:18:14]
output [31:0] io_core_wb_inst, // @[Frontend.scala:18:14]
output io_core_wb_rob_should_wb, // @[Frontend.scala:18:14]
output io_core_wb_rob_should_wb_fp, // @[Frontend.scala:18:14]
output [39:0] io_core_wb_pc, // @[Frontend.scala:18:14]
output io_core_wb_xcpt, // @[Frontend.scala:18:14]
output [4:0] io_core_wb_cause, // @[Frontend.scala:18:14]
output [39:0] io_core_wb_tval, // @[Frontend.scala:18:14]
input [1:0] io_core_wb_vxrm, // @[Frontend.scala:18:14]
input [2:0] io_core_wb_frm, // @[Frontend.scala:18:14]
output io_core_set_vstart_valid, // @[Frontend.scala:18:14]
output [6:0] io_core_set_vstart_bits, // @[Frontend.scala:18:14]
output io_core_set_vconfig_valid, // @[Frontend.scala:18:14]
output [7:0] io_core_set_vconfig_bits_vl, // @[Frontend.scala:18:14]
output io_core_set_vconfig_bits_vtype_vill, // @[Frontend.scala:18:14]
output [54:0] io_core_set_vconfig_bits_vtype_reserved, // @[Frontend.scala:18:14]
output io_core_set_vconfig_bits_vtype_vma, // @[Frontend.scala:18:14]
output io_core_set_vconfig_bits_vtype_vta, // @[Frontend.scala:18:14]
output [2:0] io_core_set_vconfig_bits_vtype_vsew, // @[Frontend.scala:18:14]
output io_core_set_vconfig_bits_vtype_vlmul_sign, // @[Frontend.scala:18:14]
output [1:0] io_core_set_vconfig_bits_vtype_vlmul_mag, // @[Frontend.scala:18:14]
output io_core_trap_check_busy, // @[Frontend.scala:18:14]
output io_tlb_req_valid, // @[Frontend.scala:18:14]
output [39:0] io_tlb_req_bits_vaddr, // @[Frontend.scala:18:14]
output [1:0] io_tlb_req_bits_size, // @[Frontend.scala:18:14]
output [4:0] io_tlb_req_bits_cmd, // @[Frontend.scala:18:14]
output [1:0] io_tlb_req_bits_prv, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_miss, // @[Frontend.scala:18:14]
input [31:0] io_tlb_s1_resp_paddr, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_pf_ld, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_pf_st, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_ae_ld, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_ae_st, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_ma_ld, // @[Frontend.scala:18:14]
input io_tlb_s1_resp_ma_st, // @[Frontend.scala:18:14]
input [4:0] io_tlb_s1_resp_cmd, // @[Frontend.scala:18:14]
input io_issue_ready, // @[Frontend.scala:18:14]
output io_issue_valid, // @[Frontend.scala:18:14]
output [31:0] io_issue_bits_bits, // @[Frontend.scala:18:14]
output [7:0] io_issue_bits_vconfig_vl, // @[Frontend.scala:18:14]
output [2:0] io_issue_bits_vconfig_vtype_vsew, // @[Frontend.scala:18:14]
output io_issue_bits_vconfig_vtype_vlmul_sign, // @[Frontend.scala:18:14]
output [1:0] io_issue_bits_vconfig_vtype_vlmul_mag, // @[Frontend.scala:18:14]
output [6:0] io_issue_bits_vstart, // @[Frontend.scala:18:14]
output [2:0] io_issue_bits_segstart, // @[Frontend.scala:18:14]
output [2:0] io_issue_bits_segend, // @[Frontend.scala:18:14]
output [63:0] io_issue_bits_rs1_data, // @[Frontend.scala:18:14]
output [63:0] io_issue_bits_rs2_data, // @[Frontend.scala:18:14]
output [19:0] io_issue_bits_page, // @[Frontend.scala:18:14]
output [2:0] io_issue_bits_rm, // @[Frontend.scala:18:14]
output [1:0] io_issue_bits_emul, // @[Frontend.scala:18:14]
output [1:0] io_issue_bits_mop, // @[Frontend.scala:18:14]
input io_index_access_ready, // @[Frontend.scala:18:14]
output io_index_access_valid, // @[Frontend.scala:18:14]
output [4:0] io_index_access_vrs, // @[Frontend.scala:18:14]
output [7:0] io_index_access_eidx, // @[Frontend.scala:18:14]
output [1:0] io_index_access_eew, // @[Frontend.scala:18:14]
input [63:0] io_index_access_idx, // @[Frontend.scala:18:14]
input io_mask_access_ready, // @[Frontend.scala:18:14]
output io_mask_access_valid, // @[Frontend.scala:18:14]
output [7:0] io_mask_access_eidx, // @[Frontend.scala:18:14]
input io_mask_access_mask, // @[Frontend.scala:18:14]
output [39:0] io_scalar_check_addr, // @[Frontend.scala:18:14]
output io_scalar_check_store, // @[Frontend.scala:18:14]
input io_scalar_check_conflict // @[Frontend.scala:18:14]
);
wire _itc_io_busy; // @[Frontend.scala:31:19]
wire _itc_io_s0_tlb_req_valid; // @[Frontend.scala:31:19]
wire [39:0] _itc_io_s0_tlb_req_bits_vaddr; // @[Frontend.scala:31:19]
wire [1:0] _itc_io_s0_tlb_req_bits_size; // @[Frontend.scala:31:19]
wire [4:0] _itc_io_s0_tlb_req_bits_cmd; // @[Frontend.scala:31:19]
wire [1:0] _itc_io_s0_tlb_req_bits_prv; // @[Frontend.scala:31:19]
wire _itc_io_retire; // @[Frontend.scala:31:19]
wire [39:0] _itc_io_pc; // @[Frontend.scala:31:19]
wire _itc_io_vstart_valid; // @[Frontend.scala:31:19]
wire [6:0] _itc_io_vstart_bits; // @[Frontend.scala:31:19]
wire _itc_io_xcpt_valid; // @[Frontend.scala:31:19]
wire [63:0] _itc_io_xcpt_bits_cause; // @[Frontend.scala:31:19]
wire [39:0] _itc_io_xcpt_bits_tval; // @[Frontend.scala:31:19]
wire [31:0] _itc_io_inst_bits; // @[Frontend.scala:31:19]
wire _itc_io_issue_valid; // @[Frontend.scala:31:19]
wire [31:0] _itc_io_issue_bits_bits; // @[Frontend.scala:31:19]
wire [7:0] _itc_io_issue_bits_vconfig_vl; // @[Frontend.scala:31:19]
wire [2:0] _itc_io_issue_bits_vconfig_vtype_vsew; // @[Frontend.scala:31:19]
wire _itc_io_issue_bits_vconfig_vtype_vlmul_sign; // @[Frontend.scala:31:19]
wire [1:0] _itc_io_issue_bits_vconfig_vtype_vlmul_mag; // @[Frontend.scala:31:19]
wire [6:0] _itc_io_issue_bits_vstart; // @[Frontend.scala:31:19]
wire [2:0] _itc_io_issue_bits_segstart; // @[Frontend.scala:31:19]
wire [2:0] _itc_io_issue_bits_segend; // @[Frontend.scala:31:19]
wire [63:0] _itc_io_issue_bits_rs1_data; // @[Frontend.scala:31:19]
wire [63:0] _itc_io_issue_bits_rs2_data; // @[Frontend.scala:31:19]
wire [19:0] _itc_io_issue_bits_page; // @[Frontend.scala:31:19]
wire [2:0] _itc_io_issue_bits_rm; // @[Frontend.scala:31:19]
wire [1:0] _itc_io_issue_bits_emul; // @[Frontend.scala:31:19]
wire [1:0] _itc_io_issue_bits_mop; // @[Frontend.scala:31:19]
wire _ptc_io_busy; // @[Frontend.scala:30:19]
wire _ptc_io_s0_tlb_req_valid; // @[Frontend.scala:30:19]
wire [39:0] _ptc_io_s0_tlb_req_bits_vaddr; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s0_tlb_req_bits_size; // @[Frontend.scala:30:19]
wire [4:0] _ptc_io_s0_tlb_req_bits_cmd; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s0_tlb_req_bits_prv; // @[Frontend.scala:30:19]
wire [31:0] _ptc_io_s1_inst_bits; // @[Frontend.scala:30:19]
wire _ptc_io_s2_inst_valid; // @[Frontend.scala:30:19]
wire [31:0] _ptc_io_s2_inst_bits_bits; // @[Frontend.scala:30:19]
wire _ptc_io_s2_vstart_valid; // @[Frontend.scala:30:19]
wire [6:0] _ptc_io_s2_vstart_bits; // @[Frontend.scala:30:19]
wire _ptc_io_s2_retire; // @[Frontend.scala:30:19]
wire _ptc_io_s2_xcpt_valid; // @[Frontend.scala:30:19]
wire [63:0] _ptc_io_s2_xcpt_bits_cause; // @[Frontend.scala:30:19]
wire [39:0] _ptc_io_s2_xcpt_bits_tval; // @[Frontend.scala:30:19]
wire [39:0] _ptc_io_s2_pc; // @[Frontend.scala:30:19]
wire _ptc_io_s2_internal_replay_valid; // @[Frontend.scala:30:19]
wire [39:0] _ptc_io_s2_internal_replay_bits_pc; // @[Frontend.scala:30:19]
wire [31:0] _ptc_io_s2_internal_replay_bits_bits; // @[Frontend.scala:30:19]
wire [7:0] _ptc_io_s2_internal_replay_bits_vconfig_vl; // @[Frontend.scala:30:19]
wire _ptc_io_s2_internal_replay_bits_vconfig_vtype_vill; // @[Frontend.scala:30:19]
wire [54:0] _ptc_io_s2_internal_replay_bits_vconfig_vtype_reserved; // @[Frontend.scala:30:19]
wire _ptc_io_s2_internal_replay_bits_vconfig_vtype_vma; // @[Frontend.scala:30:19]
wire _ptc_io_s2_internal_replay_bits_vconfig_vtype_vta; // @[Frontend.scala:30:19]
wire [2:0] _ptc_io_s2_internal_replay_bits_vconfig_vtype_vsew; // @[Frontend.scala:30:19]
wire _ptc_io_s2_internal_replay_bits_vconfig_vtype_vlmul_sign; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_internal_replay_bits_vconfig_vtype_vlmul_mag; // @[Frontend.scala:30:19]
wire [6:0] _ptc_io_s2_internal_replay_bits_vstart; // @[Frontend.scala:30:19]
wire [63:0] _ptc_io_s2_internal_replay_bits_rs1_data; // @[Frontend.scala:30:19]
wire [63:0] _ptc_io_s2_internal_replay_bits_rs2_data; // @[Frontend.scala:30:19]
wire [2:0] _ptc_io_s2_internal_replay_bits_rm; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_internal_replay_bits_emul; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_internal_replay_bits_mop; // @[Frontend.scala:30:19]
wire _ptc_io_s2_issue_valid; // @[Frontend.scala:30:19]
wire [31:0] _ptc_io_s2_issue_bits_bits; // @[Frontend.scala:30:19]
wire [7:0] _ptc_io_s2_issue_bits_vconfig_vl; // @[Frontend.scala:30:19]
wire [2:0] _ptc_io_s2_issue_bits_vconfig_vtype_vsew; // @[Frontend.scala:30:19]
wire _ptc_io_s2_issue_bits_vconfig_vtype_vlmul_sign; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_issue_bits_vconfig_vtype_vlmul_mag; // @[Frontend.scala:30:19]
wire [6:0] _ptc_io_s2_issue_bits_vstart; // @[Frontend.scala:30:19]
wire [2:0] _ptc_io_s2_issue_bits_segend; // @[Frontend.scala:30:19]
wire [63:0] _ptc_io_s2_issue_bits_rs1_data; // @[Frontend.scala:30:19]
wire [63:0] _ptc_io_s2_issue_bits_rs2_data; // @[Frontend.scala:30:19]
wire [19:0] _ptc_io_s2_issue_bits_page; // @[Frontend.scala:30:19]
wire [2:0] _ptc_io_s2_issue_bits_rm; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_issue_bits_emul; // @[Frontend.scala:30:19]
wire [1:0] _ptc_io_s2_issue_bits_mop; // @[Frontend.scala:30:19]
reg r; // @[Frontend.scala:54:18]
wire [6:0] _io_core_wb_rob_should_wb_WIRE = {1'h0, _itc_io_inst_bits[31:26]}; // @[Frontend.scala:17:7, :31:19]
wire [6:0] _io_core_wb_rob_should_wb_WIRE_4 = {1'h0, _ptc_io_s2_inst_bits_bits[31:26]}; // @[Frontend.scala:17:7, :30:19]
always @(posedge clock) begin // @[Frontend.scala:17:7]
if (_ptc_io_s0_tlb_req_valid) // @[Frontend.scala:30:19]
r <= _itc_io_busy; // @[Frontend.scala:31:19, :54:18]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File decode.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket.Instructions32
import freechips.rocketchip.rocket.CustomInstructions._
import freechips.rocketchip.rocket.RVCExpander
import freechips.rocketchip.rocket.{CSR,Causes}
import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}
import FUConstants._
import boom.v3.common._
import boom.v3.util._
// scalastyle:off
/**
* Abstract trait giving defaults and other relevant values to different Decode constants/
*/
abstract trait DecodeConstants
extends freechips.rocketchip.rocket.constants.ScalarOpConstants
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val xpr64 = Y // TODO inform this from xLen
val DC2 = BitPat.dontCare(2) // Makes the listing below more readable
def decode_default: List[BitPat] =
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)
val table: Array[(BitPat, List[BitPat])]
}
// scalastyle:on
/**
* Decoded control signals
*/
class CtrlSigs extends Bundle
{
val legal = Bool()
val fp_val = Bool()
val fp_single = Bool()
val uopc = UInt(UOPC_SZ.W)
val iq_type = UInt(IQT_SZ.W)
val fu_code = UInt(FUC_SZ.W)
val dst_type = UInt(2.W)
val rs1_type = UInt(2.W)
val rs2_type = UInt(2.W)
val frs3_en = Bool()
val imm_sel = UInt(IS_X.getWidth.W)
val uses_ldq = Bool()
val uses_stq = Bool()
val is_amo = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)
val wakeup_delay = UInt(2.W)
val bypassable = Bool()
val is_br = Bool()
val is_sys_pc2epc = Bool()
val inst_unique = Bool()
val flush_on_commit = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val rocc = Bool()
def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)
val sigs =
Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,
rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,
is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,
is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)
sigs zip decoder map {case(s,d) => s := d}
rocc := false.B
this
}
}
// scalastyle:off
/**
* Decode constants for RV32
*/
object X32Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
Instructions32.SLLI ->
List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRLI ->
List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
Instructions32.SRAI ->
List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Decode constants for RV64
*/
object X64Decode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)
)
}
/**
* Overall Decode constants
*/
object XDecode extends DecodeConstants
{
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |
LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),
SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),
MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read
JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),
BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),
// I-type, the immediate12 holds the CSR register.
CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),
CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),
CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),
SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),
ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),
SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),
FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),
FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance
// currently serializes pipeline
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec? rs1 regtype | | | uses_stq | | |
// | | | micro-code | rs2 type| | | | is_amo | | |
// | | | | iq-type func unit | | | | | | | is_fence | | |
// | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// A-type | | | | | | | | | | | | | | | | | | | | | | | |
AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance
AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),
AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),
AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),
AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),
AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),
AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),
AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),
AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),
AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),
LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),
SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),
SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)
)
}
/**
* FP Decode constants
*/
object FDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),
FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops
FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),
FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to FP
FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// Int to FP
FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// FP to Int
FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
// "fp_single" is used for wb_data formatting (and debugging)
FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* FP Divide SquareRoot Constants
*/
object FDivSqrtDecode extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
// frs3_en wakeup_delay
// | imm sel | bypassable (aka, known/fixed latency)
// | | uses_ldq | | is_br
// is val inst? rs1 regtype | | | uses_stq | | |
// | is fp inst? | rs2 type| | | | is_amo | | |
// | | is dst single-prec? | | | | | | | is_fence | | |
// | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall
// | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
//scalastyle:on
/**
* RoCC initial decode
*/
object RoCCDecode extends DecodeConstants
{
// Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions
// frs3_en wakeup_delay
// is val inst? | imm sel | bypassable (aka, known/fixed latency)
// | is fp inst? | | uses_ldq | | is_br
// | | is single-prec rs1 regtype | | | uses_stq | | |
// | | | | rs2 type| | | | is_amo | | |
// | | | micro-code func unit | | | | | | | is_fence | | |
// | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?
// | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)
// | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit
// | | | | | | | | | | | | | | | | | | | | | | | csr cmd
// | | | | | | | | | | | | | | | | | | | | | | | |
val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |
CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),
CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)
)
}
/**
* IO bundle for the Decode unit
*/
class DecodeUnitIo(implicit p: Parameters) extends BoomBundle
{
val enq = new Bundle { val uop = Input(new MicroOp()) }
val deq = new Bundle { val uop = Output(new MicroOp()) }
// from CSRFile
val status = Input(new freechips.rocketchip.rocket.MStatus())
val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)
val interrupt = Input(Bool())
val interrupt_cause = Input(UInt(xLen.W))
}
/**
* Decode unit that takes in a single instruction and generates a MicroOp.
*/
class DecodeUnit(implicit p: Parameters) extends BoomModule
with freechips.rocketchip.rocket.constants.MemoryOpConstants
{
val io = IO(new DecodeUnitIo)
val uop = Wire(new MicroOp())
uop := io.enq.uop
var decode_table = XDecode.table
if (usingFPU) decode_table ++= FDecode.table
if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table
if (usingRoCC) decode_table ++= RoCCDecode.table
decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)
val inst = uop.inst
val cs = Wire(new CtrlSigs()).decode(inst, decode_table)
// Exception Handling
io.csr_decode.inst := inst
val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)
val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U
val system_insn = cs.csr_cmd === CSR.I
val sfence = cs.uopc === uopSFENCE
val cs_legal = cs.legal
// dontTouch(cs_legal)
val id_illegal_insn = !cs_legal ||
cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)
cs.rocc && io.csr_decode.rocc_illegal ||
cs.is_amo && !io.status.isa('a'-'a') ||
(cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||
csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||
((sfence || system_insn) && io.csr_decode.system_illegal)
// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_valid, xcpt_cause) = checkExceptions(List(
(io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB
(uop.bp_debug_if, (CSR.debugTriggerCause).U),
(uop.bp_xcpt_if, (Causes.breakpoint).U),
(uop.xcpt_pf_if, (Causes.fetch_page_fault).U),
(uop.xcpt_ae_if, (Causes.fetch_access).U),
(id_illegal_insn, (Causes.illegal_instruction).U)))
uop.exception := xcpt_valid
uop.exc_cause := xcpt_cause
//-------------------------------------------------------------
uop.uopc := cs.uopc
uop.iq_type := cs.iq_type
uop.fu_code := cs.fu_code
// x-registers placed in 0-31, f-registers placed in 32-63.
// This allows us to straight-up compare register specifiers and not need to
// verify the rtypes (e.g., bypassing in rename).
uop.ldst := inst(RD_MSB,RD_LSB)
uop.lrs1 := inst(RS1_MSB,RS1_LSB)
uop.lrs2 := inst(RS2_MSB,RS2_LSB)
uop.lrs3 := inst(RS3_MSB,RS3_LSB)
uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)
uop.dst_rtype := cs.dst_type
uop.lrs1_rtype := cs.rs1_type
uop.lrs2_rtype := cs.rs2_type
uop.frs3_en := cs.frs3_en
uop.ldst_is_rs1 := uop.is_sfb_shadow
// SFB optimization
when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {
uop.lrs2_rtype := RT_FIX
uop.lrs2 := inst(RD_MSB,RD_LSB)
uop.ldst_is_rs1 := false.B
} .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {
uop.uopc := uopMOV
uop.lrs1 := inst(RD_MSB, RD_LSB)
uop.ldst_is_rs1 := true.B
}
when (uop.is_sfb_br) {
uop.fu_code := FU_JMP
}
uop.fp_val := cs.fp_val
uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?
uop.mem_cmd := cs.mem_cmd
uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))
uop.mem_signed := !inst(14)
uop.uses_ldq := cs.uses_ldq
uop.uses_stq := cs.uses_stq
uop.is_amo := cs.is_amo
uop.is_fence := cs.is_fence
uop.is_fencei := cs.is_fencei
uop.is_sys_pc2epc := cs.is_sys_pc2epc
uop.is_unique := cs.inst_unique
uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)
uop.bypassable := cs.bypassable
//-------------------------------------------------------------
// immediates
// repackage the immediate, and then pass the fewest number of bits around
val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))
uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))
//-------------------------------------------------------------
uop.is_br := cs.is_br
uop.is_jal := (uop.uopc === uopJAL)
uop.is_jalr := (uop.uopc === uopJALR)
// uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)
// uop.is_ret := (uop.uopc === uopJALR) &&
// (uop.ldst === X0) &&
// (uop.lrs1 === RA)
// uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&
// (uop.ldst === RA)
//-------------------------------------------------------------
io.deq.uop := uop
}
/**
* Smaller Decode unit for the Frontend to decode different
* branches.
* Accepts EXPANDED RVC instructions
*/
class BranchDecodeSignals(implicit p: Parameters) extends BoomBundle
{
val is_ret = Bool()
val is_call = Bool()
val target = UInt(vaddrBitsExtended.W)
val cfi_type = UInt(CFI_SZ.W)
// Is this branch a short forwards jump?
val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))
// Is this instruction allowed to be inside a sfb?
val shadowable = Bool()
}
class BranchDecode(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val inst = Input(UInt(32.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val out = Output(new BranchDecodeSignals)
})
val bpd_csignals =
freechips.rocketchip.rocket.DecodeLogic(io.inst,
List[BitPat](N, N, N, N, X),
//// is br?
//// | is jal?
//// | | is jalr?
//// | | |
//// | | | shadowable
//// | | | | has_rs2
//// | | | | |
Array[(BitPat, List[BitPat])](
JAL -> List(N, Y, N, N, X),
JALR -> List(N, N, Y, N, X),
BEQ -> List(Y, N, N, N, X),
BNE -> List(Y, N, N, N, X),
BGE -> List(Y, N, N, N, X),
BGEU -> List(Y, N, N, N, X),
BLT -> List(Y, N, N, N, X),
BLTU -> List(Y, N, N, N, X),
SLLI -> List(N, N, N, Y, N),
SRLI -> List(N, N, N, Y, N),
SRAI -> List(N, N, N, Y, N),
ADDIW -> List(N, N, N, Y, N),
SLLIW -> List(N, N, N, Y, N),
SRAIW -> List(N, N, N, Y, N),
SRLIW -> List(N, N, N, Y, N),
ADDW -> List(N, N, N, Y, Y),
SUBW -> List(N, N, N, Y, Y),
SLLW -> List(N, N, N, Y, Y),
SRAW -> List(N, N, N, Y, Y),
SRLW -> List(N, N, N, Y, Y),
LUI -> List(N, N, N, Y, N),
ADDI -> List(N, N, N, Y, N),
ANDI -> List(N, N, N, Y, N),
ORI -> List(N, N, N, Y, N),
XORI -> List(N, N, N, Y, N),
SLTI -> List(N, N, N, Y, N),
SLTIU -> List(N, N, N, Y, N),
SLL -> List(N, N, N, Y, Y),
ADD -> List(N, N, N, Y, Y),
SUB -> List(N, N, N, Y, Y),
SLT -> List(N, N, N, Y, Y),
SLTU -> List(N, N, N, Y, Y),
AND -> List(N, N, N, Y, Y),
OR -> List(N, N, N, Y, Y),
XOR -> List(N, N, N, Y, Y),
SRA -> List(N, N, N, Y, Y),
SRL -> List(N, N, N, Y, Y)
))
val cs_is_br = bpd_csignals(0)(0)
val cs_is_jal = bpd_csignals(1)(0)
val cs_is_jalr = bpd_csignals(2)(0)
val cs_is_shadowable = bpd_csignals(3)(0)
val cs_has_rs2 = bpd_csignals(4)(0)
io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA
io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat("b00?01") && GetRd(io.inst) === X0
io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),
ComputeJALTarget(io.pc, io.inst, xLen))
io.out.cfi_type :=
Mux(cs_is_jalr,
CFI_JALR,
Mux(cs_is_jal,
CFI_JAL,
Mux(cs_is_br,
CFI_BR,
CFI_X)))
val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))
// Is a sfb if it points forwards (offset is positive)
io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U
io.out.sfb_offset.bits := br_offset
io.out.shadowable := cs_is_shadowable && (
!cs_has_rs2 ||
(GetRs1(io.inst) === GetRd(io.inst)) ||
(io.inst === ADD && GetRs1(io.inst) === X0)
)
}
/**
* Track the current "branch mask", and give out the branch mask to each micro-op in Decode
* (each micro-op in the machine has a branch mask which says which branches it
* is being speculated under).
*
* @param pl_width pipeline width for the processor
*/
class BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
// guess if the uop is a branch (we'll catch this later)
val is_branch = Input(Vec(pl_width, Bool()))
// lock in that it's actually a branch and will fire, so we update
// the branch_masks.
val will_fire = Input(Vec(pl_width, Bool()))
// give out tag immediately (needed in rename)
// mask can come later in the cycle
val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))
val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))
// tell decoders the branch mask has filled up, but on the granularity
// of an individual micro-op (so some micro-ops can go through)
val is_full = Output(Vec(pl_width, Bool()))
val brupdate = Input(new BrUpdateInfo())
val flush_pipeline = Input(Bool())
val debug_branch_mask = Output(UInt(maxBrCount.W))
})
val branch_mask = RegInit(0.U(maxBrCount.W))
//-------------------------------------------------------------
// Give out the branch tag to each branch micro-op
var allocate_mask = branch_mask
val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))
for (w <- 0 until pl_width) {
// TODO this is a loss of performance as we're blocking branches based on potentially fake branches
io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)
// find br_tag and compute next br_mask
val new_br_tag = Wire(UInt(brTagSz.W))
new_br_tag := 0.U
tag_masks(w) := 0.U
for (i <- maxBrCount-1 to 0 by -1) {
when (~allocate_mask(i)) {
new_br_tag := i.U
tag_masks(w) := (1.U << i.U)
}
}
io.br_tag(w) := new_br_tag
allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)
}
//-------------------------------------------------------------
// Give out the branch mask to each micro-op
// (kill off the bits that corresponded to branches that aren't going to fire)
var curr_mask = branch_mask
for (w <- 0 until pl_width) {
io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)
curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)
}
//-------------------------------------------------------------
// Update the current branch_mask
when (io.flush_pipeline) {
branch_mask := 0.U
} .otherwise {
val mask = Mux(io.brupdate.b2.mispredict,
io.brupdate.b2.uop.br_mask,
~(0.U(maxBrCount.W)))
branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask
}
io.debug_branch_mask := branch_mask
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
| module BranchDecode_3( // @[decode.scala:623:7]
input clock, // @[decode.scala:623:7]
input reset, // @[decode.scala:623:7]
input [31:0] io_inst, // @[decode.scala:625:14]
input [39:0] io_pc, // @[decode.scala:625:14]
output io_out_is_ret, // @[decode.scala:625:14]
output io_out_is_call, // @[decode.scala:625:14]
output [39:0] io_out_target, // @[decode.scala:625:14]
output [2:0] io_out_cfi_type, // @[decode.scala:625:14]
output io_out_sfb_offset_valid, // @[decode.scala:625:14]
output [5:0] io_out_sfb_offset_bits, // @[decode.scala:625:14]
output io_out_shadowable // @[decode.scala:625:14]
);
wire [31:0] io_inst_0 = io_inst; // @[decode.scala:623:7]
wire [39:0] io_pc_0 = io_pc; // @[decode.scala:623:7]
wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22]
wire _io_out_is_ret_T_6; // @[decode.scala:695:72]
wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:623:7]
wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:623:7]
wire _io_out_is_call_T_3; // @[decode.scala:694:47]
wire [39:0] _io_out_target_T_16; // @[decode.scala:697:23]
wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:700:8]
wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:710:76]
wire _io_out_shadowable_T_11; // @[decode.scala:712:41]
wire io_out_sfb_offset_valid_0; // @[decode.scala:623:7]
wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:623:7]
wire io_out_is_ret_0; // @[decode.scala:623:7]
wire io_out_is_call_0; // @[decode.scala:623:7]
wire [39:0] io_out_target_0; // @[decode.scala:623:7]
wire [2:0] io_out_cfi_type_0; // @[decode.scala:623:7]
wire io_out_shadowable_0; // @[decode.scala:623:7]
wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53]
wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36]
wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23]
wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77]
wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23]
wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77]
wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23]
wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77]
wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23]
wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77]
wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23]
wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77]
wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:689:34, :690:35, :694:32]
wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:623:7]
wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:694:65]
assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:694:{32,47,65}]
assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:623:7, :694:47]
wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:623:7]
wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:695:51]
wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:695:51]
wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:690:35, :695:{32,51}]
wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:695:90]
assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:695:{32,72,90}]
assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:623:7, :695:72]
wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:623:7]
wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:623:7]
wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:623:7, :710:50]
wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:337:{27,35}]
wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:623:7]
wire _br_offset_T = io_inst_0[7]; // @[decode.scala:623:7, :708:30]
wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:623:7]
wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:623:7]
wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:623:7, :708:42]
wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:623:7]
wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:623:7, :708:58]
wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:337:{22,68}]
wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:337:{22,27,46}]
wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:337:{22,55}]
wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:337:22]
wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:337:22, :338:27]
wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:338:{10,17,27}]
wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:338:17]
wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:338:17]
wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:338:{17,42}]
wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:338:42]
wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:338:{42,52}]
wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:343:{27,35}]
wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:623:7]
wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:623:7]
wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:623:7]
wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:343:{22,69,82}]
wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:343:22]
wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:343:{22,27,46}]
wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:343:{22,59}]
wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:343:22]
wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:343:22, :344:27]
wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:344:{10,17,27}]
wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:344:17]
wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:344:17]
wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:344:{17,42}]
wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:344:42]
wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:344:{42,52}]
assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:688:33, :697:23]
assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:623:7, :697:23]
wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:688:33, :704:8]
wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:689:34, :702:8, :704:8]
assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:690:35, :700:8, :702:8]
assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:623:7, :700:8]
wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:708:{22,58}]
wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:708:{22,30,42}]
wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:708:22]
wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:710:{42,50}]
wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:688:33, :710:{39,42}]
wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:708:22, :710:68]
wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:710:{39,55,68}]
wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:708:22, :710:90]
wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:710:{90,117}]
assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:710:{55,76,117}]
assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:623:7, :710:76]
assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:623:7, :708:22, :711:27]
wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:692:35, :713:5]
wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:714:22]
wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:713:{5,17}, :714:22]
wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:623:7, :715:14]
wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:715:14]
wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:695:90, :715:41]
wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:715:{14,22,41}]
wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:713:17, :714:42, :715:22]
assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:691:41, :712:41, :714:42]
assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:623:7, :712:41]
assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:623:7]
assign io_out_is_call = io_out_is_call_0; // @[decode.scala:623:7]
assign io_out_target = io_out_target_0; // @[decode.scala:623:7]
assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:623:7]
assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:623:7]
assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:623:7]
assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:623:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i1_e8_s24_41(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_41 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File btb.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128,
useFlops: Boolean = false
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rmeta = Wire(Vec(nWays, Vec(bankWidth, new BTBMeta)))
val s1_req_rbtb = Wire(Vec(nWays, Vec(bankWidth, new BTBEntry)))
val s1_req_rebtb = Wire(UInt(vaddrBitsExtended.W))
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
val s1_targs = Wire(Vec(nWays, Vec(bankWidth, UInt(vaddrBitsExtended.W))))
for (w <- 0 until bankWidth) {
for (b <- 0 until nWays) {
val entry_btb = WireInit(s1_req_rbtb(b)(w))
s1_targs(b)(w) := Mux(entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
}
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := s1_targs(s1_hit_ways(w))(w)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f1(w) := io.resp_in(0).f1(w)
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
if (params.useFlops) {
for (w <- 0 until nWays) {
val meta = Reg(Vec(nSets, Vec(bankWidth, new BTBMeta)))
val btb = Reg(Vec(nSets, Vec(bankWidth, new BTBEntry)))
s1_req_rmeta(w) := meta(s1_idx)
s1_req_rbtb(w) := btb(s1_idx)
for (i <- 0 until bankWidth) {
when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {
when (doing_reset || s1_update_wbtb_mask(i)) {
btb(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,
0.U.asTypeOf(new BTBEntry), s1_update_wbtb_data)
}
when (doing_reset || s1_update_wmeta_mask(i)) {
meta(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,
0.U.asTypeOf(new BTBMeta), s1_update_wmeta_data(i))
}
}
}
}
val ebtb = Reg(Vec(extendedNSets, UInt(vaddrBitsExtended.W)))
s1_req_rebtb := ebtb(s1_idx)
} else {
for (w <- 0 until nWays) {
val meta = SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W)))
val btb = SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W)))
meta.suggestName(s"btb_meta_way_${w}")
btb.suggestName(s"btb_data_way_${w}")
s1_req_rmeta(w) := VecInit(meta.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta)))
s1_req_rbtb(w) := VecInit(btb.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBEntry)))
when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {
btb.write(
Mux(doing_reset, reset_idx, s1_update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wbtb_mask).asBools
)
meta.write(
Mux(doing_reset, reset_idx, s1_update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wmeta_mask).asBools
)
}
}
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
ebtb.suggestName(s"btb_ebtb")
s1_req_rebtb := ebtb.read(s0_idx, s0_valid)
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
}
}
| module btb_data_way_1( // @[btb.scala:192:29]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [55:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [55:0] W0_data,
input [3:0] W0_mask
);
btb_data_way_0_ext btb_data_way_0_ext ( // @[btb.scala:192:29]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[btb.scala:192:29]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_113( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueueSource_Phit_6( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35]
mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35]
mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35]
mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35]
mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35]
mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35]
mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35]
mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35]
mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_66( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLFIFOFixer_2( // @[FIFOFixer.scala:50:9]
input clock, // @[FIFOFixer.scala:50:9]
input reset, // @[FIFOFixer.scala:50:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_privileged_0 = auto_anon_in_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_secure_0 = auto_anon_in_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_user_amba_prot_fetch_0 = auto_anon_in_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] _a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_id_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_id_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [15:0] _allIDs_FIFOed_T = 16'hFFFF; // @[FIFOFixer.scala:127:48]
wire [2:0] auto_anon_in_a_bits_param = 3'h0; // @[Nodes.scala:27:25]
wire [2:0] auto_anon_out_a_bits_param = 3'h0; // @[Nodes.scala:27:25]
wire [2:0] anonIn_a_bits_param = 3'h0; // @[Nodes.scala:27:25]
wire [2:0] anonOut_a_bits_param = 3'h0; // @[Nodes.scala:27:25]
wire auto_anon_in_a_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29]
wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _stalls_T_9 = 1'h0; // @[FIFOFixer.scala:88:71]
wire _stalls_T_10 = 1'h0; // @[FIFOFixer.scala:88:65]
wire stalls_0 = 1'h0; // @[FIFOFixer.scala:88:50]
wire _stalls_T_20 = 1'h0; // @[FIFOFixer.scala:88:71]
wire _stalls_T_21 = 1'h0; // @[FIFOFixer.scala:88:65]
wire stalls_1 = 1'h0; // @[FIFOFixer.scala:88:50]
wire _stall_T = 1'h0; // @[FIFOFixer.scala:91:45]
wire stall = 1'h0; // @[FIFOFixer.scala:91:45]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_id_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _stalls_a_sel_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_6 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire _anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire _anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire _anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_bufferable = auto_anon_in_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_modifiable = auto_anon_in_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_readalloc = auto_anon_in_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_writealloc = auto_anon_in_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_privileged = auto_anon_in_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_secure = auto_anon_in_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_user_amba_prot_fetch = auto_anon_in_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9]
wire _anonOut_a_valid_T_2 = anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29]
wire [3:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source; // @[Parameters.scala:52:29]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign anonOut_a_bits_user_amba_prot_bufferable = anonIn_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_modifiable = anonIn_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_readalloc = anonIn_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_writealloc = anonIn_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_privileged = anonIn_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_secure = anonIn_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_user_amba_prot_fetch = anonIn_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign _anonIn_a_ready_T_2 = anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}]
wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T; // @[Decoupled.scala:51:35]
assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T_4; // @[Decoupled.scala:51:35]
assign _stalls_id_T_4 = _T_5; // @[Decoupled.scala:51:35]
wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg flight_0; // @[FIFOFixer.scala:79:27]
reg flight_1; // @[FIFOFixer.scala:79:27]
reg flight_2; // @[FIFOFixer.scala:79:27]
reg flight_3; // @[FIFOFixer.scala:79:27]
reg flight_4; // @[FIFOFixer.scala:79:27]
reg flight_5; // @[FIFOFixer.scala:79:27]
reg flight_6; // @[FIFOFixer.scala:79:27]
reg flight_7; // @[FIFOFixer.scala:79:27]
reg flight_8; // @[FIFOFixer.scala:79:27]
reg flight_9; // @[FIFOFixer.scala:79:27]
reg flight_10; // @[FIFOFixer.scala:79:27]
reg flight_11; // @[FIFOFixer.scala:79:27]
reg flight_12; // @[FIFOFixer.scala:79:27]
reg flight_13; // @[FIFOFixer.scala:79:27]
reg flight_14; // @[FIFOFixer.scala:79:27]
reg flight_15; // @[FIFOFixer.scala:79:27]
wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _stalls_a_sel_T = anonIn_a_bits_source[3]; // @[Parameters.scala:54:10]
wire _stalls_a_sel_T_5 = anonIn_a_bits_source[3]; // @[Parameters.scala:54:10]
wire _stalls_a_sel_T_1 = ~_stalls_a_sel_T; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35]
wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}]
wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_1 = flight_0 | flight_1; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_2 = _stalls_T_1 | flight_2; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_3 = _stalls_T_2 | flight_3; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_4 = _stalls_T_3 | flight_4; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_5 = _stalls_T_4 | flight_5; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_6 = _stalls_T_5 | flight_6; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_7 = _stalls_T_6 | flight_7; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}]
wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel_1 = _stalls_a_sel_T_8; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1; // @[Decoupled.scala:51:35]
wire _stalls_id_T_7 = _stalls_id_T_5; // @[FIFOFixer.scala:85:{47,56}]
wire _stalls_T_11 = stalls_a_sel_1 & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_12 = flight_8 | flight_9; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_13 = _stalls_T_12 | flight_10; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_14 = _stalls_T_13 | flight_11; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_15 = _stalls_T_14 | flight_12; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_16 = _stalls_T_15 | flight_13; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_17 = _stalls_T_16 | flight_14; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_18 = _stalls_T_17 | flight_15; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18; // @[FIFOFixer.scala:88:{15,26,44}]
assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [15:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [15:0] SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [15:0] SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [15:0] _SourceIdSet_T = 16'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T : 16'h0; // @[OneHot.scala:58:35]
wire [15:0] _SourceIdClear_T = 16'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T : 16'h0; // @[OneHot.scala:58:35]
wire [15:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35]
wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[FIFOFixer.scala:50:9]
if (reset) begin // @[FIFOFixer.scala:50:9]
a_first_counter <= 9'h0; // @[Edges.scala:229:27]
d_first_counter <= 9'h0; // @[Edges.scala:229:27]
flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
SourceIdFIFOed <= 16'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[FIFOFixer.scala:50:9]
if (_a_first_T) // @[Decoupled.scala:51:35]
a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (_d_first_T) // @[Decoupled.scala:51:35]
d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21]
flight_0 <= ~(_T_3 & anonIn_d_bits_source == 4'h0) & (_T_1 & anonIn_a_bits_source == 4'h0 | flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_1 <= ~(_T_3 & anonIn_d_bits_source == 4'h1) & (_T_1 & anonIn_a_bits_source == 4'h1 | flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_2 <= ~(_T_3 & anonIn_d_bits_source == 4'h2) & (_T_1 & anonIn_a_bits_source == 4'h2 | flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_3 <= ~(_T_3 & anonIn_d_bits_source == 4'h3) & (_T_1 & anonIn_a_bits_source == 4'h3 | flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_4 <= ~(_T_3 & anonIn_d_bits_source == 4'h4) & (_T_1 & anonIn_a_bits_source == 4'h4 | flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_5 <= ~(_T_3 & anonIn_d_bits_source == 4'h5) & (_T_1 & anonIn_a_bits_source == 4'h5 | flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_6 <= ~(_T_3 & anonIn_d_bits_source == 4'h6) & (_T_1 & anonIn_a_bits_source == 4'h6 | flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_7 <= ~(_T_3 & anonIn_d_bits_source == 4'h7) & (_T_1 & anonIn_a_bits_source == 4'h7 | flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_8 <= ~(_T_3 & anonIn_d_bits_source == 4'h8) & (_T_1 & anonIn_a_bits_source == 4'h8 | flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_9 <= ~(_T_3 & anonIn_d_bits_source == 4'h9) & (_T_1 & anonIn_a_bits_source == 4'h9 | flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_10 <= ~(_T_3 & anonIn_d_bits_source == 4'hA) & (_T_1 & anonIn_a_bits_source == 4'hA | flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_11 <= ~(_T_3 & anonIn_d_bits_source == 4'hB) & (_T_1 & anonIn_a_bits_source == 4'hB | flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_12 <= ~(_T_3 & anonIn_d_bits_source == 4'hC) & (_T_1 & anonIn_a_bits_source == 4'hC | flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_13 <= ~(_T_3 & anonIn_d_bits_source == 4'hD) & (_T_1 & anonIn_a_bits_source == 4'hD | flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_14 <= ~(_T_3 & anonIn_d_bits_source == 4'hE) & (_T_1 & anonIn_a_bits_source == 4'hE | flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_15 <= ~(_T_3 & (&anonIn_d_bits_source)) & (_T_1 & (&anonIn_a_bits_source) | flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
TLMonitor_19 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_bufferable (anonIn_a_bits_user_amba_prot_bufferable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_modifiable (anonIn_a_bits_user_amba_prot_modifiable), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_readalloc (anonIn_a_bits_user_amba_prot_readalloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_writealloc (anonIn_a_bits_user_amba_prot_writealloc), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_privileged (anonIn_a_bits_user_amba_prot_privileged), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_secure (anonIn_a_bits_user_amba_prot_secure), // @[MixedNode.scala:551:17]
.io_in_a_bits_user_amba_prot_fetch (anonIn_a_bits_user_amba_prot_fetch), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_bufferable = auto_anon_out_a_bits_user_amba_prot_bufferable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_modifiable = auto_anon_out_a_bits_user_amba_prot_modifiable_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_readalloc = auto_anon_out_a_bits_user_amba_prot_readalloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_writealloc = auto_anon_out_a_bits_user_amba_prot_writealloc_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_privileged = auto_anon_out_a_bits_user_amba_prot_privileged_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_secure = auto_anon_out_a_bits_user_amba_prot_secure_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_user_amba_prot_fetch = auto_anon_out_a_bits_user_amba_prot_fetch_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_135( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
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